PHILIPS UCB1510

UCB1510
AC97 digital modem codec
Rev. 01 — 4 February 2000
Preliminary specification
1. Description
The UCB1510 is a single chip, integrated mixed signal telecom codec that can
directly be connected to a DAA and supports high speed modem protocols. The
general purpose I/O pins provide programmable inputs and/or outputs to the system.
The UCB1510 has a serial AClink interface intended to communicate to the system
controller. Both the codec input data and codec output data and the control register
data are multiplexed on this interface.
2. Features
c
c
■ Sigma delta telecom codec with programmable sample rate, including digitally
controlled input voltage level, mute, loop back and clip detection functions. The
telecom codec can be directly connected to a Data Access Arrangement (DAA)
and includes a built in sidetone suppression circuit
■ AClink (rev 2.1) interface with secondary codec support
■ 3.3 V supply voltage and built in power saving modes make the UCB1510 optimal
for portable and battery powered applications
■ 5 V tolerant interface for motherboard/PC add on
■ Maximum operating current 25 mA
■ 8 general purpose IO pins for line interface control
■ Interrupt detection driven wake up sequence for ring detect
■ Low cost 12.288 MHz crystal
3. Applications
■
■
■
■
Standalone modems
Integrated modems
Audio/Modem Riser (AMR) Cards
Mobile Daughter Cards (MDC)
UCB1510
Philips Semiconductors
AC97 digital modem codec
4. Ordering information
Table 1:
Ordering information
Type number
Package
UCB1510DB
Name
Description
Version
SSOP28
plastic shrink small outline package, 28 leads, body width 5.3mm
SOT341-1
5. Block diagram
A0
ADC
down
sample
filter
DAC
up
sample
filter
TINP
Line1 PCM flow
PON
Serial bus
interface
TINN
SDOUT
SDIN
SYNC
TOUTP
data /
control
registers
RESET
BIT_CLK
TOUTN
Clock buffers &
sample rate
dividers
Voltage
reference
VREFBYP
GPIO
XTAL_IN/A1
IO[7:0]
XTAL_OUT
Fig 1. Block diagram
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
2 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
6. Pinning information
6.1 Pinning
VDDD
1
28
XTAL_OUT
IO0
2
27
XTAL_IN/A1
IO1
3
26
VSSA
IO2
4
25
TINN
IO3
5
24
TINP
RESET
6
23
VREFBYP
A0
7
22
TOUTN
PON
8
21
TOUTP
SYNC
9
20
VDDA
SDOUT 10
19
VSSD
VSSD 11
18
IO7
SDIN 12
17
IO6
BIT_CLK 13
16
IO5
VDDD 14
15
IO4
UCB1510
Fig 2. Pin configuration
6.2 Pin description
Table 2:
Pin description
Symbol
Pin
Reset
state [1]
Type [2]
Description
VDDD
1
-
S
digital supply
IO0
2
input
I/OC
general purpose I/O pins
IO1
3
input
I/OC
general purpose I/O pins
IO2
4
input
I/OC
general purpose I/O pins
IO3
5
input
I/OC
general purpose I/O pins
RESET
6
-
IC
asynchronous reset input
A0
7
-
IC
address select (for secondary codec) inverted polarity
PON
8
-
IC
asynchronous cold reset
SYNC
9
-
I/OC
AClink synchronization input
SDOUT
10
-
IC
AClink data input
VSSD
11
-
S
digital ground
SDIN
12
0 [4]
OC
AClink data output
13
- [3]
I/OC
AClink serial interface clock
BIT_CLK
VDDD
14
-
S
digital supply
IO4
15
input
I/OC
general purpose I/O pins
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
3 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
Table 2:
Pin description…continued
Symbol
Pin
Reset
state [1]
Type [2]
Description
IO5
16
input
I/OC
general purpose I/O pins
IO6
17
input
I/OC
general purpose I/O pins
IO7
18
input
I/OC
general purpose I/O pins
VSSD
19
-
S
digital ground
VDDA
20
-
S
analog supply
TOUTP
21
hi Z
OA
positive telecom codec output
TOUTN
22
hi Z
OA
negative telecom codec output
VREFBYP
23
hi Z
I/OA
external reference voltage bypass
TINP
24
-
IA
positive telecom codec input
TINN
25
-
IA
negative telecom codec input
VSSA
26
-
S
analog ground
XTAL_IN/A1
27
- [3]
IA/IC
Xtal oscillator/master clock input or inverted
secondary address
XTAL_OUT
28
- [3]
OA
Xtal oscillator output
[1]
[2]
[3]
[4]
After cold or warm reset, the AClink interface is active with MLNK bit reset.
I/OC = CMOS bidirectional; ID = digital input; S = supply; OA = analog output; IC = CMOS input;
IA = analog input; I/OA = analog bidirectional; OC = CMOS output.
BIT_CLK is an input for AClink secondary codec, an output for primary codec. When BIT_CLK is an
output, the XTAL oscillator is active.
SDIN is driving a 0 until a valid SYNC framing signal is received after cold reset.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
4 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
7. Functional description
The functional description of the devices id described in Section 8 through
Section 15.
8. Telecom codec
The telecom codec contains an input channel, built up from a 64 times oversampling
sigma delta analog to digital converter (ADC) with digital decimation filters,
programmable gain and attenuation and built-in sidetone suppression circuit.
The output path consists of a digital up sample filter, a 64 time oversampling 4 bit
digital to analog converter (DAC) circuit with integrated filter followed by a differential
output driver, capable of directly driving a 600 Ω isolation transformer. The output
path includes a mute function. The telecom codec also incorporates loop back
modes, in which codec output path and the input path are connected in series. The
loop back tap and entry points are identified as circled letters in Figure 3, loop back
modes are described in the AClink register definition.
sidetone_enable
TINP
TINN
ADC[3:2]
ADC
SIDETONE
J
SUPPRESSION
H
CIRCUIT
DIGITAL
DECIMATION
FILTER
14
G
TOUTP
D
E
DAC
TOUTN
C
DIGITAL
NOISE
SHAPER
14
B
DAC Mute
Fig 3. Telecom codec block diagram
The telecom sample rate (fst) is derived from the AC master clock and is
programmable using the sample rate registers. Not all AC97 specified sample rates
are supported, refer to Table 3 “Sampling frequencies” for details.
PCM data is transferred in the slot 5 of the AClink.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
5 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
Table 3:
Sampling frequencies
Sampling frequency (Hz)
Register 0x40
value
Support
AC ‘97
requirements
7200
0x1C20
no
recommended
8000
0x1F40
yes
required
8228.57 (57600/7)
0x2024
no
recommended
8400
0x20D0
no
recommended
9000
0x2328
no
recommended
9600
0x2580
yes
required
10285.71 (72000/7)
0x282D
no
recommended
12000
0x2EE0
yes
recommended
13714.29 (96000/7)
0x3592
yes
required
16000
0x3E80
yes
required
19200
0x4B00
yes
recommended
24000
0x5DC0
yes
recommended
48000
0xBB80
no
recommended
Any programmed vlaue above 24 kHz will lead to a 24 kHz sampling rate.
Changing the sampling rate while the codec is active may lead to unpredictable
results in the ADC and DAC chains and should be avoided.
The output section of the telecom codec is designed to interface with a 600 Ω line
through an isolation transformer. The built in mute function is activated by the
DAC Mute bit in register 0x46. The output driver remains active in the mute mode,
however no output signal is produced.
8.1 Digital filters
These filters are tailored for high speed modem performance.
A voice band filter can be activated to reduce the noise in the lower frequencies.
Table 4:
Filter characteristics
Parameter
Condition
Group delay
25 samples
Pass band ripple
±0.1 dB
Out of band rejection
>0.55 fs
-50 dB
Pass band
(no voice band filter)
0.0016 to 0.45 fs
Transition band
0.45 to 0.55 fs
Voice band filter rejection band
0-0.0018 fs
Voice band filter cutoff frequency
30 dB
0.05 fs
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Value
Rev. 01 — 4 February 2000
6 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
8.2 Analog interface
UCB1510
Ro
TOUTP
Rg
TINP
1:1 transformer
A
Ri
Rt
Rs
Rt
Rt
Rs
Central Office
Rt
B
Ri
+
+
-
TINN
Rg
Ro
TOUTN
Fig 4. Typical telecom codec sidetone suppression circuit (without protection circuits).
An important built-in feature of the telecom codec is the sidetone suppression circuit.
The sidetone suppression circuit is activated when sidetone_enable of register 0x5A
is set.The sidetone suppression circuit subtracts part of the telecom output signal
from the telecom input signal. As a result the available dynamic range of the input
path can be more effectively utilized. If the sidetone suppression circuit is disabled,
the telecom input dynamic range can be largely occupied by the telecom output
signal.
The built-in side tone suppression circuit, shown in Figure 4, has a fixed subtraction
ratio, set be the resistors Rs and Ri, which equals 600⁄456. This ratio is calculated from
the following relations.
The impedance seen by the telephone line equals:
Ro × Ri
Z line = 2 ×  R t + R t + ------------------ , differential, in which Rt represents winding resistance

R +R
o
i
of the transformer, divided by 2. Assuming Ri >> Ro, then
R line = R t + R t + R o = 600 ⁄ 2 = 300Ω single ended.
A typical transformer has 156 Ω winding impedance, thus Ro should be 144 Ω. The
ratio of the telecom input and output voltage is, therefore:
456
156 + 300
V i(tel) = V o(tel) × --------------------------------------- = V o(tel) × --------600
156 + 300 + 144
Proper sidetone suppression thus requires Rs/Ri to be Vi/Vo.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
7 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
9. On-chip reference circuit
The UCB1510 contains an on chip reference voltage source, which generates the
bias currents and the virtual analog ground. Alternatively the UCB1510 can be driven
from an external reference voltage source.
Bias ENA
vref_external
internal
analog
ground
&
ena
internal
bandgap Vbg
reference
voltage
circuitry
&
vref_bypass
VREFBYP
Fig 5. Block diagram of the reference circuit.
Two bits in the control register 0x5A determine the mode of operation of this
reference voltage circuit. vref_bypass connects the internal reference voltage to the
VREFBYP pin, while vref_external disables the internal reference voltage and
switches the UCB1510 into the external voltage reference mode.
If the internal reference voltage is connected to the VREFBYP pin, an external
capacitor could be connected to filter this reference voltage. When choosing a
capacitor, the internal impedance (around 50 kΩ) should be taken into account.
If vref_external is set, an external voltage reference connected to the VREFBYP pin
is used as the voltage reference by UCB1510.
10. Power supply strategy
Since all the control logic of the UCB1510 is powered by the VDDD, power should
always be present on this pin for interrupts to be possible. VDDA needs not be present
all the time although it is recommended to use the control bits to turn OFF the analog
sections.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
8 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
11. Register definition
11.1 Supported registers
Table 5:
Supported registers
Register
Name
0x00 to 0x3A
All audio registers are ignored
0x3C
Extended Modem ID
0x3E
Extended Modem Status and Control
0x40
Line1 DAC/ADC Rate
0x42 and 0x44
Reserved for future use
0x46
Line1 DAC/ADC Level
0x48 and 0x4A
Reserved for future use
0x4C
GPIO Pin Configuration
0x4E
GPIO Pin Polarity
0x50
GPIO Pin Sticky
0x52
GPIO Pin Wake-up Mask
0x54
GPIO Pin Status
0x56
Miscellaneous Modem AFE Status and Control
0x58
Ignored
0x5A
Codec control
0x5C
Mode control
0x5E
Test control
0x5E to 0x7A
Ignored
0x7C
Vendor ID1
0x7E
Vendor ID2
11.2 Register detail
Shaded areas indicate read only data.
11.2.1
Extended Modem ID
Table 6: Extended Modem ID Register
Register address: 0x3C; default: N/A
Bit
D15
D14
Symbol
ID1
ID0
Bit
D7
D6
D13
D12
D11
D10
D9
D5
D4
D3
D2
D1
D0
0
0
0
0
LIN1
Symbol
Table 7:
Description of Extended Modem ID bits
Bit
Symbol Function/Value
D15:14
ID[1:0]
{A1,A0} where A0 is the inverse polarity of the A0 pin. A1 is the inverse
polarity of XTAL_IN pin if A0 is HIGH (A0 pin is LOW), otherwise A1 is 0.
D0
LIN1
Line 1 support indicator = 1 (i.e., Line 1 is supported).
[1]
Writing this register will cause a register reset: all modem registers will then take their default values.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
D8
Rev. 01 — 4 February 2000
9 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
11.2.2
Extended Modem Status and Control
Table 8: Extended Modem Status and Control Register
Register address: 0x3E; default: 0xFFxx
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Symbol
PRH
PRG
PRF
PRE
PRD
PRC
PRB
PRA
D7
D6
D5
D4
D3
D2
D1
D0
HDAC
HADC
DAC2
ADC2
DAC1
ADC1
MREF
GPIO
Bit
Symbol
Table 9:
11.2.3
Description of Extended Modem status and Control bits
Bit
Symbol Function/Value
D15
PRH
D14
PRG
Reserved, should be 1
D13
PRF
Reserved, should be 1
D12
PRE
Reserved, should be 1
D11
PRD
1 -> Line1 DAC OFF
D10
PRC
1 -> Line1 ADC OFF
D9
PRB
1 -> Line1 VREF OFF
D8
PRA
1 -> GPIO OFF
D7
HDAC
0 (not supported)
D6
HADC
0 (not supported)
D5
DAC2
0 (not supported)
D4
ADC2
0 (not supported)
D3
DAC1
1 indicates Line1 DAC ready (means that the Line1 DAC and the VREF
are enabled and ready)
D2
ADC1
1 indicates Line1 ADC ready (means that the Line1 ADC and the VREF
are enabled and ready)
D1
MREF
1 indicates Line1 VREF up to nominal level.
D0
GPIO
1 indicates GPIO ready.
Reserved, should be 1
Line 1 Sample Rate
Table 10: Line 1 Sample Rate Register
Register address: 0x40; default: 0x1F40
Bit
Symbol
Bit
Symbol
D15
D14
D13
D12
D11
D10
D9
D8
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
D7
D6
D5
D4
D3
D2
D1
D0
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
Refer to Table 3 “Sampling frequencies” for supported sample rates.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
10 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
11.2.4
Line 1 DAC/ADC Level
Table 11: Line 1 DAC/ADC Level Register
Register address: 0x46; default: 0x8080
Bit
D15
Symbol
DAC
mute
Bit
Symbol
D7
D14
D13
D12
D11
D10
D9
D8
D6
D5
D4
D3
D2
D1
D0
ADC3
ADC2
ADC1
ADC0
ADC
mute
Table 12: Description of Line1 DAC/ADC Level bits
11.2.5
Bit
Symbol
Function/Value
D15
DAC mute
DAC section is active, but no signal will be sent.
D7
ADC mute ADC section is active, but no signal will be sent.
D3-D2
ADC[3:2]
ADC Gain (0 -> 0 dB, 1 -> 6 dB, 2 -> 12 dB, 3 -> 18 dB)
D1-D0
ADC[1:0]
These bits are ignored.
GPIO Pin Configuration
Table 13: GPIO Pin Configuration Register
Register address: 0x4C; default: 0x00FF
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GC7
GC6
GC5
GC4
GC3
GC2
GC1
GC0
Symbol
Bit
Symbol
The GPIO Pin Configuration register specifies whether a GPIO pin is configured for
input (1) or for output (0).
11.2.6
GPIO Pin Polarity
Table 14: GPIO Pin Polarity Register
Register address: 0x4E; default: 0xFFFF
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
Symbol
Bit
Symbol
The GPIO Pin Polarity register defines GPIO Input Polarity (0 = Low, 1 = High) when
a GPIO pin is configured as an input.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
11 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
11.2.7
GPIO Pin Sticky
Table 15: GPIO Pin Sticky Register
Register address: 0x50; default: 0x0000
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GS7
GS6
GS5
GS4
GS3
GS2
GS1
GS0
Symbol
Bit
Symbol
The GPIO Pin Sticky register defines GPIO Input Type (0 = Non-Sticky, 1 = Sticky)
when a GPIO pin is configured as input. Sticky is defined as Edge sensitive,
Non-Sticky as Level-sensitive.
GPIO inputs configured as Sticky are cleared by writing a 0 to the corresponding bit
of the GPIO Pin Status register 0x54, and by reset.
Remark: Changing GPIO control registers while a GPIO is sticky may cause
unwanted interrupts and should be done carefully.
11.2.8
GPIO Wake-up Mask
Table 16: GPIO Wake-up Mask Register
Register address: 0x52; default: 0x0000
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GW7
GW6
GW5
GW4
GW3
GW2
GW1
GW0
Symbol
Bit
Symbol
The GPIO Pin Wake-up Mask register provides a mask for determining if an input
GPIO change will generate a wake-up or GPIO_INT (0 = No, 1 = Yes).
When the AC-link is powered down, a wake-up event will trigger the assertion of
SDIN. When the AC-link is powered up, a wake-up event will appear as
GPIO_INT = 1 on bit 0 of input slot 12.
11.2.9
GPIO Pin Status
Table 17: GPIO Pin Status Register
Register address: 0x54; default: N/A
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Symbol
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Symbol
GI7
GI6
GI5
GI4
GI3
GI2
GI1
GI0
The GPIO Status register reflects the state of all GPIO pins (inputs and outputs) on
slot 12.
When the GPIO is an output pin, the value set on slot #12 is transmitted directly to the
pin. When the GPIO pin is a non-sticky input, the status of the pin is accessible in
read mode. When the GPIO is a sticky Input, a transition, either from high to low
(polarity = 0) or from low-to-high (polarity = 1), will assert the corresponding GI bit
to 1. The GI bit will remain asserted until it is cleared by a write of 0.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
12 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
11.2.10
Miscellaneous Modem AFE Status and Control
Table 18: Miscellaneous Modem AFE Status and Control Register
Register address: 0x56; default: 0x0000
Bit
D15
D14
Symbol
Bit
D13
D12
D11
MLNK
D7
D6
Symbol
D5
D10
D9
D8
reserved, should be 0x0
D4
D3
reserved, should be 0x0
D2
D1
D0
L1B2
L1B1
L1B0
Table 19: Description of Miscellaneous Modem AFE Status and Control bits
Bit
Symbol
Function/Value
D13
MLNK
1 -> AClink goes to sleep.
D[2:0]
L1B[2:0]
Line1 loop back modes (refer to Table 20).
Table 20: Loop back modes
See Figure 3.
Mode
Description
0
Disabled
1
ADC loop back (incoming analog signal is amplified, digitized, down-sampled,
LOOPED, up-sampled, converted to analog, amplified/filtered) (G) to (B) loop.
2
Local analog loop back (digital signal is up-sampled, converted to analog,
amplified/filtered, LOOPED, amplified, digitized, down-sampled, sent back) (E)
to (J) loop.
3
DAC loop back (digital signal is up-sampled, converted to analog, LOOPED
digitized, down-sampled, sent back) (E) to (J) loop. Same as mode 2.
4
Remote analog loop back (incoming analog signal is amplified, LOOPED,
amplified/filtered, sent back) (J) to (D) loop.
7
Digital loop back: signal is captured from the AC-link and sent back as is. Slot
request for slot#5 is controlled according to the programmed sampling rate.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
13 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
11.2.11
Vendor Specific Codec Control
Table 21: codec_control Register
Register address: 0x5A; default: 0x0400
Bit
D15
D14
D13
D12
Symbol
D11
AC
Bit
Symbol
D10
D9
D8
ME
VE
VB
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
SE
0
0
0
VF
Table 22: codec_control bits
11.2.12
Bit
Symbol
Function/Value
D12
AC
adc_clip, in read mode, this bit indicates clipping in the line1 ADC.
This indicator is sticky and should be cleared by writing it with a 0.
D10
ME
reserved, should be 1
D9
VE
vref_external, overwrites VB
D8
VB
vref_bypass
D[7:5],
D[3:1]
0
Bits marked ‘0’ are reserved for future use and should be programmed
with 0.
D4
SE
sidetone_enable
D0
VF
voice_filter:1->enable voice band digital filter.
Vendor Specific Mode Control
Table 23: mode_control Register
Register address: 0x5C; default: 0x0000
Bit
D15
D14
D13
D12
D11
D10
Symbol
Bit
D7
Symbol
[1]
D9
D8
reserved: 0x0
D6
D5
D4
0
0
0
D3
D2
D1
D0
0
BITSTREAM
Bits marked 0 are reserved for future use and should be programmed with 0.
Table 24: mode_control bits
11.2.13
Bit
Symbol
D0
BITSTREAM line1 ADC bitstream data is sent directly to IO4. The associated
clock is sent to IO6.
Function/Value
Vendor specific Test Control
Table 25: Test_control Register
Register address: 0x5E; default: N/A
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Symbol
Bit
Symbol
This register cannot be reset. It has no effect until the IC is put in vendor test mode
(see Table 29 “Mode selection with AC pins”).
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AC97 digital modem codec
11.2.14
Vendor ID1
Table 26: Vendor ID1 Register
Register address: 0x7C; default: 0x5053
Bit
Symbol
Bit
Symbol
11.2.15
D15
D14
D13
D12
D11
D10
D9
D8
0
1
0
1
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
1
Vendor ID2
Table 27: Vendor ID2 Register
Register address: 0x7E; default: 0x4301
Bit
Symbol
Bit
Symbol
D15
D14
D13
D12
D11
D10
D9
D8
0
1
0
0
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
11.3 Register reset modes
11.3.1
Warm reset
When a warm reset is activated, MLNK is set to 0 but the other registers retain their
values. If the codec is primary, the BIT_CLK is started and stabilized after 200 ms.
11.3.2
Cold reset
When a cold reset is activated, MLNK is set to 0 and all registers are programmed to
their default values. If the codec is primary, the BIT_CLK is started and stabilized
after 200 ms.
11.3.3
Register reset
A register reset causes all registers to return to their default values. Initiated by a
write to register 0x3C.
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AC97 digital modem codec
12. AC97 interface
12.1 Control register data transfer
The AClink frames is made of 13 slots. Slot0 is a 16-bit long tag slot, the remaining 12
slots are 20-bit long data transfer.
48KHz
SYNC
20bits
#5
#6
#7
#8
#9
#10
#11
#12
#0
SLOT #12: I/O CTRL
#4
SLOT #6.. #9:
not supported by UCB1510
#3
SLOT #5: LINE1 DAC
#2
SLOT #3 & #4:
not supported by UCB1510
#1
SLOT #2: CMD DATA
#0
SLOT #0: TAG
SDOUT (SLOT #)
16 bits
SLOT #1: CMD ADDR
Clock:12.288MHz
Fig 6. AClink frame slot definition
Register update is done at the end of slot 2. The new register value is effective
thereafter.
Slot #0 and slot #3 to #12 are shared by all codecs (primary and secondary). Multiple
codecs using the same slot cannot be used at the same time. Slot #1 and slot #2 are
used for register transfer and are codec specific. Addressing is defined in the
Tag slot #0: The UCB1510 will send a 1 as Tag slot bit 15 whenever the AClink is
active (MLNK is 0).
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Bit 15: Register index[3]
Bit 16: Register index[4]
SLOT #0
Bit 17: Register index[5]
5
4
3
2
1
0 19 18 17 16 15
Bit 15: Register index[3]
Bit 16: Register index[4]
Bit 17: Register index[5]
Bit 18: Register index[6]
Bit 0: Codec ID A0
Bit 19: Read/Write (1-> read)
SLOT #0
Bit 18: Register index[6]
Bit 1: Codec ID A1
1
Bit 0: 0
Bit 19: Register_read
BIT_CLK
Bit 2: Unused, set to 0
2
Bit 1: 0
SYNC
Bit3: If 1 then Slot #12 (I/O Control) is valid
3
Bit 2: Unused, set to 0
16 BIT_CLKs
Bit 4: If 1 then SLot #11 s valid - should be 0 for UCB1510
Bit 6: If 1 then Slot #9 is valid - should be 0 for UCB1510
Bit7: If 1 then Slot #8 is valid - should be 0 for UCB1510
Bit 8: If 1 then Slot #7 is valid - should be 0 for UCB1510
4
Bit3: If 1 then Slot #12 (I/O Control) is valid
Fig 7. Tag slot bit definition (controller to codec)
Bit 5: If 1 then Slot #10 is valid - should be 0 for UCB1510
6
5
Bit 4: 0
7
6
Bit 5: 0
8
7
Bit 6: 0
0 15 14 13 12 11 10 9
8
Bit7: I0
Bit 9: If 1 then Slot #6 is valid - should be 0 for UCB1510
Bit 10: If 1 then Slot #5 (Line 1) is valid
Bit 11: If 1 then Slot #4 is valid - should be 0 for UCB1510
Bit 12: If 1 then Slot #3 is valid - should be 0 for UCB1510
Bit 13: If 1 then Slot #2 (CMD_DATA) is valid
Bit 14: If 1 then Slot #1 (CMD_ADDR) is valid
0 15 14 13 12 11 10 9
Bit 8: 0
Bit 9: 0
Bit 10: If 1 then Slot #5 is valid
Bit 11: 0
Bit 12: 0
SDIN
(bit numbers)
Bit 13: If 1 then Slot #2 (CMD_DATA) is valid
Bit 15: If 1 then Valid Frame; if 0 then frame can be ignored
SDOUT
(bit numbers)
Bit 14: If 1 then Slot #1 (CMD_ADDR) is valid
Bit 15: If 1 then Valid Frame; if 0 then frame can be ignored
Philips Semiconductors
UCB1510
AC97 digital modem codec
16 BIT_CLKs
SYNC
BIT_CLK
0 19 18 17 16 15
SLOT #1
SLOT #1
Fig 8. Tag slot bit definition (codec to controller)
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12.2 Codec addressing
Table 28: Codec addressing examples
CMD ADDR
CMD DATA
Codec ID
(A1, A0)
Read/Write
Transfer
Description
slot #0
bit 14
slot #0
bit 13
slot #0
bits 1 and 0
slot #1
bit 19
0
0
00
x
idle
No register data is transferred, slots 1
and 2 are not valid
1
x
1
1
00
1
primary read
Read for primary codec register
00
0
primary write
Write to a primary codec register
x
x
01
1
secondary read
Read from the 01 secondary codec
register
x
x
11
0
secondary write
Write to a 11 secondary codec register
12.2.1
Primary codec addressing
For addressing a primary codec, bits 1 and 0 of the Tag slot (codec ID A1 and A0)
should be 0. The bits 13 and 14 are used for register data transfer. When the
controller is not sending/receiving control data, it should be addressing the primary
codec. When writing to a register, the bits 14 and 13 (ADDR and DATA valid) should
be set to 1. When reading from a register, only the bit 14 is required to be 1.
12.2.2
Secondary codec addressing
When the Codec ID (A1,A0) is not 00, the controller is addressing a secondary codec
in a read or write sequence. The direction is defined in the slot 1 read/write bit (bit
19).
12.3 PCM sample transfer
Since the AClink frame frequency is defined to be 48kHz, exchanging samples with
the controller at a different sampling rate requires the support of on demand sample
transfer (slot request). The UCB1510 will send samples to the controller and assert
the slot 5 valid bit in the slot#0 (bit10)of the AClink frame. When it needs a new
sample from the controller, it will put a 0 on the slot5req bit in the slot#1 (bit9) of the
AClink frame. When the slot5req bit is 1, it indicates to the controller that no new
sample is needed. When the DAC is not active, the slot5req bit is kept at 0.
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12.4 Interrupt request from UCB1510
MLNK
BIT_CLK
SDIN
Interrupt request
Interrupt request
is enabled
Fig 9. Setting the SDIN for interrupt request
12.4.1
When BIT_CLK is running
The AClink is active and the interrupt request is transmitted by setting the interrupt bit
of slot 12 in the AClink frame.
If UCB1510 is configured as a primary codec, this is the case when MLNK is set to 0.
If UCB1510 is configured as a secondary codec, this is the case whether MLNK is set
to 0 or 1.
12.4.2
When BIT_CLK is stopped
In order to request an interrupt, the UCB1510 will assert the SDIN pin, if MLNK is set
to 1. BIT_CLK is not needed for this to happen. This applies when UCB1510 is used
as a primary or secondary codec.
If UCB1510 is configured as a primary codec, BIT_CLK is stopped as a result of
MLNK being set to 1.
If UCB1510 is configured as a secondary codec, BIT_CLK is stopped when the
controller shuts down the primary codec. For UCB1510 to generate interrupt while
BIT_CLK is stopped, MLNK has to be set to 1 before BIT_CLK is stopped.
After BIT_CLK is stopped, SDIN will be brought to 0, unless an interrupt asserts it
to 1. It is recommended that a level triggered interrupt detection is used in case the
interrupt request is asserted at the same time BIT_CLK is stopped.
12.5 Wake-up request to the UCB1510
A cold reset will program the registers to their default value and will wake up the
AClink.
When the AClink is not active (no BIT_CLK present), a rising SYNC will cause a
warm reset. If MLNK is set to 1, a rising RESET will also cause a warm reset. After a
warm reset, MLNK will be reset to 0.
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AC97 digital modem codec
13. General purpose I/O
The UCB1510 has 8 programmable digital input/output (I/O) pins. These pins can be
independently programmed for polarity, value, direction and interrupt through the
GPIO control registers.
14. Interrupt generation
The UCB1510 contains a programmable interrupt control block.
The internal interrupt signal presents the 'OR' function of all interrupt status bits and
can be used to give an interrupt to the system controller using the AClink interrupt
protocol
The interrupt controller is implemented asynchronously. This provides the possibility
to generate interrupts when BIT_CLK is stopped, e.g. an interrupt can be generated
in power down mode, when the state of one of the IO pins changes (e.g. ring detect).
15. Reset circuit and mode selection
The AC97 specification rev 2.1 describes a number of states and reset functions for a
modem codec either in primary or secondary codec.
15.1 Resets
15.1.1
Pulling the PON pin LOW
The PON pin acts as a hardware reset and is typically connected to a power
detection circuit.
15.1.2
Activating the RESET pin
Pulling the RESET pin low will start a cold or a warm reset sequence.
If the circuit is active (MLNK = 0). A cold reset is started. The reset sequence will end
after the rising edge of RESET. Only then will the AClink be available. Vendor test
modes are inactive as soon as the reset sequence starts so that mode sensing is
possible.
If the MLNK bit is set when the RESET pin is pulled low, a warm reset is activated
when RESET goes high again.
15.1.3
Activating the SYNC pin when AClink is inactive
When the AClink is not active (no BIT_CLK present), a rising SYNC will cause a
warm reset.
15.1.4
Writing reg 0x3C
When written, the reg 0x3C will initiate a register reset. All registers are set to their
default values.
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AC97 digital modem codec
15.2 Vendor test modes
When starting a RESET pin induced cold reset, the AClink pins are sensed for
Vendor Test mode selection. BIT_CLK does not need to be running at that moment
Table 29: Mode selection with AC pins
SYNC
SDOUT
Mode
0
0
Normal mode, the AClink is operating properly.
0
1
ATE test mode. All AClink pins are set to input thus allowing
board level JTAG testing.
1
0
Vendor test mode.
1
1
ATE test mode.
When the vendor test mode is activated, the vendor test register takes action. This
mode is for test only and should not be used in normal operation. Exiting this mode
requires a cold reset.
15.3 Primary/secondary codec selection
Secondary codec implementation is selected by wiring the A0 pin low.
When A0 is low (A0 is 1), the XTAL_IN is used as A1 thus allowing ‘01’ and ‘11’ as
secondary addresses. ‘10’ is not possible. The ID register will then reflect the A1,A0.
Details can be found in the description of register 0x3C.
When the UCB1510 is a secondary codec, it derives its internal clock from BIT_CLK.
BITCLK is therefore configured as input.
16. Limiting values
Table 30: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). [1].
Symbol
Parameter
Min
Max
Unit
VDD
supply voltage
−0.5
+4.0
V
Vi
DC input voltage
−0.5
VDD + 0.5
V
Vo
DC output voltage
−
VDD + 0.5
V
Ii(d)
diode input current
−
10
mA
Io(d)
diode output current
−
10
mA
Io
continuous output current,
digital outputs
−
4
mA
Tstg
storage temperature
−55
+150
°C
[1]
[2]
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any conditions
other than those described in the Absolute Maximum Rating section of this specification is not implied
Parameters are valid over the ambient operating temperature unless otherwise specified. All voltages
are with respect to VSSD, unless otherwise noted.
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Conditions
[2]
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AC97 digital modem codec
17. Thermal characteristics
Table 31: Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from junction
to ambient in free air
Value
Unit
55
K/W
18. Static characteristics
Table 32: Static characteristics
VSSD = VSSA1 = 0 V; Tamb =25 °C; all voltages referenced to VSSD; unless otherwise specified.
Symbol
Parameter
VDDD
digital supply voltage
VDDA1
analog supply voltage
Conditions
Min
Typ
Max
Unit
3.0
3.3
3.6
V
3.6
V
3.0
3.3
[1]
−
19
[1]
−
IDDD
digital supply current
IDDA1
digital supply current
full functionality
IDDA2
analog supply current
Power down,
only oscillator is on
VIL
LOW level input voltage
VIH
HIGH level input voltage
VOL
LOW level output voltage
IOL = 4 mA
VOH
HIGH level output voltage
IOH = 4 mA
0.8VDDD
fBIT_CLK
serial interface clock frequency
Tamb
operating ambient temperature
[1]
−
mA
−
mA
+0.2VDDD
V
t.b.d.
−0.5
−
0.8VDDD
−
0.5VDDD
V
−
−
0.4
V
−
−
V
12.288
−20
−
MHz
70
°C
Indicative value measured during the initial characterization.
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Philips Semiconductors
AC97 digital modem codec
19. Dynamic characteristics
Table 33: Dynamic characteristics
VSSD = VSSA = 0 V; VDDD = VDDA = 3.3 V ±10%; Tamb = 25 °C; VI(ref) = 1.2 V; fBIT_CLK = 12.288 MHz; unless otherwise
specified.
Symbol
Telecom
Parameter
Conditions
Min
Typ
Max
Unit
−
8
−
kHz
330
370
410
mV
input [1]
fst
sample frequency
Vi(rms)
input voltage (RMS value)
differentially applied to TINN
and TINP; ADC[3:2] = 1 (6 dB)
in register 0x46
Vi(bias)
DC bias voltage
TINN/TINP
αi
input gain
input gain step size
2 LSBs ignored, Bit 3 step
1.2
−
1.6
V
0
6
18
dB
4
6
8
dB
25
−
−
kΩ
Zi
input impedance
S/N
signal-to-noise ratio
60
75
−
dB
THD
total harmonic distortion
−
−75
−60
dB
LE(d)(ADC)
ADC differential linearity
error
−
−
2
LSB
RES
codec resolution
PBRR
pass-band ripple rejection
SBRvti
stop-band rejection
−
14
−
bit
fplt < fsig < fpht; no voice filter
[3], [6]
−
−
1.2
dB
fvht < fsig < fpht; voice filter
activated
[3], [6]
−
−
1.2
dB
fsig < fvti; voice filter activated
[3], [6]
30
−
−
dB
fsht < fsig
[3], [6]
50
−
−
dB
Doffset
digital offset
no signal applied to input
−
−
50
LSB
Ssup
sidetone suppression
effectiveness
600 Ω line impedance;
1:1 transformer with 156 Ω
winding resistance
20
−
−
dB
−
8
−
kHz
SBRsht
Telecom output
[2]
fst
sample frequency
Vo(rms)
output voltage (RMS value)
differentially measured
between TOUTP and TOUTN
1.35
−
1.85
V
Vo(bias)
DC bias voltage
TOUTP/TOUTN; telecom O/P
path enabled
1.2
−
1.6
V
RES
codec resolution
−
14
−
bit
S/N
signal-to-noise ratio
60
75
−
dB
THD
total harmonic distortion
−
−75
−
dB
PBRR
pass-band ripple rejection
SBR
stop-band rejection
fsht < f < fst
OBR(rms)
out-of-band rejection (RMS
value)
f > fst
Zo(load)
load impedance
Eoffset
−
−
1.2
dB
[4], [6]
50
−
−
dB
−
−
25
mV
600
−
−
Ω
−
−
100
mV
[5]
offset error
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9397 750 06856
Preliminary specification
[4], [6]
Rev. 01 — 4 February 2000
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UCB1510
Philips Semiconductors
AC97 digital modem codec
Table 33: Dynamic characteristics…continued
VSSD = VSSA = 0 V; VDDD = VDDA = 3.3 V ±10%; Tamb = 25 °C; VI(ref) = 1.2 V; fBIT_CLK = 12.288 MHz; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
On-chip reference circuit
Vi(ref)
reference voltage applied to
VREFBYP
1.0
1.2
1.4
V
tSTRTU
start-up time of internal
reference voltage circuit
−
−
1000
ns
Xtal oscillator
fxtal
Operating frequency
12.288
MHz
Zxtal
start-up time of internal
reference voltage circuit
10
kΩ
MHz
AClink control register data transfer
facclk
CLK input frequency
0
12.288
Dacclk
CLK duty factor
−
50
−
%
5
−
−
ns
32 tCLK
−
ns
Reset circuit
tW(NRESET)
RESET pulse width
tW(rst)
internal reset pulse width
[1]
[2]
[3]
[4]
[5]
[6]
Additional test conditions: Fsample = 8 kHz; input signal 1 kHz, 300 mV (RMS); Line1_ADC_ON = 1; TEL_VOICE_ENA = 0,
input gain +6 dB
Additional test conditions: Fsampling 8 kHz; 0 dB output attenuation; 90% of digital full scale input voltage; 1200 Ω load.
See Figure 10.
See Figure 11.
Deviation of the analog output from 0, with 0 code input to telecom output path.
All curves repeat around the sample frequency fsa or fst for telecom codec.
f plt = 0.0016 × f st
PBRR
f pht = 0.42 × f st
0dB
f sht = 0.6 × f st
f vlt = 0.018 × f st
SBRvti
f vht = 0.05 × f st
Voice filter enabled
SBRsht
Fplt
Fvlt
Fvht
Fpht
Fsht
Fig 10. Telecom input frequency response
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Preliminary specification
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AC97 digital modem codec
PBRR
f plt = 0.0016 × f st
0dB
f pht = 0.42 × f st
f sht = 0.6 × f st
SBR
Fplt
Frequency [Hz]
Fpht
Fsht
Fig 11. Telecom output frequency response
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9397 750 06856
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20. Package outline
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
D
SOT341-1
E
A
X
c
HE
y
v M A
Z
28
15
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
14
w M
bp
e
detail X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.1
0.7
8
0o
o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
SOT341-1
JEDEC
EIAJ
MO-150AH
EUROPEAN
PROJECTION
ISSUE DATE
93-09-08
95-02-04
Fig 12. SSOP28 package; SOT341-1.
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21. Soldering
21.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering is not always suitable for surface mount ICs, or for printed-circuit boards
with high population densities. In these situations reflow soldering is often used.
21.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a
conveyor type oven. Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface
temperature of the packages should preferable be kept below 230 °C.
21.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
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Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the
need for removal of corrosive residues in most applications.
21.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
21.5 Package related soldering information
Table 34: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package
Soldering method
BGA, LFBGA, SQFP, TFBGA
Wave
Reflow [1]
not suitable
suitable
suitable [2]
HBCC, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, SMS
not
PLCC [3], SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
[1]
[2]
[3]
[4]
[5]
suitable
suitable
not
recommended [3] [4]
suitable
not
recommended [5]
suitable
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
These packages are not suitable for wave soldering as a solder joint between the printed-circuit board
and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top
version).
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger
than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
22. Revision history
Table 35: Revision history
Rev Date
01
991111
CPCN
Description
-
Converted to DBII format.
The format of this specification has been redesigned to comply with Philips Semiconductors’
new presentation and information standard.
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
28 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
23. Data sheet status
Product status
Definition [1]
Objective specification
Development
This data sheet contains the design target or goal specifications for product development. Specification may
change in any manner without notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any
time without notice in order to improve design and supply the best possible product.
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
24. Definitions
25. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
© Philips Electronics N.V. 2000 All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
29 of 32
D
Datasheet status
UCB1510
Philips Semiconductors
AC97 digital modem codec
NOTES
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
30 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
Philips Semiconductors - a worldwide company
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Yugoslavia: Tel. +381 11 62 5344, Fax. +381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications,
Building BE, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 272 4825
Internet: http://www.semiconductors.philips.com
(SCA68)
© Philips Electronics N.V. 2000. All rights reserved.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
31 of 32
UCB1510
Philips Semiconductors
AC97 digital modem codec
Contents
1
2
3
4
5
6
6.1
6.2
7
8
8.1
8.2
9
10
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.2.9
11.2.10
11.2.11
11.2.12
11.2.13
11.2.14
11.2.15
11.3
11.3.1
11.3.2
11.3.3
12
12.1
12.2
12.2.1
12.2.2
12.3
12.4
12.4.1
12.4.2
12.5
13
14
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 5
Telecom codec . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Analog interface . . . . . . . . . . . . . . . . . . . . . . . . 7
On-chip reference circuit . . . . . . . . . . . . . . . . . 8
Power supply strategy. . . . . . . . . . . . . . . . . . . . 8
Register definition . . . . . . . . . . . . . . . . . . . . . . . 9
Supported registers . . . . . . . . . . . . . . . . . . . . . 9
Register detail. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Extended Modem ID . . . . . . . . . . . . . . . . . . . . . 9
Extended Modem Status and Control. . . . . . . 10
Line 1 Sample Rate . . . . . . . . . . . . . . . . . . . . 10
Line 1 DAC/ADC Level . . . . . . . . . . . . . . . . . . 11
GPIO Pin Configuration . . . . . . . . . . . . . . . . . 11
GPIO Pin Polarity . . . . . . . . . . . . . . . . . . . . . . 11
GPIO Pin Sticky . . . . . . . . . . . . . . . . . . . . . . . 12
GPIO Wake-up Mask . . . . . . . . . . . . . . . . . . . 12
GPIO Pin Status . . . . . . . . . . . . . . . . . . . . . . . 12
Miscellaneous Modem AFE Status and Control 13
Vendor Specific Codec Control. . . . . . . . . . . . 14
Vendor Specific Mode Control . . . . . . . . . . . . 14
Vendor specific Test Control. . . . . . . . . . . . . . 14
Vendor ID1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Vendor ID2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register reset modes . . . . . . . . . . . . . . . . . . . 15
Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Cold reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register reset . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC97 interface . . . . . . . . . . . . . . . . . . . . . . . . . 16
Control register data transfer . . . . . . . . . . . . . 16
Codec addressing. . . . . . . . . . . . . . . . . . . . . . 18
Primary codec addressing . . . . . . . . . . . . . . . 18
Secondary codec addressing . . . . . . . . . . . . . 18
PCM sample transfer . . . . . . . . . . . . . . . . . . . 18
Interrupt request from UCB1510. . . . . . . . . . . 19
When BIT_CLK is running . . . . . . . . . . . . . . . 19
When BIT_CLK is stopped . . . . . . . . . . . . . . . 19
Wake-up request to the UCB1510 . . . . . . . . . 19
General purpose I/O. . . . . . . . . . . . . . . . . . . . . 20
Interrupt generation. . . . . . . . . . . . . . . . . . . . . 20
© Philips Electronics N.V. 2000.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 4 February 2000
Document order number: 9397 750 06856
15
Reset circuit and mode selection . . . . . . . . . .
15.1
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.1
Pulling the PON pin LOW . . . . . . . . . . . . . . . .
15.1.2
Activating the RESET pin . . . . . . . . . . . . . . . .
15.1.3
Activating the SYNC pin when AClink is
inactive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1.4
Writing reg 0x3C . . . . . . . . . . . . . . . . . . . . . . .
15.2
Vendor test modes . . . . . . . . . . . . . . . . . . . . .
15.3
Primary/secondary codec selection . . . . . . . .
16
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .
17
Thermal characteristics. . . . . . . . . . . . . . . . . .
18
Static characteristics . . . . . . . . . . . . . . . . . . . .
19
Dynamic characteristics . . . . . . . . . . . . . . . . .
20
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
21
Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.1
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.2
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . .
21.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . .
21.4
Manual soldering. . . . . . . . . . . . . . . . . . . . . . .
21.5
Package related soldering information . . . . . .
22
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .
24
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
20
20
21
21
21
22
22
23
26
27
27
27
27
28
28
28
29
29
29