PHILIPS UCB1100

INTEGRATED CIRCUITS
UCB1100
Advanced modem/audio analog front-end
Preliminary specification
Supersedes data of 1996 Apr 09
Version 1.2
1998 May 08
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
Version 1.2
GENERAL DESCRIPTION
TABLE OF CONTENTS
The UCB1100 is a single chip, integrated mixed signal audio and
telecom codec. The single channel audio codec is designed for
direct connection of a microphone and speaker. The built-in telecom
codec can directly be connected to a DAA and supports high speed
modem protocols. The incorporated 10 bit analogue to digital
converter and the touch screen interface provides complete control
and readout of a connected 4 wire resistive touch screen. The 10
additional general purpose I/O pins provides programmable inputs
and/or outputs to the system.
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.0
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . 3
2.0
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.0
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . 4
4.0
DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 5
5.0
PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.1
PINLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.0
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 8
6.1
AUDIO CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.1.1 AUDIO INPUT SPECIFICATIONS . . . . . . . . 10
6.1.2 AUDIO OUTPUT SPECIFICATIONS . . . . . . . 11
6.2
TELECOM CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2.1 TELECOM INPUT SPECIFICATIONS . . . . . 14
6.2.2 TELECOM OUTPUT SPECIFICATIONS . . . 15
6.3
TOUCH SCREEN MEASUREMENT MODES . . . . 16
6.3.1 POSITION MEASUREMENT . . . . . . . . . . . . . 16
6.3.2 PRESSURE MEASUREMENT . . . . . . . . . . . 16
6.3.3 PLATE RESISTANCE MEASUREMENT . . . 16
6.4
TOUCH SCREEN INTERFACE . . . . . . . . . . . . . . . . . 17
6.4.1 TOUCH SCREEN SPECIFICATIONS . . . . . 18
6.5
10 BIT ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5.1 SPECIFICATION OVERVIEW . . . . . . . . . . . . 21
6.6
ON CHIP REFERENCE CIRCUIT . . . . . . . . . . . . . . 21
6.6.1 SPECIFICATION OVERVIEW . . . . . . . . . . . . 21
6.7
SERIAL INTERFACE BUS . . . . . . . . . . . . . . . . . . . . . 22
6.7.1 SIB DATA FORMAT . . . . . . . . . . . . . . . . . . . . . 23
6.7.2 CODEC DATA TRANSFER . . . . . . . . . . . . . . 24
6.7.3 CONTROL REGISTER DATA TRANSFER . 26
6.7.4 AC ELECTRICAL CHARACTERISTICS . . . 27
6.8
GENERAL PURPOSE I/Os . . . . . . . . . . . . . . . . . . . . 27
6.9
INTERRUPT GENERATION . . . . . . . . . . . . . . . . . . . 27
6.10 RESET CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.0
MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
POWER ROUTING STRATEGY . . . . . . . . . . . . . . . . 29
8.0
CONTROL REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . 30
9.0
PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1
PACKAGE OUTLINE LQFP48 . . . . . . . . . . . . . . . . . . 34
10.0 DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
The UCB1100 has a serial interface bus (SIB) intended to
communicate to the system controller. Both the codec input and
output data and the control register data is multiplexed on this SIB
interface.
APPLICATIONS
• Personal Intelligent Communicators
• Personal Digital Assistants (PDA)
• Screen phones
• Smart Phone and smart Fax
• Intelligent Communicators
KEY FEATURES
• 48-pin LQFP (SOT313-2) small body SMD package and low
external component count result in minimal PCB space
requirement.
• A 12-bit sigma delta audio codec with programmable sample rate,
input and output voltage levels, capable of connecting directly to
speaker and microphone, including digitally controlled mute,
loopback and clip detection functions
• A 14-bit sigma delta telecom codec with programmable sample
rate, including digitally controlled input voltage level, mute,
loopback and clip detection functions. The telecom codec is
intended for direct connection to a DAA (digital access
arrangement) and includes a built-in sidetone suppression circuit.
• A complete 4 wire resistive touch screen interface circuit
supporting position, pressure and plate resistance measurements.
• A 10-bit successive approximation ADC with internal track and
hold circuit and analogue multiplier for touch screen readout and
monitoring of four external high voltage (7.5V) analogue voltages.
• A high speed, 4 wire serial interface data bus (SIB) for
communication to system controller.
• A 3.3V supply voltage and built in power saving modes make the
UCB1100 optimal for portable and battery powered applications.
1998 May 08
2
1998 May 08
3
Figure 1. Block Diagram of the UCB1100
ad0
ad1
ad2
ad3
tsmx
tspy
tsmy
vssa3
supply pin
analog pin
1 bit ADC
64fsa
1 bit ADC
effect
64fsa
digital
noise
shaper
9 to 1
track & hold
control
power
10 bit ADC
10
64fst
divtel0:6]
sample
frequency
divider
fst
internal
reset
stretcher
reset
Interrupt
controller
decoder
serial bus
controller
serial bus
encoder
serial bus
sync
enable
adc
start
IOwdat[0:9]
IOrdat[0:9]
io0 io1 io2 io3 io4 io5 io6 io7 io8 io9
Programmable IO pin block
IOmode[0:9]
eanble data
interrupt data
for all
from other blocks
analog blocks
clear_interrupt[0:15]
rising_edge_ena[0:15]
falling_edge_ena[0:15]
adc_sync_ena
stop logic
adcsync
64fsa
sample
frequency
divider
fsa
fs
divaud[0:6]
ADC start
to external register 11
voltage
bias voltage
mux
fs
12
telecom output enable
14
14
fs
telecom input enable
digital
decimation
filter
external
filter
digital
noise
shaper
12
fs
attn[4,5]
audio_output_enable
digital
volume
control
digital
decimation
filter
reference
4
64fs
4
64fs
4
64fs
1
64fs
audio_input_enable
touch screen
external
reference
effect
4 bit DAC
TELECOM CODEC
attenuation
attn[0,3]
4 bit DAC
AUDIO CODEC
gain[0,2]
test
irqout
nreset
sibdin
sibclk
sibsync
sibdout
Advanced modem/audio analog front-end
digital pin
switched
voltage
dividers
switch matrix
touch screen
mute
mux
loopback
mute
mux
loopback
to all other analog and digital blocks
vrefbyp
side tone suppression
echo on
vssa1
gain[3,4]
control data registers
toutp
toutn
tinp
tinn
vssa2
spkrp
spkrn
vdda2
micgnd
micp
Vssa1 Vdda1 2xVssd 2xVddd
Philips Semiconductors
Preliminary specification
UCB1100
1.0 FUNCTIONAL BLOCK DIAGRAM
SN00126
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
2.0 ORDERING INFORMATION
DESCRIPTION
ORDERING
CODE
PACKAGE
DRAWING
Plastic low profile
quad flat package;
48 leads
UCB1100LP/X3
SOT313-2
3.0 ABSOLUTE MAXIMUM RATINGS
SYMBOL
MIN
MAX
UNIT
Supply voltage
–0.5
5.0
V
DC input voltage, except AD0–3 inputs
–0.5
VDD+0.5
V
VADMAX
DC input voltage AD0–3 inputs
–0.5
8.5
V
VOMAX
DC output voltage
–0.5
VDD+0.5
V
VDDMAX
VIMAX
PARAMETER
IIKMAX
DC diode input current, all inputs
10
mA
IOKMAX
DC diode output current
10
mA
IOLMAX
Continuous output current, digital outputs
4
mA
150
°C
Tstg
Storage temperature
–55
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the Absolute Maximum Rating section of this
specification is not implied.
2. This product includes circuitry specially designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid submitting the UCB1100 to conditions exceeding the maximum
ratings.
3. Parameters are valid over the operating ambient temperature unless otherwise specified. All voltages are with respect to the VSSD pin,
unless otherwise noted.
1998 May 08
4
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
4.0 DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to 70°C, VSSD = VSSA1 = VSSA2 = VSSA3 = 0V, sibclk = 10MHz, audio_divisor = 12, telecom_divisor = 40.
Voltage with respect to the VSSD pin, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
NOTES
UNIT
MIN
TYP
MAX
VDDD
digital supply voltage
3.0
3.3
3.6
V
VDDA1
analogue supply voltage (excl.speaker driver)
3.0
3.3
3.6
V
VDDA2
analogue supply voltage (speaker driver only)
3.0
3.3
3.6
V
VSSA2
analogue ground voltage wrt. VSSD
–0.4
0
0.4
V
VSSA3
analogue ground voltage wrt VSSD
–0.4
0
0.4
V
10
mA
mA
mA
mA
mA
µA
IDDD
IDDA1
IDDA2
digital supply current,
full functionality
only audio codec activated
only telecom codec activated
only touch screen activated
only adc activated
no functions activated, sibclk stopped
Note 1
19
17
19
15
15
analogue supply current,
full functionality
only audio codec activated
only telecom codec activated
only touch screen activated
only adc activated
no analogue functions activated
Note 1, Note 2
total speaker driver supply current
full functionality
only audio codec activated
only telecom codec activated
only touch screen activated
only adc activated
no analogue functions activated
Note 1, Note 2
3.8
1.5
1.7
0.4
0.5
<10
mA
mA
mA
mA
mA
µA
0.2
0.2
mA
mA
µA
µA
µA
µA
10
10
10
10
VTSCB
touch screen bias voltage
ITSCB
maximum touch screen bias current
1.8
V
VADFS
full scale voltage ad0–ad3 inputs
7.5
V
VTSFS
full scale input touch screen inputs
7.5
V
10
mA
VIL
input low voltage
–0.5
0.3*VDDD
V
VIH
input high voltage
0.7*VDDD
VDDD+0.5
V
VOL
output low voltage
IOL=2mA
0.2*VDDD
V
VOH
output high voltage
IOH=2mA
fSIBCLK
Tamb
clock frequency
0
Operating Ambient Temperature
0
NOTES:
1. Indicative value only. Value will be frozen following silicon measurements.
2. Excluding connected touch screen and speaker load currents.
1998 May 08
0.8*VDDD
5
V
10
15
MHz
70
°C
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
37 vssd
38 nreset
39 sibsync
40 sibdout
41 sibclk
42 sibdin
43 irqout
44 not used
45 io4
46 io5
47 io6
48 vddd
5.0 PINOUT
io7
1
36 io3
io8
2
35 io2
io9
3
34 io1
adcsync
4
33 io0
vssd
5
not used
6
vssa2
7
spkrn
8
29 tsmy
sprkp
9
28 tsmx
vdda2 10
27 tspy
32 vddd
UCB1100
LQFP48
31 not used
30 tspx
TOP VIEW
ad1 24
ad2 23
ad3 22
micp 21
micgnd 20
not used 19
vssa1 18
vdda1 17
vrefbyp 16
tinp 15
25 ad0
tinn 14
26 vssa3
toutn 12
test 13
toutp 11
SN00127
Figure 2. LQFP48 (SOT313-2)
1998 May 08
6
UCB1100
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
5.1 Pinlist
PINNING
SYMBOL
PIN TYPE
LQFP48
RESET
STATE
DESCRIPTION
NOTE
vddd
32, 48
supply
digital supply
vssd
5, 37
ground
digital ground
vdda1
17
supply
analogue supply
vssa1
18
ground
analogue ground
vdda2
10
supply
analogue speaker driver supply
vssa2
7
ground
analogue speaker driver ground
vssa3
26
ground
touch screen switch matrix ground
sibclk
41
CMOS input
SIB serial interface master clock
sibdin
42
CMOS input
SIB data input
sibdout
40
CMOS output
sibsync
39
CMOS input
irqout
43
CMOS output
active-High
‘0’
micp
21
analogue input
Hi-Z
microphone signal input
micgnd
20
analogue input
Hi-Z
microphone ground switch input
sprkp
9
analogue output
Hi-Z
positive speaker output
3
spkrn
8
analogue output
Hi-Z
negative speaker output
3
tinp
15
analogue input
Hi-Z
positive telecom codec input
3
‘0’ / Hi-Z
SIB data output
1
1
2
SIB synchronization
interrupt output
tinn
14
analogue input
Hi-Z
negative telecom codec input
3
toutp
11
analogue output
Hi-Z
positive telecom codec output
3
toutn
12
analogue output
Hi-Z
negative telecom codec output
3
ad0–3
25–22
analogue input
Hi-Z
analogue high voltage inputs
tspx
30
analogue IO
Hi-Z
positive X-plate touch screen
tsmx
28
analogue IO
Hi-Z
negative X-plate touch screen
tspy
27
analogue IO
Hi-Z
positive Y-plate touch screen
tsmy
29
analogue IO
Hi-Z
negative Y-plate touch screen
adcsync
4
digital input
vrefbyp
16
analogue IO
Hi-Z
external reference voltage input, external filter connection
io0–9
33–36,
45–47,
1–3
CMOS IO
input
general purpose IO pins
nreset
38
CMOS input
active-Low
test
13
CMOS input
not used
6, 19,
31, 44
adc synchronization pulse input
asynchronous reset input
‘0’
test mode protection
not connected pins
NOTES:
1. The vssd and vssa1 pins are connected to each other within the UCB1100.
2. The first 64 bits of the sib frame will be ‘0’, the remaining bits in the sib frame will be Hi-Z.
3. The spkrp/spkrn, tinp/tiln and toup/toutn are differential pairs.
4. The test pin contains a internal pull down. This pin should be connected to vssd in normal mode of the UCB1100.
1998 May 08
7
4
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
For example, a serial clock of 10 MHz, with a divisor of 14, results in
an audio sample rate of 22.321kHz. Both the rising and the falling
edges of the sibclk are used in case an odd audio_divisor is set.
Thus a 50% duty cycle of the sibclk signal is mandatory to obtain
time equidistant sampling with odd divisors.
6.0 FUNCTIONAL DESCRIPTION
The UCB1100 consists of several analogue and digital sub circuits
which can be programmed via the Serial Interface Bus (SIB). This
enables the user to set the UCB1100 functionality according actual
application requirements.
The frequency response of the audio codec depends mainly on the
selected sample rate, since the bandwidth is limited in the down and
up sampling filters. These digital filters both contain several FIR and
IIR low pass filters and a DC removal filter (high pass filter). A 1st
order analogue anti aliasing filter is implemented at the input of the
microphone input to prevent aliasing in the adc path. A 3rd order
smoothing filter is implemented between dac and speaker driver
stage to reduce the spurious frequencies at the speaker outputs.
6.1 Audio codec
The audio codec contains an input channel, built up from a 64 times
oversampling sigma delta analogue to digital converter (ADC) with
digital decimation filters and a programmable gain microphone
preamp. The output path consists of a digital up sample filter, a 64
time oversampling 4 bit digital to analogue converter (DAC) circuit
followed by a speaker driver, capable of driving directly a low
impedance bridge tied (BTL) speaker. The output path features
digitally programmable attenuation and a mute function. The audio
codec also incorporates a loopback mode, in which codec output
path and the input path are connected in series.
The audio codec input (=ADC) and output (= DAC) paths can be
enabled individually by setting the audio_adc and/or audio_dac bits
in the audio control register B. These enable bits operate both on
the associated analogue and digital functions, for optimal power
control of both the analogue and the digital parts.
The audio sample rate is derived from the SIB interface clock pin
(SIBclk) and is programmable through the SIB interface. The audio
sample rate is given by the following equation:
Fsa (2 * Fsibclk)
(64 * audio_divisor)
UCB1100
(5 audio_divisor 128)
audio_input_enable
gain[3,4]
micp
loopback
gain[0,2]
64fsa
mux
64fs
1 bit ADC
micgnd
1
loop input
vssa1
fs
round
up
+3dB
16
Sinc4
FIR
interpolator
low pass
FIR
2
DC
removal
2
half band
WDF
half band
FIR
12
half band
WDF
half band
WDF
DC
removal
fs
round
up
4
2
+3dB
2
2
2
noise
shaper
loop input
vdda2
64fs
spkrp
spkrn
4 bit DAC
4
vssa2
12
digital
volume
control
attn[0,3]
mute
64fsa
attn[4,5]
audio_output_enable
SN00128
Figure 3. Detailed Block Diagram Audio codec
1998 May 08
8
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
The output level can be attenuated in 3dB steps down to -69dB. The
8 highest attenuation steps are implemented in the analogue
circuitry, while the two 24dB steps are implemented in the digital
domain. This preserves the ‘audio quality’ of the output signal at
lowest attenuation settings. The speaker driver is muted when the
audio-mute bit in the audio control register B is set. The speaker
driver will remain activated in that case, however no signal is
produced by the speaker driver circuitry.
UCB1100
vdda1
vdda1
micp
micp
micgnd
micgnd
vssa1
vssa1
UCB1100
UCB1100
‘Passive’ Microphone
UCB1100
UCB1100
‘Active’ Microphone
SN00129
spkrp
spkrp
spkrp
spkrn
spkrn
spkrn
Figure 4. Possible Microphone Connections
The UCB1100 audio codec input path accepts microphone signals
directly, only a DC blocking capacitor is needed, since the micp input
is biased around 1.4V. The ‘ground’ side of the microphone is either
connected to the analogue ground (vssa1) or to the micgnd pin of
the UCB1100. The latter will decrease the current consumption of
active microphones, since the micgnd pin is made Hi-Z when the
audio codec input path is disabled.
Bridge Tied
Speaker
Load
The full scale input voltage of the audio input path is programmable
in 1.5dB steps by setting the appropriate data in the audio-input-gain
bits in the audio control register A.
The speaker driver is designed to directly drive a bridge tied load
(BTL). This yields the highest output power and it does not require
external DC blocking capacitors. The speaker driver also accepts
single ended connection of a speaker, in which case the maximum
output power is reduced to a quarter of the BTL situation.
Consequently this way of connecting the speaker to the speaker
driver reduces the power consumption of the speaker driver in the
UCB1100 by a factor of 2. Figure 6 shows possible ways to connect
a speaker to the UCB1100.
The audio input and output path are activated independently; the
input path is enabled when the audio-input-enable bit is set, the
output path is enabled when the audio-output-enable bit is set in the
audio control register B. This provides the user the means to reduce
the current consumption of the UCB1100 if one part of the audio
codec is not used in the application.
digital attenuation
48dB
24dB
The audio codec has a loopback mode for system test purposes,
which is activated when the audio_loopback enable bit in the audio
control register B is set. This is an analogue loopback which
internally connects the output of the audio output path to the input of
the audio input path, (see Figure 3). In this mode the normal
microphone input is ignored, but the speaker driver can be operated
normally.
0dB
analog attenuation
SN00131
Figure 6. Possible Speaker Connections
A clip detection circuit will inform the user whenever the input
voltage exceeds the maximum input voltage. In that case the clip
detect status bit in audio control register B is set. An interrupt is
generated on the irqout pin of the UCB1100 whenever the enable
audio clip detect rising interrupt or the enable audio detect falling
edge interrupt bit is set in the rising edge interrupt enable or falling
edge interrupt control register B is set.
21dB
0dB
24dB
48dB
69dB
programmed attenuation
SN00130
Figure 5. Analogue and Digital Attenuation Settings
Audio Output Path
1998 May 08
Single Ended Speaker Connections
9
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.1.1 Audio Input Specifications
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
FSA
TYP
audio sample frequency
VINAM
full scale input voltage
VMICP
MAX
26
kHz
0 dB gain setting
0.28
Vpp
DC bias voltage micp input
audio input path enabled
1.4
V
RINPAI
input impedance
audio input path enabled
25
kΩ
RHINE
impedance micgnd to vssa1
audio input path enabled
GSA
gain step size
NAGS
number of gain steps
GmA
maximum gain
GEAR
gain error (accuracy of gain setting)
ROESAI
DNAAI
1.3
1.5
100
Ω
1.7
dB
32
46.5
0 dB gain setting,
full scale input voltage
–1
resolution audio input
0
dB
1
12
differential non linearity audio input ADC
dB
bit
0.9
LSB
THUDAI
total harmonic distortion
0db input gain selected
0.28Vpp, 1kHz to micp
0.03
%
THDMGAI
total harmonic distortion
46.5dB gain setting,
1mVpp, 1kHz to micp
0.1
%
SNRAI
signal to noise ratio
audio input
0dB input gain selected
0.28Vpp, 1kHz to micp
65
dB
SNRMGAI
signal to noise ratio
46.5dB gain selected
1mVpp, 1kHz to micp
50
dB
RIPIA
pass band ripple
FPLAI <Fsig < FPHAI
SBRIA
stop band rejection
audio input
FSHAI<Fsig.<20kHz
EIA
out of band rejection
audio input
F > 20kHz
NOTE: Coding scheme for ADC output data is 2’s complement.
0.5
70
dB
t.b.f.
FPHA = 0.42 * FSA
0dB
FSHA = 0.6 * FSA
SBRIA
FPHA
FPLA
FSHA
FREQUENCY (Hz)
SN00132
Figure 7. Audio Input Path Frequency Response
1998 May 08
mVrms
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FPLA = 0.00016 * FSA
RIPIA
dB
10
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.1.2 Audio Output Specifications
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
TYP
MAX
VOFFIA
offset error
No signal applied to micp
0
LSB
VOOA
full scale output voltage
0dB attenuation,
16ohm speaker
differential Spkrp–Spkrn
3.2
Vpp
VOFFOA
offset error
16ohm speaker
50
mVpp
VSPK
DC bias voltage
spkrp and spkrn pin
ASOA
attenuation step size
NSOA
number of attenuation steps
24
AMOA
maximum attenuation
69
dB
resolution
12
bit
ROESOA
DNAOA
Audio output path enabled
1.4
2.8
3.0
differential non linearity DAC
V
3.2
dB
0.9
LSB
2
%
0.03
%
THUDOAS
total harmonic distortion
16Ω speaker
0dB attenuation
20Hz to 20kHz
THUDOAH
total harmonic distortion
1kΩ headphone
0dB attenuation
20Hz to 20kHz bandwidth
SNROAS
signal to noise ratio
16Ω speaker
0dB attenuation
20Hz to 20kHz bandwidth
40
80
dB
SNROAH
signal to noise ratio,
1kHΩ headphone
0dB attenuation
20Hz to 20kHz bandwidth
65
80
dB
RIPOA
pass band ripple
FSUOA
cut off frequency upper stop band
SBROA
stop band rejection
EIOA
ZSPKR
0.5
FPLAO < Fsig <– FPHAO
FSHAO<Fsig.<20kHz
integrated out of band energy
70
F > 20kHz
speaker impedance
8
NOTE: Coding scheme for DAC input data is 2’s complement.
mVrms
16
Ω
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FSHA = 0.6 * FSA
SBROA
FPHA
FPLA
FSHA
FREQUENCY (Hz)
SN00133
Figure 8. Audio Output Filter Frequency Response
1998 May 08
FSA
30
FPHA = 0.42 * FSA
0dB
dB
0.6
dB
FPLA = 0.00016 * FSA
RIPOA
0.5
11
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
edges of the sibclk are used in case an odd telecom_divisor is set.
In that case a 50% duty cycle of the sibclk signal is mandatory to
obtain time equidistant sampling.
6.2 Telecom codec
The telecom codec contains an input channel, built up from a 64
times oversampling sigma delta analogue to digital converter (ADC)
with digital decimation filters, programmable attenuation and build in
sidetone suppression circuit. The output path consist of a digital up
sample filter, a 64 time oversampling 4 bit digital to analogue
converter (DAC) circuit followed by a differential output driver,
capable of directly driving a 600ohm isolation transformer. The
output path includes a mute function. The telecom codec also
incorporates a loopback mode, in which codec output path and the
input path are connected in series.
The input path of the telecom codec has a programmable
attenuation. It also implements a voice band filter, which consists of
an digital low pass filter, which is a part of the decimation filter.
Therefore the pass band of the voice band filter is determined by the
selected telecom codec sample rate. This voice band filter is
activated by the high pass enable bit in the telecom control register
B. The resulting telecom input filter curves are given in Figures 11
and 12.
The telecom sample rate is derived from the SIB interface clock pin
(sibclk) and is programmable through the SIB interface. The telecom
sample rate is given by the following formula:
Fst (2 * Fsibclk)
(64 * telecom_divisor)
UCB1100
The output section of the telecom codec is designed to interface with
a 600 ohm line through an isolation transformer. The built in mute
function is activated by the mute bit in the telecom control register B.
The output driver remains active in the mute mode, however no
output signal is produced.
(5 telecom_divisor 128)
For example, a sibclk of 10 MHz, with a divisor of 40, results in a
telecom sample rate of 7.813kHz. Both the rising and the falling
side tone suppression
echo on
telecom input enable
loopback
effect
attenuation
mux
tinp
tinn
64fs
1 bit ADC
4
loop inputs
fs
round
up
+3dB
16
2
Sinc4
FIR
DC
removal
low pass
FIR
half band
FIR
half band
WDF
14
2
half band
WDF
high pass
FIR
half band
FIR
half band
FIR
DC
removal
fs
round
up
2
+3dB
2
14
2
2
loop inputs
noise
shaper
interpolator
64fs
toutp
toutn
4 bit DAC
4
mute
4
effect
telecom output enable
SN00134
Figure 9. Detailed Block Diagram Telecom codec
1998 May 08
12
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
An important built in feature of the telecom codec is the sidetone
suppression circuit. The sidetone suppression circuit is activated
when the sidetone suppression enable bit in the telecom control
register B is set. The telecom input signal contains a large part of
the telecom output signal Tout, when the sidetone suppression
circuit is disabled. The available dynamic range of the telecom input
is occupied largely by the telecom output voltage.
toutp
Ro
1:1 transformer
tinp
A
Rt
Rt
Rt
Rt
Rg
Ri
The sidetone suppression circuit subtracts a part of the telecom
output signal from the telecom input signal when activated. The
available dynamic range is in that case used more effectively than
without sidetone suppression.
Rs
Rs
B
tinn
Ri
UCB1100
The built in side tone suppression circuit, shown in Figure 9, has a
fixed subtraction ratio, set be the resistors Rs and Ri, which equals
600 / 456. This ratio is calculated from the following relations:
Rg
Ro
toutn
The impedance seen by the telephone line equals:
ǒ
Ǔ
Rline + 2 * Rt ) Rt ) Ro * Ri
Ro ) Ri
SN00135
In which Rt represents winding resistance of the transformer, divided
by 2. Assuming Ri >> Ro then
Figure 10. Telecom codec Sidetone Suppression Circuitry
Shown with the Typical Connection between UCB1100 and
Telephone Line (No Protections Circuits Shown)
Rline + Rt ) Rt ) Ro + 600 + 300
2
A typical transformer has 156 ohm winding impedance, thus Re
should be 144 ohm. The ratio of the telecom input and output
voltage is therefore
Tin + Tout *
1998 May 08
13
156 ) 300
+ Tout * 456
156 ) 300 ) 144
600
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.2.1 Telecom Input Specifications
LIMITS
SYMBOL
FST
VINTM
PARAMETER
CONDITIONS
MIN
TYP
sample frequency
MAX
10
full scale input voltage
0 dB attenuation setting
0.519
telecom input path enabled
UNIT
kHz
Vp
VTIN
DC bias voltage Tinp / Tinn pins
1.4
V
ASIT
attenuation step size
6
dB
NSTI
number of attenuation steps
2
AMTI
maximum attenuation
6
AERTI
attenuation error
(accuracy of attenuation setting)
RTI
0 dB attenuation setting,
full scale input voltage
–0.5
input impedance
0
dB
0.5
dB
25
kΩ
SINADTI
total harmonic distortion
+ noise to signal ratio
full scale input signal
70
dB
SINADTIS
total harmonic distortion
+ noise to signal ratio
–43dBm input voltage
32
dB
DNLTI
differential non linearity ADC
RESTI
resolution
2
LSB
14
bit
RIPTI
pass band ripple, no voice filter
FPLTI < Fsig < FPHTI
0.6
dB
RIPVTI
pass band ripple, voice filter activated
FVHTI < Fsig < FPHTI
0.6
dB
SBRVTI
stop band rejection,
voice filter activated
Fsig < FVLTI
30
dB
SBRHTI
stop band rejection
FSHTI <Fsig.<FST
55
dB
600Ω line,
1:1 line transformer with
156Ω winding resistance
20
dB
SSUP
sidetone suppression effectiveness
NOTE: Coding scheme for ADC output data is 2’s complement.
RIPTI
RIPTI
0dB
0dB
SIBVTI
SBRHTI
SIBHTI
FPHT
FPLT
FSHT
FVLT FVHT
FREQUENCY (Hz)
FREQUENCY (Hz)
SN00136
FSHT
SN00137
Figure 11. Telecom Input Frequency Response,
No Voice Filter
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FPLT = 0.00016 * FST
FPHT = 0.42 * FST
FSHT = 0.6 * FST
FVLT = 0.018 * FST
FVHT = 0.05 * FST
1998 May 08
FPHT
14
Figure 12. Telecom Input Frequency Response,
Voice Filter Enabled
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.2.2 Telecom Output Specifications
LIMITS
SYMBOL
FST
PARAMETER
CONDITIONS
MIN
MAX
10
kHz
differential Toutp/Toutn
4.0
4.4
Vpp
telecom output path
enabled
1.4
V
sample frequency
VOOT
full scale output voltage
VTOUT
DC bias voltage
Toutp / Toutn pins
UNIT
TYP
ROESTO
resolution
14
bit
SINADTO
signal to noise + distortion
75
dB
RIPTO
pass band ripple
0.6
dB
RIPVTO
pass band ripple,
voice band filter activated
0.6
dB
SBRVTO
stop band rejection,
voice filter activated
Fsig < FVLT
SBRTO
stop band rejection
FSHT < Fsig
EITO
integrated out of band energy
70
Frequencies > FST
ZTELTO
minimal load impedance
VOFFTO
offset error
(deviation of the analogue output from
zero with 0 code input to telecom output path)
dB
25
1200Ω load
50
FPHT = 0.42 * FST
0dB
FSHT = 0.6 * FST
SBRHTO
FPHT
mV
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FPLT = 0.00016 * FST
RIPTO
FSHT
FREQUENCY (Hz)
SN00138
Figure 13. Telecom Output Frequency Response,
No Voice Filter
1998 May 08
Ω
600
NOTE: Coding scheme for the DAC input data is 2’s complement.
FPLT
mVrms
15
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.3 Touch Screen Measurement Modes
6.3.3 Plate Resistance Measurement
The UCB1100 contains an on chip interface for a 4 wire resistive
touch screen. This interface supports three modes of touch screen
measurements, position, pressure and plate resistance.
The plate resistance of a touch screen varies typically a lot due to
processing spreads. Knowing the actual plate resistance makes it
possible to compensate for the plate resistance effects in the
pressure resistance measurements. Secondly the plate resistance
decreases when two or more spots on the touch screen are
pressed. In that case a part of one plate, e.g. the X plate is shorted
by the other plate, which decreases the actual plate resistance.
6.3.1 Position Measurement
Two position measurements are needed to determine the location of
the pressed spot. First an X measurement, secondly a Y
measurement. The X plate is biased during the X position
measurement the X plate and the voltage on one or both Y terminals
(tspy, tsmy) measured. The circuit can been represented by a
potentiometer, with the tspy and/or tsmy electrode being the ‘wiper’.
The measured voltage on the tspy/tsmy terminal is proportional to
the X position of the pressed spot of the touch screen.
The plate resistance measurement is executed in the same way as
the pressure resistance measurement. In this case only one of the
two plates is biased and the other plate is kept floating. The current
through the connected plate is again a direct indication of the
connected resistance.
In the Y position mode the X plate and Y plate terminals are
interchanged, thus the Y plate is biased on the voltage on the tspx
and/or tsmx terminal is measured.
Vtscbias
iplate
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tspx
Vposition
Vtscbias
Xplate
tsmy
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏ
tspx
tsmx
Xplate
tsmy
SN00141
tspy
tsmx
Figure 16. Touch Screen Setup for Plate Resistance
Measurement
SN00139
Figure 14. Touch Screen Setup for Position Measurement
6.3.2 Pressure Measurement
The pressure used to press the touch screen can be determined. In
fact the contact resistance between the X and Y plate is measured,
which is a good indication of the size of the pressed spot and the
applied pressure. A soft stylus, e.g. a finger, leads to a rather large
contact area between the two plates when a large pressure is
applied. A hard stylus, e.g. a pen, leads to less variation in
measured contact resistance since the contact area is rather small.
One plate is biased at one or both terminals during this pressure
measurement, whereas the other plate is grounded, again on one or
both terminals. The current flowing through the touch screen is a
direct indication for the resistance between both plates. A
compensation for the series resistance, formed by the touch screen
plates itself will improve the accuracy of this measurement.
Vtscbias ipresure
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tspx
Xplate
tsmy
tsmx
tspy
SN00140
Figure 15. Touch Screen Setup for Pressure Measurement
1998 May 08
tspy
16
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.4 Touch Screen Interface
comparator
The UCB1100 contains a universal resistive touch screen interface
for 4 wire resistive touch screen, capable of performing both
position, pressure and plate resistance measurements. In addition
the touch screen can be programmed to generate interrupts when
the touch screen is pressed. The last mode is also active when the
UCB1100 is set in the standby mode.
Vdda
Rint
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏ
tspx
Xplate
tsmy
tsmx
tspx
tsmx
tspy
tsmy
tsc_mod_sel
tspy
vdda1
ts.. power
comparator
touch screen
bias voltage
ts.. ground
touch screen
current monitor
vssa3
In addition to the measurements made above, the touch screen can
also act as an interrupt source. In this mode the X plate of the touch
screen has to be powered and the Y plate has to be grounded. In
this case the touch screen is not biased by the active touch screen
bias circuit, but by a resistor to vdda1. This configuration simply
biases the touch screen and the UCB1100 does not consume power
unless the touch screen is touched. The voltage on the X plate
terminals drops if the screen is pressed. This voltage drop is
detected by Schmitt trigger circuits, of which the outputs are
connected to the interrupt control block. An touch screen interrupt is
generated either when the touch screen is pressed (falling edge
enabled) or when the touch screen is released (rising edge
enabled). which can by used to activate the system around the
UCB1100 to start a touch screen readout sequence. The internal
Schmitt trigger circuits are connected to the tspx and tsmx signals
after the built in low pass filters. This reduces the number of
spurious interrupts, due to the coupling between the LCD screen
and the touch screen sensors.
vssa1
adc_input_sel
analog mux
tsc_bias_ena
mux
tsc_mod_sel
to adc input
SN00142
Figure 17. Block Diagram of the Touch Screen Interface
The touch screen interface connects to the touch screen by four
wires: tspx, tsmx, tspy and tsmy. Each of these pins can be
programmed to tbe floating, powered or grounded in the touch
screen switch matrix. The setting of each touch screen pin is
programmable by the power ts.. and ground ts.. bits in the touch
screen control register. Possible conflicting settings (grounding and
powering of a touch screen pin at the same time) are detected by
the UCB1100. In that case the UCB1100 will ground the touch
screen pin.
Each of the four touch screen signals can be selected as input for
the built in 10 bit ADC, which is used to determine the voltage on the
selected touch screen pin. The flexible switch matrix and the multi
functional touch screen bias circuit enables the user of the UCB1100
to set each desired touch screen configuration.
The UCB1100’s internal voltage reference (Vref) is as reference
voltage for the touch screen bias circuitry. This makes the touch
screen biasing independent of supply voltage and temperature
variations. Four low pass filters, one on each touch screen terminal,
are built in to minimize the noise coupled from the LCD into the
touch screen signals. An LCD typically generates large noise
glitches on the touch screen, since they are closely coupled.
1998 May 08
SN00143
Figure 18. Touch Screen Setup for Interrupt Detection
The setting of the touch screen bias circuitry and the adc_input
multiplexer is determined by the setting of the tsc_mod_sel bits in
the touch screen control register according the following table.
17
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
TOUCH SCREEN MODE SELECTION
tsc_mod_sel bits
selected mode
00
interrupt
resistor to vdda1
touch screen bias source
defined by adc_input_sel bits
‘selected’ adc input
01
pressure
touch screen bias circuit
touch screen current monitor
10
position
touch screen bias circuit
defined by adc_inp_sel bits
11
position
touch screen bias circuit
defined by adc_input_sel bits
SUMMARY OF TOUCH SCREEN MODES
Touch screen measurement
tspx
tsmx
tspy
tsmy
touch screen
mode
touch screen
bias
X position
powered 1
grounded 1
adc input 2
adc input 2
position
enabled
Y position
adc input
2
2
1
1
position
enabled
pressure – 1
powered 1
powered 1
grounded 1
grounded 1
pressure
enabled
pressure – 2
powered
floating
grounded
floating
pressure
enabled
pressure – 3
floating
grounded
powered
floating
pressure
enabled
pressure – 4
floating
powered
floating
grounded
pressure
enabled
pressure – 5
grounded
floating
floating
powered
pressure
enabled
X plate resistance
powered 1
grounded 1
floating
floating
pressure
enabled
pressure
enabled
interrupt
disabled 3
adc input
powered
1
Y plate resistance
floating
floating
powered
interrupt
powered
powered
grounded
grounded
grounded
1
grounded
NOTES:
1. The powered and grounded touch screen pins may be interchanged.
2. One of the two indicated touch screen pins have to be selected.
3. The touch screen bias has to be disabled in this mode by the user, to prevent false interrupts.
6.4.1 Touch Screen Specifications
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VTSCBIAS
touch screen bias voltage
touch screen position mode
selected
ITSCMAX
maximum touch screen current
touch screen position mode
selected
RTSCINT
maximum touch screen resistance to
generate an interrupt
touch screen interrupt mode
selected
2500
Ω
RSWGND
on resistance ground switch
touch screen pin
programmed grounded
50
Ω
tTSCSTR
start up time touch screen bias voltage
generator
25
µs
1998 May 08
18
1.8
V
10
mA
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
the conversion. An interrupt may be generated whenever a
conversion is completed, depending of the setting of the
adc_interrupt_ena bits in the sib register 2 and 3. The
adc_data_valid bit in the SIB register 11 indicates the status of the
ADC; it equals ‘0’ when a ADC sequence is started and it equals ‘1’
when the ADC result is stored in the SIB register 11.
6.5 10 bit ADC
The UCB1100 includes a 10 bit successive approximation analogue
to digital converter (ADC) with build in track and hold circuitry, an
analogue multiplexer to select 4 analogue inputs or the 5 touch
screen voltages and 4 switched resistive voltage dividers on the
analogue ad0–3 high voltage inputs. The ADC is used to readout the
touch screen inputs and it measures the voltage on the four
analogue high voltage inputs ad0–3.
The ADC sequence is started in two ways. First it starts whenever
the adc_start bit in register 10 is changed from ‘0’ to ‘1’; this is the
case when the adc_sync_ena bit in registers 10 equals ‘0’
(=default). Internal logic determines whether the adc input
multiplexer setting was changed in the sib frame, carrying the
adc_start bit transition. If this is the case, an additional tracking time
is added automatically.
The ADC is controlled through the SIB interface. It is enabled by the
adc_enable bit in register 10; the ADC circuitry, including the track
and hold circuitry does not consume any power when it is not
enabled.
A complete analogue to digital conversion consists of several
phases. First the ADC input selector must be set to the proper input.
Secondly the track and hold must track the signal; this requires a
certain settling time if the adc input was changed. After this time the
sample is taken. A calibration of the ADC circuitry is performed
before the actual conversion starts. The result of the conversion is
stored in the register 11 of the SIB interface, after the completion of
The second mode of operation is activated when the adc_sync_ena
bit is set to ‘1’. In this mode the ADC conversion is not started by an
‘0’ to ‘1’ transition of the adc_start bis, but is ‘armed’. During the
arming situation the track and hold circuit tracks the selected input
signal. A sample is taken and the actual ADC conversion is started
when a rising edge is detected on the adcsync input pin.
internal reference
adcsync
to external register 11
mux
10 bit ADC
9 to 1
ADC start
adc
start
stop logic
sync
enable
10
track & hold
adc_sync_ena
SN00144
Figure 19. Block Diagram of the 10 bit ADC Circuit
tadcena
adc_ena
adc_input_selection
tadctrk
adc_start
tadccal
tconv
’adc state’
track
cal
conversion
track
adc_dat_valid
adc_data
SN00145
Figure 20. Timing Diagram of an ADC Conversion Sequence (adc_sync_ena=‘0’)
1998 May 08
19
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
will start on the first detected rising edge on the adcsyn pin after this
tracking time.
The ADC sequence is started in two ways. First it starts whenever
the adc_start bit in register 10 is changed from ‘0’ to ‘1’; this is the
case when the adc_sync_ena bit in registers 10 equals ‘0’
(=default). Internal logic determines whether the adc input
multiplexer setting was changed in the sib frame, carrying the
adc_start bit transition. If this is the case, an additional tracking time
is added automatically.
This mode is particulary useful when the internal ADC has to be
synchronized with the external systems. Typically it is used to
synchronize the readout of the touch screen with the driving of the
LCD screen, which is normally placed in the direct neighborhood of
the touch screen. Many spikes and a lot of ‘noise’ are superposed
on the touch screen signals, due to the close coupling of the touch
screen and the LCD.
The second mode of operation is activated when the adc_sync_ena
bit is set to ‘1’. In this mode the ADC conversion is not started by an
‘0’ to ‘1’ transition of the adc_start bis, but is ‘armed’. During the
arming situation the track and hold circuit tracks the selected input
signal. A sample is taken and the actual ADC conversion is started
when a rising edge is detected on the adcsync input pin.
The UCB1100 contains four high voltage analogue inputs ad0–3
which can be selected by the ADC input multiplexer, besides the
already discussed touch screen interface signals. These high
voltage inputs optimized to handle voltages larger than the applied
supply voltage. The built in resistive voltage divider are only
activated if the corresponding analogue input is selected. The not
selected ad0–3 inputs are high ohmic resulting in minimal leakage
input leakage of these pins.
The internal ADC start logic adds a fixed tracking time, when the
ADC input multiplexer was changed in the SIB frame with the ‘0’ to
‘1’ transition of the adc_start bit. A rising edge on the adcsync pin
will not have any effect during this tracking time; the ADC sequence
tadcena
adc_ena
tadctrk
adc_input_selection
tadcdead
adc_start
tadcstrs
adcsync
tadccal
tconv
’adc state’
track
cal
conversion
adc_dat_valid
adc_data
SN00146
Figure 21. Timing Diagram of an ADC Conversion Sequence (adc_sync_ena=‘1’)
ad0 or ad1 or ad2 or ad3
adc
input
switch
adc_inp_sel[2:0]
SN00147
Figure 22. ad0–ad3 Resistive dividers
1998 May 08
20
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.5.1 Specification Overview
LIMITS
SYMBOL
RESADC
PARAMETER
CONDITIONS
TYP
7.17
7.5
7.9
V
50
resolution of ADC
VFSad
full scale ad0–3 inputs
RINad
input impedance selected ad0–3 pin
MAX
UNIT
MIN
10
bit
75
100
Ω
ILad
input leakage current,
non selected ad0–3 pins
<1
10
µA
DNLADC
differential non-linearity
0.1
0.5
lsb
INLADC
integral non linearity
0.5
2
conversion time
110
tsibclk
10
tsibclk
tconv
tadccal
settling time
adc_sync_ena=‘0’
tadctrk
tracking time
no adc input change
adc input change
tracking time
no adc input change
adc input change
adc_sync_ena=‘1’
tadctrks
1
tsibclk
tsibclk
25
50
ns
tsibclk
10
ns
50
thadcsync
lsb
tpadcsync
6.6 On Chip Reference Circuit
The UCB1100 contains an on chip reference voltage source, which
generates the reference voltages for the 10 bit ADC and the
necessary internal reference voltages. Alternatively, the UCB1100
can be driven from an external reference voltage source.
aud_in_ena
ext_vref_ena
aud_out_ena
tel_in_ena
The internal reference voltage can be monitored and filtered
additionally on the vrefbyp pin. Two bits in the ADC control register
determine the mode of operation of this reference voltage circuit.
The vrefbyp_con bit connects the internal reference voltage to the
vrefbyp pin, while the ext_vref_ena bit disables the internal
reference voltage and switches the UCB1100 into the external
voltage reference mode.
tel_out_ena
tsc_bias_ena
&
Internal
adc_ena
internal
reference
voltage
reference
&
The internal reference circuit is activated only when one or more
analogue functions inside the UCB1100 is activated. This reduces
the current consumption of the analogue part in standby mode. The
external reference voltage source is also disconnected when all
analogue functions are disabled.
circuitry
vrefbyp_con
vrefbyp
SN00148
Figure 23. Block Diagram of the Reference Circuit
6.6.1 Specification Overview
LIMITS
SYMBOL
PARAMETER
VREF
reference voltage
trefstrt
start up time of internal reference voltage
circuit
1998 May 08
CONDITIONS
21
UNIT
MIN
TYP
MAX
1.1
1.2
1.3
V
50
tsibclk
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.7 Serial Interface Bus
NOTE:
The UCB1100 serial interface bus (SIB) is compatible with industry
standard serial ports and devices, and is designed to connect
directly to a system controller. The sib protocol allows one or more
slave devices to be connected to the system controller. The data
transfer is always synchronous and it is frame based. The SIB
interface consists of four signals: sibddn, sibdout, sibclk and
sibsync.
The interrupt controller is still active, due to its
asynchronous implementation. The UCB1100 can
therefore still generate interrupts to the system controller,
when the sibclk is stopped.
The generation of the audio and telecom sample clocks require that
the sibclk signal is symmetrical: a non symmetrical sibclk will lead to
non equidistant sample moments, when an odd frequency divisor is
set in either of the audio or telecom control registers.
Each SIB frame consists of at least 64 clock cycles. Typically 128
bits are used, divided into 2 sub frames of 64 bits each. The first
word (the bits 0 to 63) is read and/or written by the UCB1100, the
remaining bits may be used for communication between the system
controller and another slave device. The sibdout pin of the UCB1100
is default-stated for the bit 64 and higher in the SIB frame to prevent
bus conflicts with other slave devices. However when the
sib_zero_ena bit (control register 1) is set, the sibdout pin is forced
to zero for bit 64 and higher to prevent floating of the sibdout line
during this part of the sib frame in case when the UCB1100 is the
only slave device connected to the bus.
SIB MASTER
UCB11001
sibclk
sibclk
sibsync
sibsync
sibdout
sibdin
sibdout
sibdin
SIB SLAVE 2
The UCB1100 always samples incoming data on the sibdin pin on
the falling edge of sibclk and it outputs data on the sibdout pin on
the rising edge of the sibclk. The start of a new sib frame is indicated
by a pulse on the sibsync line just before the start of this new sib
frame.
sibclk
sibsync
sibdin
sibdout
The applied clock signal to the sibclk pin is used as clock signal
inside the UCB1100; all internal clock signals are derived from that.
It is required that the sibclk signal is applied if one or more analogue
or digital functions is activated in the UCB1100; only the interrupt
controller is implemented synchronously. The sibclk may be stopped
when all digital and analogue functions are disabled; in that case the
lowest possible power consumption is meet. The sibclk should not
be stopped during a sib frame, but only at the end of the sib-frame,
to ensure that all analogue and digital functions are stopped
properly.
bit 0
TO OTHER SIB SLAVES
SN00149
Figure 24. Typical Connection Between the UCB1100 and the
System Controller
bit 2
bit 1
bit 62
bit 3
bit 64
bit 63
bit 127
bit 65
bit 126
bit 0
sibclk
sibsync
sibdin
sibdout #1
sibdout #2
SN00150
Figure 25. Serial Data Transmission of the UCB1100,
sibdout #1 in case sib_zero bit = ‘0’, sibdout #2 in case sib_zero bit = ‘1’
1998 May 08
22
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.7.1 SIB Data Format
The first 64 bits in the sib-frame are read and written by the
UCB1100 and they contain both audio and telecom codec data
fields, several control bits and a control register data field as is
defined in table below.
Sib frame bit
SIBDin
field definition
SIBDout
field definition
15–0
audio input path data [15:0];
bit 0 = MSB,
the 12 MSB bits are read.
audio output path data [15:0];
bit 0 = MSB,
the bits [15:12] are ‘0’
16
not read but reserved
fixed ‘0’
20–17
control register address [3:0];
bit 0 = MSB
control register address [3:0];
bit 0 = MSB;
= copy of the register address as present in
the sibdin field in the same sib frame
21
write bit (write = 1)
fixed zero
29–22
not read but reserved
fixed zeros
30
audio valid sample flag
audio valid flag
31
telecom valid sample flag
telecom valid flag
47–32
telecom input path data [15:0];
bit 0 = MSB,
the 14 MSB bits are read.
telecom output path data [15:0],
bit 0 = MSB,
the bits [15:14] are ‘0’’
63–48
control register ‘write data [15:0];
bit 0 = MSB
control register read data [15:0];
bit 0 = MSB
NOTE:
Since the data transfer is completely synchronous, a given control register may be written many times, before the device feeding the data has a
chance to change the control bits. The UCB1100 does detect whether the data is changed or not.
1998 May 08
23
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.7.2 Codec Data Transfer
The audio and telecom codecs both operate at a programmable sample rate slower than the data transfer rate of the serial bus. The codecs
sample the contents of the appropriate field each time their internal counters indicate that a new sample is necessary. They update the data
read by the serial interface in the same manner. The counters for the audio and telecom subsystems are reset each time the respective
subsection is turned on (whenever the audio/telecom input or output path enable bits are set) and counting begins at the next SIBSync input
pulse (see Figure 26). The controlling devices must be both frequency and phase synchronized to the sample rate counters within the UCB1100
in order to ensure correct operation.
sibclk/128
sibdin
#1
codec enable
tcodstr
0
sample counter
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
sample pulse
SN00151
Figure 26. Start of the codec sample counters (divisor set to 7). Sibdin sub frame #1 contains the codec input and/or output path
enable bit, the codec enable signal is the ‘OR’ function of the associated code input and output enable bit.
The codec data is loaded in the codec input register after the sub frame has been sent completely, when the appropriate data valid flag was set
in the sib frame. The codec input data is not refreshed, whenever the audio and/or telecom data valid flag equals ‘0’ in the sub frame or when no
sibdin data is transmitted.
sibclk/128
sibdin stream
codec input data
#1
#1
N
#1
N+1
#2
#2
#1
N+2
#1
N+3
#3
#3
#1
N+4
N+5
SN00152
Figure 27. Codec input data handshake protocol, sibdin frame #1 contains codec data and the data valid flag equals ‘1’,
sib frame #2 contains codec data, but the data valid flag equals ‘0’, sib frame #3 contains no data.
Codec data must be received by the UCB1100 in one of the SIB frames preceding the sample moment of the codec, it uses the last sample
received before the sample moment. In case no refreshed codec data has been sent, the UCB1100 re-uses the available ‘old’ codec data
sample. This will lead to high distortion in the codec circuits.
1998 May 08
24
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
sibclk/128
sample
counter
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
sample pulse
sibdin
A,#1
B,#1
B,#2
C,#1
D,#1
sample B
codec data
D,#1
sample C
D,#1
D,#1
sample D
E,#1
E,#2
sample D
sample E
SN00153
Figure 28. Codec input data transfer, sib frame x,#1 contains sample x data with the associate data valid flag set to ‘1’,
the sib frame indicated with x,#2 contain the codec sample x, with the associated data valid flag set to ‘0’.
The codec output data is transmitted in the first SIB frame following the sample moment of the codec. The sibdout data stream contains a data
valid bit for each codec (bit 30 and bit 31) to simplify the data transfer from the UCB1100 to the system controller. The audio and telecom data
valid bits are set to ‘1’ in the sibdout data stream when the codec generate reliable data. This is the case when the codec circuitry is stabilized
after it was enabled. This mode of operation is chosen when the dyn_vflag_ena bit (register 13) equals ‘0’. A second mode is available to
simplify the transfer of data, which is set when the dyn_vflag_ena bit is set to ‘1’. In that case the audio and the telecom data valid flag bits will
be ‘1’ in the sib frame following the codec sample moment, which contains at all times the most recent codec result.
sibclk/128
sample counter
0
6
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
sample pulse
audio data
N
N
N+1
N+2
N+2
N+3
N+3
N+4
N+4
N+5
telecom data
N
N+1
N+2
N+2
N+3
N+3
N+4
N+4
N+5
N+6
data valid flag
SN00154
Figure 29. Sample counter synchronization (divisor set to 7), audio and telecom data placement shown in sibdout data stream,
including the associated audio/telecom data valid flags (dynamic data valid flag mode).
The audio and telecom codec data each are positioned as if they had 16 bits of resolution. For the 12-bit audio codec the low 4 bits are ignored
on input and forced to 0 on output. For the 14-bit telecom codec, the low 2 bits are treated similarly.
1998 May 08
25
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
control register data contents of SIBDout data-stream in a SIB frame
represents the previous contents of the selected control register.
6.7.3 Control Register Data Transfer
The last 16 bits of the UCB1100 word is made up of control register
data. The selection of the control register and whether it is read or
written is defined by the control register address field [bit 17:20] and
the “write” bit [bit 21]. For a read action on the a control register, the
control register address field has to set to the desired control
register address and the “write” bit has to be set to zero in the
SIBDin stream, The read data is sent by the UCB1100 within the
control register data field of SIBDout during the same frame as the
read request occurred. In addition, during a read cycle, the control
register data field of SIBDin is ignored by the UCB1100 which
implies that no modifications of the UCB1100 settings can be
performed when the “write” bit equals zero in the SIBDin
data-stream.
The control register address in the sibdout data-stream is a copy of
the selected control register in the sibdin data-stream. These bits
show an additional delay since they pass additional circuitry in the
UCB1100.
The control register data is actually written in the control registers
after the transfer of the first sib word is completed. This implies that
the control register data is updated during bit 64 of the sib frame.
The control data is only updated when the write bit is ‘1’ in the sib
frame. The control data will not be updated when the write bit equals
‘0’. This simplifies the read out of control register data, since it is not
required to send ‘valid’ data in the control register data field when a
control register is read, if the write bit is kept at ‘0’.
For a write cycle (“write” bit = 1), the control register data contents of
SIBDin are written to the UCB1100 register selected by the register
address field after receipt of the complete first word (the update is
performed during the 64th bit in the SIB frame). This implies that the
The control register data in the sibdout stream is sampled just
before the sib frame is started. This implies that the returned control
register data represents the ‘old’ control data, in case new data was
provided in the sibdin data stream.
tpcdu
bit 63
bit 64
bit 65
bit 66
sibclk
sibsync
sibdin
control data
SN00155
Figure 30. Control Register Update Timing
tsibclk
tsclsy
tpcldo
thclsy
tscldi
thcldi
sibclk
sibsync
tpdido
sibdin
sibdout
SN00156
Figure 31. Timing Definitions SIB Interface
1998 May 08
26
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.7.4 AC Electrical Characteristics
Tamb = 0°C to 70°C, VSSD = VSSA1 = VSSA2 = VSSA3 = 0V
VDDD = 3.3V ± 10%, VDDA1 = 3.3V ± 10%, VDDA2 = 3.3V ± 10%
LIMITS
SYMBOL
1/tsibclk
thsibclk/tsibclk
PARAMETER
NOTES
MIN
sibclk input frequency
TYP
0
duty cycle sibclk
UNIT
MAX
15
Note 1
MHz
50
%
tsclsy
sibsync valid to falling edge sibclk
ns
thclsy
sibsync hold after falling edge sibclk
ns
tscldi
sibdin valid to falling edge sibclk
ns
thcldi
sibdin hold after falling edge sibclk
ns
tpcldo
rising edge sibclk to valid sibdout
Note 2
thcldo
sibdout hold after rising sibclk edge
Note 3
tpdido
valid sibdin to valid sibdout
20
ns
ns
25
ns
tpcdu
NOTES:
1. This is a requirement when an odd divisor is set either in the audio or in the telecom codec.
2. This is valid for all sib frame bits 0 to 63, except bits 17–20.
3. This is valid for the sib frame bits 17–20.
6.8 General Purpose IOs
6.9 Interrupt Generation
The UCB1100 has 10 programmable digital input/output (IO) pins.
These pins can be independently programmed as input or output
using the IO_mode[0:9] bits in the control register 1. The output data
is determined by the content of the io_data bits in the control register
0, while the actual status of these pins can be read from the
io_data[0:9] bits in the control register 0.
The UCB1100 contains a programmable interrupt control block,
which can generate an interrupt for a ‘0’ to ‘1’ and/or a ‘1’ to ‘0’
transition on one or more of the IO[0:9] pins, the audio and telecom
clip detect, the adc_ready signal and the tspx_low and tsmx_low
signals.
The interrupt generation mode is set by the int_ris_ena bits in
register 2 and the int_fal_ena bits in the control register 3. The
actual interrupt status of each signal can be read from the control
register 4. The interrupt status is clear whenever a ‘1’ to ‘0’ transition
is written in control register 4 for the corresponding bit. The irqout
pin presents the ‘OR’ function of all interrupt status bits and can be
used to give an interrupt to the system controller.
The data on the io[0:9] pins are feed into the interrupt control block,
where they can generate an interrupt on the rising and/or falling
edge of these signals.
io_dir[x]
io_dat_in[x]
The interrupt controller is implemented asynchronously. This provide
the possibly to generate interrupts when the sibclk is stopped,
e.g., an interrupt can be generated in power down mode, when the
touch screen is pressed or when the state of one of the io pins
changes.
io[x]
io_dat_out[x]
ris_int_ena[x]
‘1’
int.
source
to interrupt module
SN00157
‘OR’ tree
D
R
&
irqout
Figure 32. Block Diagram of I/O Pin Circuitry
&
D
R
fal_int_ena[x]
int_stat[x]
register 4 (read)
int_clear[x]
reset
SN00158
Figure 33. Block Diagram of the Interrupt Controller
1998 May 08
27
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.10 Reset Circuitry
The nreset signal is captured in the UCB1100 using a asynchronous
pulse stretching circuit. The nreset signal may be pulled down when
the sibclk is still stopped. The internal circuitry remembers this reset
signal and generates an internal reset signal from at least 5 sibclk
periods.
COUNT
internal
reset
3
arstn
&
’1’
Q
D
Q
D
D
Q
R
NRESET
sibclk
SN00159
Figure 34. Block Diagram of the Reset Circuitry
sibclk
tlnrst
trsti
nreset
arstn
0
count
1
2
3
internal reset
SN00160
Figure 35. Timing Diagram of the Reset Circuitry
LIMITS
SYMBOL
PARAMETER
tlnrst
nreset pulse width
trsti
width of internal reset signal
tpclrsti
1998 May 08
CONDITIONS
MIN
TYP
MAX
5
ns
5 * tsibclk
delay between rising edge sibclk and internal reset
ns
25
28
UNIT
ns
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
7.0 MISCELLANEOUS
vddd
The UCB1100 has nine power supply pins, since the UCB1100
contains five power supply regions within the circuit. The analogue
and digital parts have their separate power supplies to reduce the
interference between these parts. The speaker driver circuit is
powered separately (vdda2/vssa2) from the other analogue circuit
parts and the touch screen switch matrix has its own ground pin
(vssa3). This separation in the analogue part reduces the
interference between the speaker driver and the touch screen switch
matrix, which has relatively large and fluctuating current
consumption and the remaining parts of the analog.
UCB1100
vdda1
vdda2
3.3V supply
vssd
vssd
vssa1
vssa2
The vssd pins and the vssa1 pin are connected within the UCB1100
circuit. It is recommended to connect the vssd pins and the vssa1
directly to a ground plane on the PCB. The split in power supply
connections should be maintained on the PCB to get optimal
separation. Figure 36 shows the recommended PCB power supply
strategy.
1998 May 08
vddd
7.1 Power Routing Strategy
vssa3
SN00161
Figure 36. Recommended Power Supply Connection Strategy
29
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
8.0 CONTROL REGISTER OVERVIEW
Address 0: IO port data register
BIT
MODE
9:0
R/W
SYMBOL
io_data[9:0]
REMARK
RESET
The bits in the write register provide the data of the io pin when programmed as output.
0
The bits in the read register return the actual state of the associated io pin.
Address 1: IO port direction register
BIT
MODE
9:0
R/W
SYMBOL
io_dir[9:0]
REMARK
If ‘1’, the associated io pin is defined as output.
RESET
0
If ‘0’, the associated io pin is defined as input
15
R/W
sib_zero
If ‘1’, the sibdout pin is forced ‘0’ during the second sib word.
0
If ‘0’, the sibdout pin tristated during the second sib word
Address 2: Rising edge interrupt enable register
BIT
MODE
SYMBOL
REMARK
RESET
9:0
R/W
io_ris_int[9:0]
If ‘1’, the rising edge interrupt of the associated io pin is enabled
0
11
R/W
adc_ris_int
If ‘1’, the rising edge interrupt of the adc_ready signal is enabled
0
12
R/W
tspx_ris_int
If ‘1’, the rising edge interrupt of the tspx signal is enabled
0
13
R/W
tsmx_ris_int
If ‘1’, the rising edge interrupt of the tsmx signal is enabled
0
14
R/W
tclip_ris_int
If ‘1’, the rising edge interrupt of the telecom clip is enabled
0
15
R/W
aclip_ris_int
If ‘1’, the rising edge interrupt of the audio clip is enabled
0
Address 3: Falling edge interrupt enable register
BIT
MODE
SYMBOL
REMARK
RESET
9:0
R/W
io_fal_int[9:0]
If ‘1’, the falling edge interrupt of the associated io pin is enabled
0
11
R/W
adc_fal_int
If ‘1’, the falling edge interrupt of the adc_ready signal is enabled
0
12
R/W
tspx_fal_int
If ‘1’, the falling edge interrupt of the tspx signal is enabled
0
13
R/W
tsmx_fal_int
If ‘1’, the falling edge interrupt of the tsmx signal is enabled
0
14
R/W
tclip_fal_int
If ‘1’, the falling edge interrupt of the telecom clip is enabled
0
15
R/W
aclip_fal_int
If ‘1’, the falling edge interrupt of the audio clip is enabled
0
Address 4: Interrupt clear/status register
BIT
MODE
SYMBOL
9:0
W
io_int_clr[0:9]
A ‘0’ to ‘1’ transition clears the interrupt of the associate io pin
R
io_int_stat[9:0]
Returns the actual interrupt status of the associated io pin
W
adc_int_clr
A ‘0’ to ‘1’ transition clears the interrupt adc_ready signal
R
adc_int_stat
Returns the actual interrupt status of the adc_ready signal
12
W
tspx_int_clr
A ‘0’ to ‘1’ transition clears the interrupt of the tspx signal
R
tspx_int_stat
Returns the actual interrupt status of the tspx signal
13
W
tsmx_int_clr
A ‘0’ to ‘1’ transition clears the interrupt of the tsmx signal
R
tsmx_int_stat
Returns the actual interrupt status of the tsmx signal
14
W
tclip_int_clr
A ‘0’ to ‘1’ transition clears the interrupt of the telecom clip
R
tclip_int_stat
Returns the actual interrupt status of the telecom clip
W
aclip_int_clr
A ‘0’ to ‘1’ transition clears the interrupt of the audio clip
R
aclip_int_stat
Returns the actual interrupt status of the audio clip
11
15
1998 May 08
REMARK
30
RESET
0
0
0
0
0
0
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
Address 5: Telecom control register A
BIT
MODE
SYMBOL
REMARK
RESET
6:0
R/W
tel_div[6:0]
Telecom codec sample rate divisor.
Valid values are between [0010000] (=16) and [1111111] (=127)
16
7
R/W
tel_loop_ena
If ‘1’, the loopback mode of within the telecom codec is enabled.
0
Address 6: Telecom control register B
BIT
MODE
SYMBOL
REMARK
RESET
3
R/W
high_pass_ena]
If ‘1’, the voice band filter in the telecom input path is enabled
4
R
tel_clip
The bit returns the actual telecom clip detection status.
W
tel_clip
A ‘0’ to ‘1’ transition bit clears the telecom clip detection status
0
6
R/W
tel_att
If ‘1’, the telecom input attenuation (6dB) is enabled.
0
11
R/W
side_sup_ena
If ‘1’, the sidetone suppression circuit is activated
0
13
R/W
tel_mute
If ‘1’, the telecom output is muted
0
14
R/W
tel_in_ena
If ‘1’, the telecom input path is activated
0
15
R/W
tel_out_ena
If ‘1’, the telecom output path is activated
0
0
Address 7: Audio control register A
BIT
MODE
SYMBOL
REMARK
RESET
6:0
R/W
aud_div[6:0]
Audio codec sample rate divisor.
Valid values lie between [00000110] (=6) and [1111111] (=127).
6
11:7
R/W
aud_gain[4:0]
Audio input gain setting.
Values range from [00000] (no gain) to [11111] (46.5dB gain)
0
Address 8: Audio control register B
BIT
MODE
SYMBOL
REMARK
RESET
4:0
R/W
aud_att[4:0]
Audio output attenuation setting.
Values range from [00000] (no attenuation) to [11111] (69dB attenuation).
0
6
R/W
aud_clip_ena
If ‘1’, the audio clip detection circuitry is activated
0
8
R/W
aud_loop
If ‘1’, the loopback mode in the audio codec is activated.
0
13
R/W
aud_mute
If ‘1’, the audio output is muted
0
14
R/W
aud_in_ena
If ‘1’, the audio codec input path is activated.
0
15
R/W
aud_out_ena
If ‘1’, the audio codec output path is activated.
0
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31
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
Address 9: Touch screen control register
BIT
MODE
SYMBOL
REMARK
RESET
0
R/W
tspx_pow
If ‘1’, the tspx pin is powered
0
1
R/W
tsmx_pow
If ‘1’, the tsmx pin is powered
0
2
R/W
tspy_pow
If ‘1’, the tspy pin is powered
0
3
R/W
tsmy_pow
If ‘1’, the tspy pin is powered
0
4
R/W
tspx_gnd
If ‘1’, the tspx pin is grounded
0
5
R/W
tsmx_gnd
If ‘1’, the tsmx pin is grounded
0
6
R/W
tspy_gnd
If ‘1’, the tspy pin is grounded
0
7
R/W
tsmy_gnd
If ‘1’, the tspy pin is grounded
0
[9:8]
R/W
tsc_mode[1:0]
Touch screen operation mode
00 : interrupt mode
01 : pressure measurement mode
1x : position measurement mode
0
11
R/W
tsc_bias_ena
If ‘1’, the touch screen bias circuitry is activated.
0
12
R/W
tspx_state
This bit returns the inverted state of the tspx pin,
‘0’ is high voltage (pen up), ‘1’ is low voltage (pen down)
13
R/W
tsmx_state
This bit returns the inverted state of the tsmx pin,
‘0’ is high voltage (pen up), ‘1’ is low voltage (pen down)
Address 10: ADC control register
BIT
MODE
SYMBOL
REMARK
RESET
0
R/W
adc_sync_ena
If ‘1’, the adc sync mode is activated
0
1
R/W
vrefbyp_con
If ‘1’, the internal reference voltage is connected to the vrefbyp pin.
0
4:2
R/W
adc_input[2:0]
ADC input selection bits:
000: tspx
001: tsmx
010: tspy
011: tsmy
100 ad0
101: ad1
110: ad2
111: ad3
0
5
R/W
ext_ref_ena
If ‘1’, an external reference voltage has to be applied to the vrefbyp pin
0
7
R/W
adc_start
A ‘0’ to ‘1’ transition starts the adc conversion sequence.
0
15
R/W
adc_ena
If ‘1’, the adc circuit is activated
0
Address 11: ADC data register
BIT
MODE
SYMBOL
REMARK
RESET
14:5
R
adc_data[9:0]
Returns the ADC result
0
15
R
adc_dat_val
Returns ‘0’ if an adc conversion is in progress.
Returns ‘1’ if the 0 adc conversion is completed and the adc data is stored in the
adc_data[9:0] register.
0
Address 12: ID register
BIT
MODE
SYMBOL
REMARK
5:0
R
version[5:0]
Returns 000011 for all the UCB1100 circuits meeting this specification.
11:6
R
device[5:0]
Returns 000000 for all the UCB1100 circuits meeting this specification.
15:12
R
supplier[3:0]
Returns 0001 for all the UCB1100 circuits meeting this specification.
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RESET
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
Address 13: Mode register
BIT
MODE
SYMBOL
REMARK
RESET
0
R/W
aud_test
If ‘1’, the analogue audio test mode is activated
(Note 1)
0
1
R/W
tel_test
If ‘1’, the analogue telecom test mode is activated
(Note 1)
0
5–2
R/W
prod_test_mode
These bits select the build in production test modes
(Note 1)
0
12
R/W
dyn_vflag_ena
If ‘1’, the dynamic data valid flag mode is activated for both the audio and the telecom
data valid flag.
0
13
R/W
aud_off_can
If ‘1’, the offset cancelling circuit in the audio input path is disabled.
0
14
R/W
Reserved bit for special function
15
R/W
Reserved bit for special function
NOTES:
1. These bits can only be written if the test pin is ‘1’.
2. The functionality of the UCB1100 is changed when one or more test modes are activated.
Address 14: Reserved
BIT
MODE
SYMBOL
REMARK
RESET
This register is reserved for future use.
Address 15: Null register
BIT
MODE
15:0
R
1998 May 08
SYMBOL
REMARK
Returns [1111111111111111] at all times
33
RESET
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
9.0 PACKAGE OUTLINES
9.1 LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
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SOT313-2
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
NOTES
1998 May 08
35
UCB1100
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
10.0 DEFINITIONS
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 05-98
Document order number:
1998 May 08
36
9397 750 03868