PHILIPS UCB1300

INTEGRATED CIRCUITS
DATA SHEET
UCB1300
Advanced modem/audio analog
front-end
Preliminary specification
File under Integrated Circuits, <Handbook>
1999 Jul 20
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog
front-end
UCB1300
FEATURES
• 48 pin LQFP (SOT313) small body SMD package and low external component count results in minimal PCB space
requirement
• 12-bit sigma delta audio codec with programmable sample rate, input and output voltage levels, capable of connecting
directly to speaker and microphone, including digitally controlled mute, loopback and clip detection functions
• 14-bit sigma delta telecom codec with programmable sample rate, including digitally controlled input voltage level,
mute, loopback and clip detection functions. The telecom codec can be directly connected to a Data Access
Arrangement (DAA) and includes a built in sidetone suppression circuit
• Complete 4 wire resistive touch screen interface circuit supporting position, pressure and plate resistance
measurements
• 10-bit successive approximation ADC with internal track and hold circuit and analog multiplexer for touch screen
read-out and monitoring of four external high voltage (7.5V) analog voltages
• High speed, 4 wire serial interface data bus (SIB) for communication to the system controller
• 3.3V supply voltage and built in power saving modes make the UCB1300 optimal for portable and battery powered
applications
• Maximum operating current 25 mA
• 10 general purpose IO pins
APPLICATIONS
• Handheld Personal Computers, Personal Intelligent Communicators, Personal Digital Assistants
• Smart Mobile Phones
• Screen/Web Phones
• Internet Access Terminal
• Modems
GENERAL DESCRIPTION
The UCB1300 is a single chip, integrated mixed signal audio and telecom codec. The single channel audio codec is
designed for direct connection of a microphone and a speaker. The built-in telecom codec can directly be connected to
a DAA and supports high speed modem protocols. The incorporated analog to digital converter and the touch screen
interface provides complete control and read-out of an 4 wire resistive touch screen. The 10 general purpose I/O pins
provide programmable inputs and/or outputs to the system.
The UCB1300 has a serial interface bus (SIB) intended to communicate to the system controller. Both the codec input
data and codec output data and the control register data are multiplexed on this SIB interface.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
ORDERING INFORMATION
TYPE
NUMBER
UCB1300BE
PACKAGE
NAME
LQFP48
DESCRIPTION
VERSION
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
BLOCK DIAGRAM
IO(n)
TINP
1 bit
ADC
down
sample
filter
Digital IO
circuits
4 bit
DAC
up
sample
filter
data /
control
registers
Serial bus
interface
TINN
TOUTP
SIBDIN
SIBDOUT
SIBSYNC
IRQOUT
TOUTN
Clock buffers &
sample rate
SIBCLK
dividers
MICP
1 bit
ADC
down
sample
filter
Voltage
reference
4 bit
DAC
up
sample
filter
10 bit ADC
touch
screen
interface
SKRP
SKRN
multiplexer
MICGND
AD(n)
Fig.1 Block diagram.
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TSPX,TSMX
TSPY,TSMY
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
PINNING
SYMBOL
PIN
RESET
STATE
DESCRIPTION
TYPE(1)
IO7
1
general purpose I/O pins
input
I/OC
IO8
2
general purpose I/O pins
input
I/OC
IO9
3
general purpose I/O pins
input
I/OC
ADCSYNC
4
ADC synchronization pulse input
-
IC
VSSD
5
digital ground
-
S(2)
n.c
6
not connected
-
-
VSSA2
7
analog speaker driver ground
-
S
SPKRN
8
negative speaker output
hi Z
OA
SPKRP
9
positive speaker output
hi Z
OA
VDDA2
10
analog speaker driver supply
-
S
TOUTP
11
positive telecom codec output
hi Z
OA
TOUTN
12
negative telecom codec output
hi Z
OA
TEST
13
test mode protection
‘0’
IC
TINN
14
negative telecom codec input
hi Z
IA
TINP
15
positive telecom codec input
hi Z
IA
VREFBYP
16
external reference voltage input
hi Z
I/OA
VDDA1
17
analog supply
-
S
VSSA1
18
analog ground
-
S
n.c
19
not connected
-
-
MICGND
20
microphone ground switch input
hi Z
IA
MICP
21
microphone signal input
hi Z
IA
AD3
22
analog voltage inputs
hi Z
IA
AD2
23
analog voltage inputs
hi Z
IA
AD1
24
analog voltage inputs
hi Z
IA
AD0
25
analog voltage inputs
hi Z
IA
VSSA3
26
analog touch screen ground
-
S
TSPY
27
positive Y-plate touch screen
hi Z
I/OA
TSMX
28
negative X-plate touch screen
hi Z
I/OA
TSMY
29
negative Y-plate touch screen
hi Z
I/OA
TSPX
30
positive X-plate touch screen
hi Z
I/OA
n.c
31
not connected
-
-
VDDD
32
digital supply
-
S
IO0
33
general purpose I/O pins
input
I/OC
IO1
34
general purpose I/O pins
input
I/OC
IO2
35
general purpose I/O pins
input
I/OC
IO3
36
general purpose I/O pins
input
I/OC
VSSD
37
digital ground
-
S
RESET
38
asynchronous reset input
-
IC
SIBSYNC
39
SIB synchronization input
-
IC
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
SYMBOL
PIN
UCB1300
RESET
STATE
DESCRIPTION
TYPE(1)
SIBDOUT
40
SIB data output
‘1’(6)
OC
SIBCLK
41
SIB serial interface clock
−
IC
SIBDIN
42
SIB data input
−
IC
IRQOUT
43
interrupt output
‘0’
OC
n.c
44
not connected
−
−
IO4
45
general purpose I/O pins
input
I/OC
IO5
46
general purpose I/O pins
input
I/OC
IO6
47
general purpose I/O pins
input
I/OC
VDDD
48
digital supply
−
S
Notes
1. I/OC = CMOS bidirectional; ID = digital input; S = supply; OA = analog output; IC = CMOS input; IA = analog input;
I/OA = analog bidirectional; OC = CMOS output.
2. VSSD (pins 5 and 37) and VSSA1 (pin 18) are connected internally within the UCB1300.
3. SKPRN/SPKRP (pins 8 and 9), TINN/TINP (pins 14 and 15) and TOUTP/TOUTN are differential pairs
4. TEST (pin 13) is connected to an internal pull-down resistor. This pin should be held LOW during normal operation
of the circuit.
5. The not connected pins (pins 6, 19, 31 and 44) are reserved for future applications and should be left floating.
6. SIBDOUT reset state is 1 until the SIB bus is running. SIBDOUT will be active once the SIB bus has started.
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Preliminary specification
VDDD
IO6
IO5
IO4
n.c.
IRQOUT
SIBDIN
SIBCLK
SIBDOUT
SIBSYNC
RESET
VSSD
47
46
45
44
43
42
41
40
39
38
37
dbook, full pagewidth
UCB1300
48
Advanced modem/audio analog front-end
IO7
1
36
IO3
IO8
2
35
IO2
IO9
3
34
IO1
ADCSYNC
4
33
IO0
VSSD
5
32
VDDD
n.c.
6
n.c.
22
23
24
AD3
AD2
AD1
AD0
21
25
20
12
MICP
TOUTN
MICGND
VSSA3
19
26
18
11
n.c.
TOUTP
VSSA1
TSPY
17
TSMX
27
16
28
10
VDDA1
9
VDDA2
VREFBYP
SPRKP
15
TSMY
TINP
29
14
SPKRN
13
30
8
TINN
7
TEST
VSSA2
TSPX
Fig.2 Pin configuration.
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UCB1300
XXX
6
MXXxxx
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
FUNCTIONAL DESCRIPTION
The UCB1300 consists of several analog and digital sub circuits which can be programmed via the Serial Interface Bus
(SIB). This enables the user to set the UCB1300 functionality according to actual application requirements.
AUDIO CODEC
The audio codec contains an input channel, built up with an 64 times oversampling sigma delta analog to digital converter
(ADC) with digital decimation filters and a programmable gain microphone preamplifier. The programmable gain
microphone amplifier features a built-in offset cancellation stage, which reduces the distortion of this stage at high gain
settings, caused by the offset voltages of the internal amplifiers or leakage on the board. It can be deactivated (reg13,
bit 13) for improved performance at low gain settings. A general rule is that below a gain setting of 16 (24dB gain) the
offset cancellation circuit will reduce THD and signal bandwidth and should then be deactivated.
The output path consists of a digital up sample filter, a 64 time oversampling 4 bit digital to analog converter (DAC) circuit
followed by a BTL speaker driver, capable of driving a 16 Ω speaker. The output path features a digital programmable
attenuation and a mute function.
The audio codec also incorporates a loopback mode, in which codec output path and the input path are connected in
series.
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Preliminary specification
Advanced modem/audio analog front-end
AUD_GAIN[4,3]
AUD_OFF_CAN
AUD_LOOP
UCB1300
AUD_GAIN[2..0]
1bit ADC
DIGITAL
DECIMATION
FILTER
MICP
12
MICGND
AUD_IN_ENA
AUD_OUT_ENA
VCCSPKR
SPKRP
4bit DAC
DIGITAL
ATTENUATOR
SPKRN
VSSSPKR
AUD_MUTE
AUD_ATT[2..0]
DIGITAL
NOISE
SHAPER
12
AUD_ATT[4,3]
Fig.3 Audio codec block diagram.
The audio sample rate (fsa) is derived from the SIB interface clock pin (SIBCLK) and is programmable through the SIB
interface using AUD_DIV[n]. The audio sample rate is given by the following equation:
( 2 × f SIBCLK )
f sa = ------------------------------------------------( 64 × AUD_DIV[n] )
(7< AUD_DIV[n] < 128)
For example, a serial clock of 9.216 MHz, with a divisor of 12, results in an audio sample rate of 24.0 kHz. Both the rising
and the falling edges of SIBCLK are used in case AUD_DIV[n] is set to an odd number, which demands a 50% duty cycle
of SIBCLK to obtain time equidistant sampling.
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Preliminary specification
Advanced modem/audio analog front-end
UCB1300
PASSIVE
VDDA1
ACTIVE
UCB1300
VDDA1
17
UCB1300
17
MICP
21
MICP
21
MICGND
20
MICGND
20
VSSA1
18
VSSA1
18
Fig.4 Possible microphone connections.
The UCB1300 audio codec input path accepts microphone signals directly, only a DC blocking capacitor is needed since
the MICP input is biased around 1.4V. The ‘ground’ side of the microphone is either connected to the analog ground
(Vssa1) or to the MICGND pin. The latter will decrease the current consumption of active microphones, since the MICGND
pin is made Hi-Z when the audio codec input path is disabled.
The full scale input voltage of the audio input path is programmable in 1.5 dB steps by setting the appropriate number in
AUDIO_GAIN[n] in the audio control register A. Using very high gains may require the use of the internal offset
cancellation circuit programmable in reg 13 to avoid clipping in the ADC.
A clip detection circuit will inform the user whenever the input voltage exceeds the maximum input voltage, since this will
lead to a high distortion. In that case AUD_CLIP_STAT in the audio control register B is set. When ACLIP_RIS_INT is
set, an interrupt is generated on the IRQOUT pin on the rising edge of the clip detect signal. When ACLIP_FAL_INT is
set, an interrupt is generated on the falling edge of the clip detect signal.
The frequency response of the audio codec depends mainly on the selected sample rate, since the bandwidth is limited
in the down and up sampling filters. These digital filters both contain several FIR and IIR low pass filters and a DC
removal filter (high pass filter). A 3rd order smoothing filter is implemented in the DAC path, between DAC and speaker
driver stage to reduce the spurious frequencies at the speaker outputs.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
48dB
24dB
0dB
21dB
0dB
24dB
48dB
programmed attenuation
69dB
Fig.5 Analog and digital attenuation settings audio output path.
The output level can be attenuated in 3 dB steps down to -69 dB. The first 8 attenuation steps (0 to 21 dB) are
implemented in the analog domain. The digital up sample filter contains a 24 dB and a 48 dB attenuation setting. This
arrangement preserves the resolution, thus the ‘audio quality’ of the audio output signal for attenuation settings till 21 dB.
The speaker driver is muted when AUDIO_MUTE in the audio control register B is set. The speaker driver will remain
activated in that case, however no signal is produced by the speaker driver circuit.
The speaker driver is designed to directly drive a bridge tied load (BTL). This yields the highest output power and this
arrangement does not require external DC blocking capacitors. The speaker driver also accepts single ended connection
of a speaker, in which case the maximum output power is reduced to a quarter of the BTL situation. Consequently this
way of connecting the speaker to the speaker driver reduces the power consumption of the speaker driver in the
UCB1300 by a factor of 2. Fig.6 shows possible ways to connect a speaker to the driver. Loading the amplifiers with a
capacitive load may cause high frequency oscillations and should be done cautiously.
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Preliminary specification
Advanced modem/audio analog front-end
BRIDGE TIED
SPEAKER LOAD
UCB1300
UCB1300
SINGLE ENDED SPEAKER CONNECTIONS
UCB1300
UCB1300
SPKRP
9
SPKRP
9
SPKRP
9
8
8
8
SPKRN
SPKRN
+
SPKRN
+
+
+
Fig.6 Possible speaker connections.
The audio input and output path are activated independently; the input path is enabled when AUDIO_IN_ENA is set, the
output path is enabled when AUD_OUT_ENA is set in the audio control register B. This provides the user the means to
reduce the current consumption of the UCB1300 if one part of the audio codec is not used in the application.
The audio codec has a loopback mode for system test purposes, which is activated when the AUDIO_LOOP bit in the
audio control register B is set. This is an analog loopback which internally connects the output of the audio output path
to the input of the audio input path, (see Fig.3). In this mode the normal microphone input is ignored, but the speaker
driver can be operated normally.
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Preliminary specification
Advanced modem/audio analog front-end
UCB1300
TELECOM CODEC
The telecom codec contains an input channel, built up from a 64 times oversampling sigma delta analog to digital
converter (ADC) with digital decimation filters, programmable attenuationgain and built-in sidetone suppression circuit.
The output path consist of a digital up sample filter, a 64 time oversampling 4 bit digital to analog converter (DAC) circuit
followed by a differential output driver, capable of directly driving a 600 Ω isolation transformer. The output path includes
a mute function. The telecom codec also incorporates a loopback mode, in which codec output path and the input path
are connected in series.
TEL_ATTATT TEL_GAIN
TEL_SIDE_ENA
TINP
TINN
1bit ADC
SIDETONE
DIGITAL
DECIMATION
FILTER
SUPPRESSION
CIRCUIT
14
TEL_IN_ENA
TEL_OUT_ENA
TOUTP
4bit DAC
TOUTN
DIGITAL
NOISE
SHAPER
14
TEL_MUTE
Fig.7 Telecom codec block diagram.
The telecom sample rate (fst) is derived from the SIB interface clock pin (SIBCLK) and is programmable through the SIB
interface. The telecom sample rate is given by the following formula:
( 2 × F SIBCLK )
f st = ------------------------------------------------( 64 × TEL_DIV[n] )
(15 < TEL_DIV[n] <128)
For example, a SIBCLK of 9.216 MHz, with a divisor of 40, results in a telecom sample rate of 7.2 kHz. Both the rising
and the falling edges of the SIBCLK are used in case TEL_DIV[n] is set to an odd number. In that case a 50% duty cycle
of the SIBCLK signal is mandatory to obtain time equidistant sampling.
The input path of the telecom codec has a programmable attenuationgain. It also implements a voice band filter, which
consists of an digital low pass filter, which is a part of the decimation filter. Therefore the pass band of the voice band
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Preliminary specification
Advanced modem/audio analog front-end
UCB1300
filter is determined by the selected telecom codec sample rate. This voice band filter is activated by setting
TEL_VOICE_ENA in the telecom control register B. The resulting telecom input filter curves are given in Fig.37 and
Fig.38.
The output section of the telecom codec is designed to interface with a 600 Ω line through an isolation transformer. The
built in mute function is activated by TEL_MUTE in the telecom control register B. The output driver remains active in the
mute mode, however no output signal is produced. Loading the drivers with a capacitive load may cause high frequency
oscillations and should be done cautiously.
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Preliminary specification
Advanced modem/audio analog front-end
UCB1300
TOUCH SCREEN MEASUREMENT MODES
The UCB1300 contains an on chip interface for a 4 wire resistive touch screen. This interface supports three modes of
touch screen measurements: position, pressure and plate resistance.
POSITION MEASUREMENT
Two position measurements are needed to determine the location of the pressed spot. First an X measurement, secondly
a Y measurement. The X plate is biased during the X position measurement of the X plate and the voltage on one or both
Y terminals (TSPY, TSMY) measured. The circuit can then be represented by a potentiometer, with the TSPY and/or
TSMY electrode being the ‘wiper’. The measured voltage on the TSPY/TSMY terminal is proportional to the X position
of the pressed spot of the touch screen.
Vposition
Vtscbias
tspx
tsmy
tspy
tsmx
Fig.8 Touch screen setup for position measurement.
In the Y position mode the X plate and Y plate terminals are interchanged, thus the Y plate is biased while the voltage
on the TSPX and/or TSMX terminal is measured.
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Preliminary specification
Advanced modem/audio analog front-end
UCB1300
PRESSURE MEASUREMENT
The pressure used to press the touch screen can be determined. In fact the contact resistance between the X and Y plate
is measured, which is a good indication of the size of the pressed spot and the applied pressure. A soft stylus, e.g. a
finger, leads to a rather large contact area between the two plates when a large pressure is applied. A hard stylus, e.g.
a pen, leads to less variation in measured contact resistance since the contact area is rather small.
Vtscbias
ipressure
tspx
tsmy
tspy
tsmx
Fig.9 Touch screen setup for pressure measurement.
One plate is biased at one or both terminals during this pressure measurement, whereas the other plate is grounded,
again on one or both terminals. The current flowing through the touch screen is a direct indication for the resistance
between both plates. A compensation for the series resistance, formed by the touch screen plates itself will improve the
accuracy of this measurement. The measurement is done with a resistive voltage divider. The internal resistor should be
taken into account to evaluate the settling time of the pressure measurement given the board capacitors connected to
the ADC tap point in pressure mode.
Switch matrix
Vtscbias
Measured resistor
To ADC
Internal resistor (about 1kΩ)
Fig.9 Pressure measurement scheme.
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Preliminary specification
Advanced modem/audio analog front-end
UCB1300
PLATE RESISTANCE MEASUREMENT
The plate resistance of a touch screen varies typically a lot due to processing spread. Knowing the actual plate resistance
makes it possible to compensate for the plate resistance effects in pressure resistance measurements. The plate
resistance decreases when two or more spots on the touch screen are pressed. In that case a part of one plate, e.g. the
X plate is shorted by the other plate, which decreases the actual plate resistance
Vtscbias
iplate
tspx
tsmy
tspy
tsmx
Fig.10 Touch screen setup for plate resistance.
The plate resistance measurement is executed in the same way as the pressure resistance measurement. In this case
only one of the two plates is biased and the other plate is kept floating. The current through the connected plate is again
a direct indication of the connected resistance.
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Preliminary specification
Advanced modem/audio analog front-end
UCB1300
TOUCH SCREEN INTERFACE
tsmy
tspy
tsmx
tspx
The UCB1300 contains a universal resistive touch screen interface for 4-wire resistive touch screen, capable of
performing position, pressure and plate resistance measurements. In addition the touch screen can be programmed to
generate interrupts when the touch screen is pressed. The last mode is also active when the UCB1300 is set in the
stand-by mode.
tsc_mode (interrupt)
vdda1
touch screen
bias voltage
ts..power
ts..ground
tsc_mode
(pressure)
1kΩ
vssa1
vssa3
tsc_bias_ena
Current sense input
adc_input[2:0]
tsc_mode_sel
analog mux
to adc input
Fig.11 Block diagram of the touch screen interface.
The touch screen interface connects to the touch screen by four wires: TSPX, TSMX, TSPY and TSMY. Each of these
pins can be programmed to be floating, powered or grounded in the touch screen switch matrix. The setting of each touch
screen pin is programmable through the touch screen control register. Possible conflicting settings (grounding and
powering of a touch screen pin at the same time) are detected by the UCB1300. In that case the touch screen pin will be
grounded.
In position mode, opening the TS..gnd switch can take a long time. To avoid unpredictable delays after changing the
plates configuration, the touch screen interface should be programmed to pressure mode for the duration 1 SIB frame
before resuming a position measurement.
The UCB1300’s internal voltage reference (Vref) is used as reference voltage for the touch screen bias circuit. This makes
the touch screen biasing independent of supply voltage and temperature variations. Four low pass filters, one on each
touch screen terminal, are built in to minimize the noise coupled from the LCD into the touch screen signals. An LCD
typically generates large noise glitches on the touch screen, since they are closely coupled. The influence of the glitches
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Preliminary specification
Advanced modem/audio analog front-end
UCB1300
can nevertheless be minimized by performing measurements when the LCD is quiet. This can be done by synchronizing
the measurement and the video driver with the ADCSYNC pin.
Vdda
schmitt trigger
Rint
tspx
tsmy
tspy
tsmx
schmitt trigger
Fig.12 Touch screen setup for interrupt detection.
In addition to the measurements mentioned above, the touch screen can also act as an interrupt source. In this mode
the X plate of the touch screen has to be powered and the Y plate has to be grounded. In this case the touch screen is
not biased by the active touch screen bias circuit, but by a resistor to VDDA1. This configuration simply biases the touch
screen and the UCB1300 does not consume power unless the touch screen is touched. The voltage on the X plate
terminals drops if the screen is pressed. This voltage drop is detected by Schmitt-trigger circuits, of which the outputs
are connected to the interrupt control block. A touch screen interrupt is generated either when the touch screen is
pressed (falling edge enabled) or when the touch screen is released (rising edge enabled). It can be used to activate the
system around the UCB1300 to start a touch screen read-out sequence. The internal Schmitt-trigger circuits are
connected to the TSPX and TSMX signals after the built in low pass filters. This reduces the number of spurious
interrupts, due to the coupling between the LCD screen and the touch screen sensors.
Each of the four touch screen signals can be selected as input for the built in 10 bit ADC, which is used to determine the
voltage on the selected touch screen pin. The flexible switch matrix and the multi- functional touch screen bias circuit
enables the user of the UCB1300 to set each desired touch screen configuration.
The setting of the touch screen bias circuit and the ADC input multiplexer is determined by the setting of TSC_MOD[n]
in the touch screen control register according the following table.
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Preliminary specification
Advanced modem/audio analog front-end
UCB1300
TOUCH SCREEN MODE SELECTION
TSC_MODE[N]
TOUCH SCREEN BIAS
SOURCE
SELECTED BITS
ADC MULTIPLEXER SETTING
(TOUCH SCREEN INPUTS)
00
interrupt
resistor to VDDA1
defined by ADC_INPUT[n]
01
pressure
touch screen bias circuit
touch screen current monitor
1X
position
touch screen bias circuit
defined by ADC_INPUT[n]
SUMMARY OF TOUCH SCREEN MODES; note 1
TOUCH SCREEN
MEASUREMENT
TSPX
TSMX
TSPY
TSMY
TOUCH
SCREEN
MODE
TOUCH
SCREEN
BIAS
X position
powered(2)
grounded(2)
ADC_INPUT[n]
ADC_INPUT[n]
position
Y position
ADC_INPUT[n]
ADC_INPUT[n]
powered(2)
grounded(2)
position
enabled
pressure - 1
powered(2)
powered(2)
grounded(2)
grounded(2)
pressure
enabled
pressure - 2
powered
floating
grounded
floating
pressure
enabled
pressure - 3
floating
grounded
powered
floating
pressure
enabled
pressure - 4
floating
powered
floating
grounded
pressure
enabled
pressure - 5
grounded
floating
floating
powered
pressure
enabled
X-plate resistance
powered(2)
grounded(2)
floating
floating
pressure
enabled
Y-plate resistance
floating
floating
powered(2)
grounded(2)
pressure
enabled
interrupt
powered
powered
grounded
grounded
interrupt
disabled(3)
Notes
1. Control register address 9 is used for touch screen mode selection.
2. The powered and grounded touch screen pins may be interchanged.
3. In this mode, the touch screen bias must be disabled by the user to prevent false interrupts.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
10 BIT ADC
The UCB1300 includes a 10 bit successive approximation analog to digital converter (ADC) with built-in track and hold
circuit and an analog multiplexer to select one of the 4 analog inputs (AD0 - AD3), the 4 touch screen inputs (TSPX,
TSMX, TSPY, TSMY) or the pressure output of the touch screen bias circuit. The ADC is used to read-out the touch
screen inputs and it measures the voltage on the four analog high voltage inputs AD0 - AD3. The analog multiplexer
contains 4 resistive dividers to attenuate the high voltage on the AD0 - AD3 inputs to the ADC input range.
mux
adcsync
to control reg 11
internal reference
track&hold
10
ADC start
adc start
stop logic
sync
enable
10 bit ADC
9 to 1
adc_sync_ena
Fig.13 Block diagram of the 10-bit ADC circuit.
The ADC is controlled completely through the SIB interface, but the UCB1300 contains internal logic to ease the control
of the ADC and to minimize the number of SIB frame read/write actions.
A complete ADC control sequence analog to digital conversion consists of several phases. Firstly the ADC has to be
enabled, secondly the input selector must be set to the proper input, thirdly the ADC conversion has to be started and
finally the ADC result has to be read from register 11.
The ADC is activated by setting ADC_ENA in register 10. The ADC circuit, including the track and hold circuit does not
consume any power as long as this bit is reset. The analog input multiplexer is controlled by ADC_INPUT[n] and the ADC
is actually started with the ADC_START bit. When TSPX and TSMX are in the interrupt mode, the ADC cannot be started,
even to measure AD0-3.
The UCB1300 has two different modes to start the ADC conversion, which are selected by the ADC_SYNC_ENA bit.
The default mode is the non-synchronization mode, in which the conversion is started directly with a 0->1 transition of
ADC_START. Secondly the ADC is started at a rising edge of the signal applied to the ADCSYNC pin if
ADC_SYNC_ENA is set. Activating the ADC while keeping the start logic in the started state (ADC_START = 1) will lead
to unpredictible behavior and the value of the ADC data register will not be meaningfull. Always activate a start sequence
for each aquisition (0 to 1 transition on the internal ADC_START signal).
The internal track and hold circuit requires a certain settling time to track the input signal correctly. This can be ensured
from the software by writing first a SIB frame with the ADC multiplexer setting before the SIB frame with the ADC_START
command is transferred. The UCB1300 ADC start/stop logic will detect whether the ADC input multiplexer is changed in
the same SIB frame as the ADC start command is given. In that case it will delay the actual start of the ADC circuit to
ensure that the track and hold settling time requirements are met. This leads to the following two timing diagrams:
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
‘SIB frame’
tsibwrite
tsibwrite
set adc_ena:1
set adc_start:1
UCB1300
tsibwrite
set adc_start:0
read adc result
tadcena
adc_ena (internal)
tsamdel1
adc_start (internal)
adc_input_selection
wait for start
‘adc start state’
wait for start
tadcconv
ttrckmin
‘adc state’
tracking
conversion
tracking
adc_dat_valid
adc_data
Fig.14 ADC timing sequence, non ADC sync mode, no changing ADC input multiplexer settings.
‘SIB frame’
tsibwrite
tsibwrite
tsibwrite
set adc_ena:1
set adc_start:1
set adc_start:0
read adc result
tadcena
adc_ena (internal)
tsamdel2
adc_start (internal)
adc_input_selection
‘adc start state’
wait for start
wait for start
tadcconv
ttrckmin
‘adc state’
tracking
conversion
tracking
adc_dat_valid
adc_data
Fig.15 ADC timing sequence, non ADC sync mode, changing ADC input multiplexer settings.
The ADC timing diagrams indicate that in the non-ADC sync mode the ADC result can be read in the SIB frame following
the SIB frame with the ADC start command, if the ADC multiplexer setting is not changed. If the ADC input multiplexer
setting is changed, the ADC result can be read in the second SIB frame following the SIB frame with the ADC start
command.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
The second ADC start mode gives the opportunity to start the ADC at the rising edge of the signal connected to the
ADCSYNC pin. The 0->1 transition of the ADC_START bit will arm the ADC, such that it will start in the first detected
rising edge of the ADCSYNC signal. Also in this mode, the internal start/stop logic will detect whether the ADC multiplexer
settings are changed simultaneously with the ADC start bit and it will add a delay to ensure sufficient setting time for the
internal track and hold circuit. A rising edge of the signal connected to the ADCSYNC pin occurring during this tracking
time is ignored; the ADC conversion is started on the first rising edge detected after this delay time. This leads to the
following two timing diagrams of the ADC conversion.
tsibwrite
‘SIB frame’
tsibwrite
tsibwrite
set adc_ena:1
set adc_start:1
set adc_start:0
read reg:11
tadcena
adc_ena (internal)
adc_start (internal)
adc_input_selection
‘adc start state’
wait for start
wait for sync
wait for start
tadcsam3
tadcconv
‘adc state’
conversion
tracking
tracking
thadcsync
adc_sync
adc_dat_valid
adc_data
Fig.16 ADC timing sequence, ADC sync mode, no changing ADC input multiplexer settings.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
tsibwrite
tsibwrite
‘SIB frame’
set adc_ena:1
set adc_start:1
UCB1300
tsibwrite
set adc_start:0
read reg:11
tadcena
adc_ena (internal)
ttrckmin
adc_start (internal)
adc_input_selection
‘adc start state’
wait for start
wait for sync
wait for start
tadcsam3
tadcconv
‘adc state’
tracking
conversion
tracking
thadcsync
adc_sync
adc_dat_valid
adc_data
Fig.17 ADC timing sequence, ADC sync mode, changing ADC input multiplexer settings.
The ADC sync mode is particularly useful when the internal ADC has to be synchronized to the external system. Typically
it is used to synchronize the read-out of the touch screen to the driving of the LCD screen, which is normally placed
beneath the touch screen. Many spikes and a lot of 'noise' are superposed on the touch screen signals, due to the close
coupling of the touch screen and the LCD.
The result of the conversion is stored in the register 11 of the SIB interface, after the completion of the conversion. An
interrupt may be generated whenever a conversion is completed (ADC_FLA_INT and/or ADC_RIS_INT bits in register
2 and 3) to ease the synchronization between the UCB1300 and the system controller. The ADC result is reset to 0x000,
whenever the ADC is started or armed till the ADC conversion is completed. ADC_DAT_VAL in the SIB register 11
indicates the status of the ADC; it equals '0' when a ADC sequence is started, which implies that the ADC result is not
valid and it equals '1' when the ADC conversion is completed and the result is stored in the SIB register 11.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
AD[n]
adc
input
MUX
ADC_INPUT[n]
Fig.18 Block diagram of resistive dividers AD0 - AD3.
The applied voltage on the four analog inputs of the UCB1300 (AD0 - AD3) is attenuated before it is applied to the ADC
input multiplexer using on chip resistive dividers.These high voltage inputs are optimized to handle voltages larger than
the applied supply voltage. The built-in resistive voltage dividers are only activated if the corresponding analog input is
selected. The resistive dividers are made floating when the input is not selected by the ADC input multiplexer, such that
the input leakage of these high voltage analog pins is minimized. This makes these analog inputs very suitable to monitor
battery voltage voltages.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
ON-CHIP REFERENCE CIRCUIT
The UCB1300 contains an on chip reference voltage source, which generates the reference voltages for the 10 bit ADC
and the virtual analog ground. Alternatively the UCB1300 can be driven from an external reference voltage source.
aud_in_ena
aud_out_ena
tel_in_ena
tel_out_ena
tsc_bias_ena
adc_en
ext_vref_ena
internal
analog
ground
&
ena
internal
bandgap Vbg
reference
voltage
circuitry
internal
ADC
reference
&
vrefbyp_con
vrefbyp
Fig.19 Block diagram of the reference circuit.
The internal reference voltage is connected to the VREFBYP pin, where an external capacitor could be connected to filter
this reference voltage, if VREF_CON (register 10) is set. THIS IS NOT RECOMMENDED since the internal impedance
of the reference (several 100MΩ) will be sensitive to board leakage and the turn on time constant will be very long.When
choosing a capacitor, the internal impedance (around 50kΩ) should be taken into account.
An external voltage reference connected to the VREFBYP pin is used as voltage reference by the UCB1300 circuit, if the
EXT_REF_ENA bit (register 10) is set. Two bits in the ADC control register determine the mode of operation of this
reference voltage circuit. VREFBYP_CON connects the internal reference voltage to the VREFBYP pin, while
EXT_VREF_ENA disables the internal reference voltage and switches the UCB1300 into the external voltage reference
mode.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
SERIAL INTERFACE BUS
The UCB1300 Serial Interface Bus (SIB) is compatible with industry standard serial ports and devices, and is designed
to connect directly to a system controller. The SIB protocol allows one or more slave devices to be connected to the
system controller. The data transfer is always synchronous and it is frame based. The SIB interface consists of four
signals: SIBDIN, SIBDOUT, SIBCLK and SIBSYNC.
SIB MASTER
UCB1300
sibclk
sibclk
sibsync
sibsync
sibdout
sibdin
sibdout
sibdin
SIB SLAVE 2
sibclk
sibsync
sibdin
sibdout
TO OTHER SIB SLAVES
Fig.20 Typical connection between the UCB1300 and the system controller.
Each SIB frame consists of at least 64 clock cycles. Typically 128 bits are used, divided into 2 sub frames of 64 bits each.
The first word (the bits 0 to 63) is read and/or written by the UCB1300, the remaining bits may be used for communication
between the system controller and another slave device. The SIBDOUT pin of the UCB1300 is tri-stated for the bit 64
and higher in the SIB frame to prevent bus conflicts with other slave devices. However when SIB_ZERO (control register
1) is set, the SIBDOUT pin is forced to zero from bit 64 onwards to prevent the SIBDOUT line from floating. This feature
is needed when the UCB1300 is the only slave device connected to the bus.
The UCB1300 always samples incoming data on the SIBDIN pin on the falling edge of SIBCLK and it outputs data on
the SIBDOUT pin on the rising edge of the SIBCLK. The start of a new SIB frame is indicated by a pulse on the SIBSYNC
line just before the start of this new SIB frame.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
bit 0
bit 1
bit 63 bit 64 bit 65
UCB1300
bit 126 bit 127 bit 0
sibclk
sibsync
sibdin
sibdout #1
sibdout #2
Fig.21 Serial data transmission of the UCB1300
The applied clock signal to the SIBCLK pin is used as clock signal inside the UCB1300; all internal clock signals are
derived from that. It is required that the SIBCLK signal is applied if one or more analog or digital functions are activated
in the UCB1300; only the interrupt controller is implemented asynchronously. SIBCLK may be stopped when all digital
and analog functions are disabled; in that case the lowest possible power consumption is met. The SIBCLK should not
be stopped during a SIB frame, but only at the end of the SIB-frame, to ensure that all analog and digital functions are
stopped properly.
Note: The interrupt controller is still active, due to its asynchronous implementation. The UCB1300 can therefore still
generate interrupts to the system controller, when the SIBCLK is stopped.
The generation of the audio and telecom sample clocks requires that the SIBCLK signal is symmetrical: a non
symmetrical SIBCLK will lead to non equidistant sample moments, when an odd frequency divisor is set in either of the
audio or telecom control register.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
SIB DATA FORMAT
The first 64 bits in the SIB-frame are read and written by the UCB1300 and they contain both audio and telecom codec
data fields, several control bits and a control register data field are defined in table below.
SIB DATA FORMATS
SIB FRAME
BIT
SIBDIN FIELD DEFINITION
SIBDOUT FIELD DEFINITION
0 - 11
audio input path data (12 bits); bit 0 = MSB
12 - 16
not read but reserved
audio output path data (12 bits); bit 0 = MSB
fixed ‘0’
17 - 20
control register address (4 bits); bit 17 = MSB
control register address (4 bits); bit 17 = MSB; is a
copy of the register address as present in the
SIBDIN field in the same SIB frame.
21
write bit (write 1)
fixed ‘0’
22 - 29
not read but reserved
fixed ‘0’
30
audio valid sample flag
audio valid flag
31
telecom valid sample flag
telecom valid flag
32 - 45
telecom input path data (14 bits)
telecom output path data (14 bits); bit 32 MSB
46 - 47
not read but reserved
fixed ‘0’
48 - 63
control register write data (16 bit); bit 48 = MSB control register read data (16 bit); bit 48 = MSB
Since the data transfer is completely synchronous, a given control register may be written many times, before the device
feeding the data has a chance to change the control bits. The UCB1300 does detect whether the data is changed or not.
CONTROL REGISTER DATA TRANSFER
The last 16 bits of the UCB1300 word is made up of control register data. The selection of the control register and whether
it is read or written is defined by the control register address field [bit 17:20] and the “write” bit [bit 21]. For a read action
of a control register, the control register address field has to be set to the desired control register address and the “write”
bit has to be set to zero in the SIBDIN stream. The read data is sent by the UCB1300 within the control register data field
of SIBDOUT during the same frame as the read request occurred. In addition, during a read cycle, the control register
data field of SIBDIN is ignored by the UCB1300 which implies that no modifications of the UCB1300 settings can be
performed when the “write” bit equals zero in the SIBDIN data-stream.
For a write cycle (“write” bit = 1), the control register data contents of SIBDIN are written to the UCB1300 register selected
by the register address field after reception of the complete first word (the update is performed during the 64th bit in the
SIB frame). This implies that the control register data contents of SIBDOUT data-stream in a SIB frame represents the
previous contents of the selected control register.
The control register address in the SIBDOUT data-stream is a copy of the selected control register in the SIB
data-stream. These bits show an additional delay since they pass additional circuit in the UCB1300.
The control register data is actually written in the control registers after the transfer of the first SIB word is completed.
This implies that the control register data is updated during bit 64 of the SIB frame. The control data is only updated when
the write bit is '1' in the SIB frame. The control data will not be updated when the write bit equals '0'. This simplifies the
read out of control register data, since it is not required to send 'valid' data in the control register data field when a control
register is read, if the write bit is kept at '0'.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
bit 63
bit 64
UCB1300
bit 65
bit 66
tpcdu
sibclk
sibsync
sibdin
control data
Fig.22 Control register update timing.
The control register data in the SIBDOUT stream is sampled just before the SIB frame is started. This implies that the
returned control register data represents the 'old' control data, in case new data was provided in the SIBDIN data stream.
tsibclk
tsclsy
tpcldo
thclsy
tscldi
thcldi
sibclk
sibsync
tpdido
sibdin
sibdout
Fig.23 Timing definitions SIB interface
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
GENERAL PURPOSE I/O
The UCB1300 has 10 programmable digital input/output (I/O) pins. These pins can be independently programmed as
input or output using IO_DIR[0:9] in control register 1. The output data is determined by the content of IO_DATA[n] in
control register 0, while the actual status of these pins can be read from the IO_DATA[n] bits in control register 0.
IO_DIR[n]
IO_DATA[n]
(Write)
IO[n]
IO_DATA[n]
(Read)
to interrupt module
Fig.24 Block diagram of I/O pin circuit.
The data on the IO0-IO9 pins are feed into the interrupt control block, where they can generate an interrupt on the rising
and/or falling edge of these signals.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
INTERRUPT CIRCUIT
The UCB1300 contains a programmable interrupt control block, which can generate an interrupt for a '0' to '1' and/or a
'1' to '0' transition on one or more of the IO0-IO9 pins, the audio and telecom clip detect, the adc_ready signal and the
TSPX and TSMX signals.
The interrupt generation mode is set by IO_RIS_INT[n] in register 2 and INT_FAL_ENA[n] in control register 3. The actual
interrupt status of each signal can be read from the control register 4. The interrupt status is cleared whenever a ‘0’ to ‘1’
transition is written in control register 4 for the corresponding bit.
‘1’
D
rising edge
interrupt enable
register 2
Q
interrupt
source
‘OR’ tree
&
R
IRQOUT
D
Q
&
R
falling edge
interrupt enable
register 3
reset
interrupt status
register 4 (read)
interrupt clear
register 4 (write)
Fig.25 Block diagram of the interrupt controller.
The IRQOUT pin presents the 'OR' function of all interrupt status bits and can be used to give an interrupt to the system
controller.
The interrupt controller is implemented asynchronously. This provides the possibility to generate interrupts when the
SIBCLK is stopped, e.g. an interrupt can be generated in power down mode, when the touch screen is pressed or when
the state of one of the IO pins changes.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
RESET CIRCUIT
RESET is captured in the UCB1300 using a asynchronous pulse stretching circuit. RESET may be pulled down when
the SIBCLK is still stopped. The internal circuit remembers this reset signal and generates an internal reset signal for at
least 5 SIBCLK periods.
&
COUNT
‘1’
D
Q
D
Q
D
<3
Q
internal
reset
R
R
RESET
SIBCLK
Fig.26 Block diagram of the reset circuit.
sibclk
tlnrst
trsti
nreset
arstn
count
0
1
2
internal reset
Fig.27 Timing diagram of the reset circuit.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
POWER ROUTING STRATEGY
The UCB1300 has nine power supply pins, since the UCB1300 contains five power supply regions within the circuit. The
analog and digital parts have their separate power supplies to reduce the interference between these parts. The speaker
driver circuit is powered separately (VDDA2/VSSA2) from the other analog circuit parts and the touch screen switch matrix
has its own ground pin (VSSA3). This separation in the analog part reduces the interference between the speaker driver
and the touch screen switch matrix, which has relatively large and fluctuating current consumption and the remaining
parts of the analog circuit.
32
48
vddd
vddd
vdda1
17
UCB1300
vdda2
10
vssa2
vssd
37
vssd
5
vssa1
3.3V supply
7
vssa3
26
18
Fig.28 Recommended power supply connection strategy, single power supply systems.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
32
UCB1300
48
vddd
vddd
vdda1
17
UCB1300
vdda2
10
3.3V
digital
supply
vssa2
vssd
37
vssd
5
vssa1
18
3.3V
analog
supply
7
vssa3
26
Fig.29 Recommended power supply connection strategy, dual power supply systems.
The VSSD pins and the VSSA1 pin are connected within the UCB1300 circuit. It is recommended to connect the VSSD pins
and the VSSA1 directly to a ground plane on the PCB. The split in power supply connections should be maintained on the
PCB to get optimal separation. Fig.28 shows the recommended PCB power supply strategy if only one single supply is
used, while Fig.29 shows the recommended power supply connection for a dual power supply system, with separate
analog and digital supplies.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
APPLICATION INFORMATION
In this chapter some application information is contained. More information will be available when an Application Note
on UCB1300 is published.
Sidetone suppression circuit
UCB1300
TOUTP
Ro
11
Rg
TINP
1:1 transformer
A
B
Ri
15
Rt
Rt
Rs
Rt
Rt
Rs
14
Ri
+
+
-
TINN
Rg
Ro
12
TOUTN
Fig.30 Typical telecom codec sidetone suppression circuit (without protection circuits).
An important built-in feature of the telecom codec is the sidetone suppression circuit. The sidetone suppression circuit is
activated when TEL_SIDE_ENA in the telecom control register B is set. The telecom input signal contains a large part
of the telecom output signal, when the sidetone suppression circuit is disabled. The available dynamic range of the
telecom input is occupied largely by the telecom output voltage.
The sidetone suppression circuit subtracts a part of the telecom output signal from the telecom input signal when
activated. The available dynamic range is in that case used more effectively than without sidetone suppression.
The built in side tone suppression circuit, shown in Fig.30, has a fixed subtraction ratio, set be the resistors Rs and Ri,
which equals 600/456. This ratio is calculated from the following relations.
The impedance seen by the telephone line equals:
R o × R i
Z line = 2 ×  R t + R t + ------------------ ,

R 0 + R i
in which Rt represents winding resistance of the transformer, divided by 2. Assuming Ri >> Ro then
R line = R t + R t + R o = 600 ⁄ 2 = 300Ω
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
A typical transformer has 156 Ω winding impedance, thus Ro should be 144 Ω. The ratio of the telecom input and output
voltage is therefore:
456
156 + 300
V i(tel) = V o(tel) × ------------------------------------------ = V o(tel) × ---------600
156 + 300 + 144
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
Codec data transfer
The UCB1300 codec operates at samples which depend on the applied SIBCLK frequency and the programmed audio
and telecom divisors. The codec data transfer between the UCB1300 and the system controller has to be synchronized
with the UCB1300 sample counters and the SIB bus data transfer protocol to prevent conversion errors, resulting in high
distortion.
Correct codec data transfer is obtained easily when the UCB1300 is connected to one of the controllers in the PR3000
series, but the UCB1300 can also be connected to other controllers, if the following data protocol is used.
START OF CODEC DATA TRANSFER
The UCB1300 internal sample counters are started at the beginning of the first SIB frame following the SIB frame in which
the codec input and/or output path is enabled. This implies that the sample rate divisor has to be programmed before the
codec input and/or output path is enabled, Fig.31. Changing the sample rate on the fly, that is without disabling both the
codec input and output path before the divisor is reprogrammed, will disturb the codec data transfer synchronization
between the UCB1300 and its controller and is therefore not allowed.
ADCSYNC
SIBDIN
sample counter
reg. 5 or 7
reg. 6 or 8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
sample frequency
Fig.31 Start-up sequence of the codec, TEL_DIV[n] = 9.
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5
6
7
8
0
1
2
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
CODEC DATA TRANSFER INTO THE
UCB1300
UCB1300
Both the audio and the telecom data is transferred within the SIB frame (bit 11-0 and bit 47-32). This data is accompanied
by two data valid flags (bit 30: audio data valid, bit 31: telecom data valid). The codec data in the SIB frames is only
processed in the UCB1300 if the appropriate data valid flag is set in the frame; the data is discarded when the data flag
equals ‘0’. Figure 32 shows the basic codec data synchronization principle used in the UCB1300.
SIB INTERFACE
UPSAMPLE FILTERS
audio data[n]
SIBCLK
DFF
SIBDIN
SIBSYNC
64 bit shift register
audio_data_valid
input
latch
&
fsa
telecom data[n]
DFF
telec_data_valid
input
latch
&
bit64
fst
Fig.32 Codec input path data synchronization principle.
Figure 32 shows that audio and telecom data is made available for the codec up sample filters during the 64th bit in the
SIB frame. This implies that the codec data has to be transferred in one of the SIB frames preceding the codec sample
moment.
Note: If the programmed divisor equals a multiple of 4, the codec data transfer is synchronized to the SIB frame repetition
rate (e.g. AUD_DIV[n] = 8 ⇒1 sample is needed in 2 SIB frames, AUD_DIV[n] = 12 ⇒ 1 sample is needed in 3 SIB
frames, etc.).
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
CODEC DATA TRANSFER FROM THE
UCB1300
UCB1300
The data resulting from the UCB1300 codec ADC (input) paths is transfer to the system controller at the programmed
codec sample rate. However the codec data is synchronized with the SIB frame repetition rate. Figure 33 shows the basic
synchronization principle used inside the UCB1300. Codec data will be present in each SIB frame produced by the
UCB1300; the sample will be repeated in the following SIB frames till a new sample has become available.
SIB INTERFACE
DOWN SAMPLE FILTERS
audio data[n]
output
SIBCLK
load
DFF
64 bit shift register
latch
bit0
bit21
fsa
telec data[n]
output
load
DFF
SIBDOUT
SIBSYNC
latch
bit48
fst
bit21
Fig.33 synchronization of codec samples in SIBDOUT data stream.
The codec samples in the SIBDOUT stream are also accompanied by a audio and telecom data valid bit (bit 30 and bit
31). These data valid flags are zero if the corresponding codec adc paths are disabled and during the start up period of
the codec’s, when unreliable samples are generated. By default (after reset), the data valid bits will be continuously ‘1’
when reliable samples are generated.
However when DYN_VFLAG_ENA is set, the data valid bits will be ‘1’ during one of the SIB frames, containing identical
samples (this is the case when a high divisor is programmed). The audio_vflag bit will be high during the last sample in
a series of identical samples, while the telecom_vflag bit is high at the first sample in a series of identical bits. An example
of the timing diagram is shown in figure 34.
SIBSYNC
fsa
audio codec out
SIBDOUT
sample N
sample N
sample N+1
sample N
sample N+1
sample N+1
sample N+2
sample N+2
sample N+2
sample N+3
sample N+2
audio_vflag bit
Fig.34 Audio codec data transfer, AUD_DIV[n] = 9, DYN_VFLAG_ENA = 1.
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sample N+3
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); notes 1 and 2
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
-0.5
+5.0
V
VI
DC input voltage (except inputs AD0 - AD3)
-0.5
VDD + 0.5
V
VI
DC input voltage AD0 - AD3
-0.5
+8.5
V
VO
DC output voltage
-
VDD + 0.5
V
II(d)
diode input current
-
10
mA
IO(d)
diode output current
-
10
mA
IO
continuous output current, digital outputs
-
4
mA
Tstg
storage temperature
-55
+150
°C
Notes
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any conditions other than those described in
the Absolute Maximum Rating section of this specification is not implied.
2. Parameters are valid over the ambient operating temperature unless otherwise specified. All voltages are with
respect to VSSD (pin 37), unless otherwise noted.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1999 Jul 20
PARAMETER
thermal resistance from junction to ambient in free air
40
VALUE
UNIT
67
K/W
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
DC CHARACTERISTICS
VSSD = VSSA1 = VSSA2 = VSSA3 = 0 V; Tamb =25 °C; fi(sibclk) = 9.216 MHz; VI(ref) = 1.2 V; all voltages referenced to VSSD
(pin 5); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
3.0
3.3
3.6
V
VDDA1
analog supply voltage - excl.
speaker driver
3.0
3.3
3.6
V
VDDA2
analog supply voltage speaker driver only
3.0
3.3
3.6
V
VSSA2
analog ground - speaker driver
-0.4
0
+0.4
V
VSSA3
analog ground - touch screen
switch matrix
-0.4
0
+0.4
V
IDDD
digital supply current(1)
19
-
mA
-
17
-
mA
only telecom codec activated -
19
-
mA
only touch screen activated
-
15
-
mA
only ADC activated
-
15
-
mA
no functions activated; fsibclk
off
-
-
10
µA
full functionality
only audio codec activated
IDDA1
analog supply current(1)(2)
full functionality
-
4.6
-
mA
only audio codec activated
-
3.7
-
mA
only telecom codec activated -
4.4
-
mA
only touch screen activated
1.0
-
mA
-
100
µA
-
only touch screen in interrupt mode
only ADC activated
IDDA2
total speaker driver supply(1)(2)
current
1.0
-
mA
no analog functions activated -
-
<10
-
µA
speaker driver enabled
-
0.6
-
mA
speaker driver disabled
-
-
10
µA
-0.5
-
+0.3VDDD
V
V
VIL
LOW level input voltage
VIH
HIGH level input voltage
0.7VDDD
-
0.5VDDD
VOL
LOW level output voltage
IOL = 2 mA
-
-
0.2VDDD
V
VOH
HIGH level output voltage
IOH = 2 mA
0.8VDDD
-
-
V
fi(sibclk)
serial interface clock frequency
0
10
15
MHz
Tamb
operating ambient temperature
-20
-
70
°C
Notes
1. Indicative value measured during the initial characterization.
2. Excluding connected touch screen and speaker load currents.
1999 Jul 20
41
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
AC CHARACTERISTICS
VSSD = VSSA1 = VSSA2 = VSSA3 = 0 V; VDDD = VDDA1 = VDDA2 = 3.3 V+/-10%; Tamb =25 °C; VI(ref) = 1.2 V;
fi(sibclk) = 9.216 MHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Audio Input; notes 1 and 2
fsa
audio sample frequency
-
-
26
kHz
VI(RMS)
input voltage (RMS value) 0 dB gain setting
90
100
125
mV
VI(BIAS)
DC bias voltage
1.35
1.4
1.5
V
Zi
input impedance
20
25
-
kΩ
Z(18-20)
impedance MICGND VSSA1
-
-
200
Ω
Gstep
gain step size
1
1.5
2
dB
Nstep
number of gain settings
-
32
-
-
Gv
gain
(AUD_GAIN=011111)
15
22.5
28
dB
EG
gain error
each gain step
-1
-
1
dB
MICP input
RES
resolution
-
12
-
bit
LE(d)(ADC)
ADC differential linearity
error
-
-
1
LSB
THD
total harmonic distortion
input gain = 0 dB
(AUD_GAIN = 00000);
-
-65
-40
dB
input signal = 1 mVrms
input gain = 22.5 dB
(AUD_GAIN[n] = 01111);
AC coupling disabled
(AUD_OFF_CAN = 0);
-
-36
-26
dB
input signal = 0.4mVrms
input gain = 46.5 dB
(AUD_GAIN[n] = 11111);
AC coupling enabled
(AUD_OFF_CAN = 1);
S/N
signal-to-noise ratio
-29
dB
input gain = 0 dB
(AUD_GAIN = 00000)
50
68
-
dB
input signal = 1mVrms;
input gain = 22.5 dB
(AUD_GAIN[n] = 01111);
25
32
-
dB
input signal = 0.4mVrms;
input gain = 46.5 dB
(AUD_GAIN[n] = 11111);
22
dB
PBRR
pass-band ripple rejection fpla < fsig < fpha(3)
-
-
1.2
dB
SBR
stop-band rejection
fsha < fsig < 20 kHz(3)
50
-
-
dB
Doffset
digital offset
no signal applied to MICP
-
-
50
LSB
1999 Jul 20
42
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
SYMBOL
PARAMETER
UCB1300
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Audio Output; notes 4 and 5
VO(RMS)
output voltage (RMS
value)
Eoffset
offset error (peak-to-peak
value)
VO(BIAS)
DC bias voltage
αstep
attenuation step size
(analog section)
Nstep
number of attenuation
steps
α
RES
attenuation = 0 dB,
differentially measured
between SKPRN and
SPRKP
1.0
1.25
1.5
V
-
-
100
mV
1.2
1.4
1.6
V
2.5
3.0
3.5
dB
-
24
-
-
attenuation
63
69
75
dB
resolution
-
12
-
bit
LE(d)(DAC)
DAC differential linearity
error
-
-
1
LSB
THD
total harmonic distortion
SPKRP/SKPRN
-
-
-35
dB
1 kΩ headphone load
-
-
-45
dB
16 Ω speaker; 100 Hz to
20 kHz bandwidth
40
-
-
dB
dB
S/N
signal-to-noise ratio
PBRR
pass-band ripple rejection fpla < fsig < fpha(6)
-
-
1.2
SBR
stop-band rejection
fsha < fsig < 20 kHz(6)
50
-
-
dB
OBR(RMS)
out-of-band rejection
(RMS value)
f > 20 kHz
-
-
50
mV
Zspeaker
speaker impedance
8
16
-
Ω
Telecom Input; notes 2 and 7
fst
sample frequency
-
-
10
kHz
VI(RMS)
input voltage (RMS value) differentially applied to
TINN and TINP;
no I/P attenuation enabled
(TEL_ATT = 0,
TEL_GAIN=0)
330
370
410
mV
VI(BIAS)
DC bias voltage
TINN/TINP
1.2
-
1.6
V
i
input
attenuationattenuation
input
attenuationamplification
enabled (TEL_ATT=1)
-6.5
-6
-5.5
dB
αi
input attenuationgain
input
attenuationamplification
enabled
(TEL_ATTAMPL = 1,
TEL_ATT=0)
5.5
6
6.5
dB
Zi
input impedance
25
-
-
kΩ
S/N
signal-to-noise ratio
65
75
-
dB
THD
total harmonic distortion
-
-76
-65
dB
1999 Jul 20
43
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
SYMBOL
LE(d)(ADC)
PARAMETER
UCB1300
CONDITIONS
ADC differential linearity
error
MIN.
-
TYP.
-
MAX.
2
UNIT
LSB
RES
resolution
-
14
-
bit
PBRR
pass-band ripple rejection fplt < fsig < fpht; no voice
filter(8)(16)
-
-
1.2
dB
fvht < fsig < fpht; voice filter
activated(8)(16)
-
-
1.2
dB
fsig < fvlt; voice filter
activated(8)(16)
30
-
-
dB
dB
SBR
stop-band rejection
fsht < fsig(8)(16)
50
-
-
Doffset
digital offset
no signal applied to MICP
-
-
50
LSB
Ssup
sidetone suppression
effectiveness
600 Ω line impedance; 1:1
transformer with 156 Ω
winding resistance
20
-
-
dB
Telecom output; note 5
fst
sample frequency
-
8
-
kHz
VO(RMS)
output voltage (RMS
value)
differentially measured
between TOUTP and
TOUTN
1.35
-
1.85
V
VO(BIAS)
DC bias voltage
TOUTP/TOUTN; telecom
O/P path enabled
1.2
-
1.6
V
RES
resolution
-
14
-
bit
S/N
signal-to-noise ratio
65
75
-
dB
THD
total harmonic distortion
-
-76
-65
dB
PBRR
pass-band ripple rejection
-
-
1.2
dB
SBR
stop-band rejection
fsht < f < fst(9)
70
-
-
dB
OBR(RMS)
out-of-band rejection
(RMS value)
f > fst(9)(16)
-
-
25
mV
Zo(load)
load impedance
Eoffset
offset error
note 10
-
-
100
mV
VI(BIAS)
bias voltage
touch screen position
mode selected
1.6
1.8
2.0
V
I
touch screen current
touch screen position
mode selected
10
-
-
mA
Ri
Max. touch screen
resistance to generate an
interrupt
touch screen interrupt
mode selected
-
-
2500
Ω
Rgs
ground switch on
resistance
-
-
50
Ω
Rps
power switch on
resistance
-
-
50
Ω
Ω
600
Touch screen
1999 Jul 20
44
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
SYMBOL
PARAMETER
UCB1300
CONDITIONS
tSTRTU
start up time of touch
screen bias voltage
generator
Eidle
Idle pressure reading
∆light_touch
Pressure reading:
pressure mode selected,
light-touch - 1.25xEidle(18) 2.2kΩ for light touch, open
for idle
MIN.
-
pressure mode selected,
open (no current drawn)
40
TYP.
MAX.
UNIT
-
25
µs
30
120
LSB
250
LSB
ADC; notes 11 and 12
RES
resolution
-
10
-
bit
VI(AD0-AD3)
full scale AD0 - AD3
inputs
7.0
7.5
8.0
V
Zi
input impedance
50
75
ILI
input leakage current
LE(d)(ADC)
ADC differential linearity
error
LE(i)(ADC)
ADC integral linearity
error
ten(ADC)
ADC enable time
td(s)
sampling delay
VADO = VAD1 = VAD2 =
VAD3 = 7.5 V
5 - 95 % of full scale
100
kΩ
10
µA
-
-
2
LSB
-
-
3
LSB
-
-
µs
non synchronization mode; no changing ADC
multiplexer settings
4tSIBCLK
-
ns
non synchronization mode; changing ADC multiplexer
settings
51tSIBCLK
-
ns
5
synchronization mode;
rising edge ADCSYNC to
sample moment
tSIBCLK
1.5tSIBCLK ns
tconv
conversion time
-
102tSIBCLK
ttrack
tracking time
5tSIBCLK
49tSIBCLK
-
ns
ns
tadcsync
ADCSYNC pulse width
5
-
-
ns
tsibwrite
control register update
after SIBSYNC falling
edge
-
65tSIBCLK
-
ns
On-chip reference circuit
Vi(ref)
reference voltage applied
to VREFBYP
1.0
1.2
1.4
V
tSTRTU
start-up time of internal
reference voltage circuit
-
-
50tSIBCLK
ns
0
-
15
MHz
-
50
-
%
Control register data transfer
fi(sibclk)
SIBCLK input frequency
δ(sibclk)
SIBCLK duty factor
1999 Jul 20
note 13
45
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
SYMBOL
PARAMETER
UCB1300
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tsu(SIBSYNC-SIBCLK) set-up time SIBSYNC to
SIBCLK falling edge
-
15
-
ns
th(SIBSYNC-SIBCLK)
SIBSYNC hold time after
falling edge of SIBCLK
-
10
-
ns
tsu(SIBDIN-SIBCLK)
set-up time SIBDIN to
SIBCLK falling edge
-
15
-
ns
th(SIBDIN-SIBCLK)
SIBDIN hold time after
falling edge of SIBCLK
-
10
-
ns
t(SIBCLK-SIBDOUT)
rising edge of SIBCLK to
valid SIBDOUT
note 14
-
10
-
ns
t(SIBDIN-SIBDOUT)
valid SIBDIN to valid
SIBDOUT
note 15
-
15
-
ns
Reset circuit
tW(NRESET)
RESET pulse width
tW(rst)
internal reset pulse width
5
-
-
ns
5tSIBCLK
-
ns
Notes
1. Additional test conditions: AUD_DIV[n] = 00001100; input signal 1 kHz, 90 mV (RMS); AUD_IN_ENA = 1.
2. Coding system for ADC output data is 2’s complement.
3. See Fig. 35.
4. Additional test conditions: AUD_DIV[n] = 00001100; 0 dB output attenuation; 90 % of digital full scale input voltage;
16 Ω speaker connected.
5. Additional test conditions: TEL_DIV[n] = 0101000; 0 dB output attenuation; 90 % of digital full scale input voltage;
1200 Ω load.
Coding system for DAC input data is 2’s complement.
6. See Fig. 36.
7. Additional test conditions: TEL_DIV[n] = 0101000; input signal 1 kHz, 300 mV (RMS); TEL_IN_ENA = 1;
TEL_VOICE_ENA = 0.
8. See Fig. 37.
9. See Fig. 38.
10. Deviation of the analog output from 0, with 0 code input to telecom output path.
11. The ADC cannot be started or armed if the touch screen circuit is set to interrupt mode (TSC_MODE[n] = 0,0).
12. Coding system for ADC is binary offset.
13. This is a requirement when an odd divisor is set in either the audio or the telecom codec.
14. This is valid for all SIB frame bits 0 to 63, except bits 17 to 20.
15. This is valid for a the SIB frame bits 17 to 20.
16. All curves repeat around the sample frequency fsa or fst for audio- respectively telecom codec.
17. Any touch-screen resistor above the maximum will not reach full scale and not saturate the ADC
18. The threshold can be used to verify a valid touch using pressure measurement.
1999 Jul 20
46
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
FREQUENCY RESPONSE CURVES
RIPia
0dB
f pla = 0.0016 × f sa
f pha = 0.42 × f sa
f sha = 0.6 × f sa
SBRia
Fpla
Frequency [Hz]
Fpha
Fsha
Fig.35 Audio input path frequency response.
RIPoa
0dB
f pla = 0.0016 × f sa
f pha = 0.42 × f sa
f sha = 0.6 × f sa
SBRoa
Fpla
Frequency [Hz]
Fpha
Fig.36 Audio output filter frequency response.
1999 Jul 20
47
Fsha
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
RIPti
f plt = 0.0016 × f st
f pht = 0.42 × f st
0dB
f sht = 0.6 × f st
f vlt = 0.018 × f st
f vht = 0.05 × f st
Voice filter enabled
SBRvti
SBRsht
Fplt
Fvlt
Fvht
Fpht
Fsht
Fig.37 Telecom input frequency response
RIPto
0dB
f plt = 0.0016 × f st
f pht = 0.42 × f st
f sht = 0.6 × f st
SBRhto
Fplt
Frequency [Hz]
Fig.38 Telecom output frequency response.
1999 Jul 20
48
Fpht
Fsht
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
CONTROL REGISTER OVERVIEW
BIT
MODE
SYMBOL
REMARK
RESET
Address 0: I/O port data register
0 to 9
R/W
IO_DATA[n]
The bits in the write register provide the data of the I/O pin
when programmed as output.
The bits in the read register return the actual state of the
associated I/O pin.
0
Address 1: I/O port direction register
0 to 9
R/W
IO_DIR[n]
If '1', the associated I/O pin is defined as output.
If ‘0', the associated I/O pin is defined as input.
0
15
R/W
SIB_ZERO
If ‘1’, the SIBDOUT pin is forced ‘0’ during the second SIB
word.
If '0', the SIBDOUT pin is three-stated during the second SIB
word.
0
Address 2: Rising edge interrupt enable register
0 to 9
R/W
IO_RIS_INT[n]
If '1', the rising edge interrupt of the associated I/O pin is
enabled.
0
11
R/W
ADC_RIS_INT
If '1', the rising edge interrupt of the adc_ready signal is
enabled.
0
12
R/W
TSPX_RIS_INT
If '1', the rising edge interrupt of the TSPX signal is enabled.
0
13
R/W
TSMX_RIS_INT
If '1', the rising edge interrupt of the TSMX signal is enabled.
0
14
R/W
TCLIP_RIS_INT
If '1', the rising edge interrupt of the telecom clip is enabled.
0
15
R/W
ACLIP_RIS_INT
If '1', the rising edge interrupt of the audio clip is enabled.
0
Address 3: Falling edge interrupt enable register
0 to 9
R/W
IO_FAL_INT[n]
If '1', the falling edge interrupt of the associated I/O pin is
enabled.
0
11
R/W
ADC_FAL_INT
If '1', the falling edge interrupt of the adc_ready signal is
enabled.
0
12
R/W
TSPX_FAL_INT
If '1', the falling edge interrupt of the TSPX signal is enabled.
0
13
R/W
TSMX_FAL_INT
If '1', the falling edge interrupt of the TSMX signal is enabled.
0
14
R/W
TCLIP_FAL_INT
If '1', the falling edge interrupt of the telecom clip is enabled.
0
15
R/W
ACLIP_FAL_INT
If '1', the falling edge interrupt of the audio clip is enabled.
0
A '0' to '1' transition clears the interrupt of the associated I/O
pin.
0
Address 4: Interrupt clear/status register
0 to 9
11
12
13
W
IO_INT_CLR[n]
R
IO_INT_STAT[n]
Returns the actual interrupt status of the associated I/O pin
0
W
ADC_INT_CLR
A '0' to '1' transition clears the interrupt adc_ready signal.
0
R
ADC_INT_STAT
Returns the actual interrupt status of the adc_ready signal.
0
W
TSPX_INT_CLR
A '0' to '1' transition clears the interrupt of the TSPX signal.
0
R
TSPX_INT_STAT
Returns the actual interrupt status of the TSPX signal.
0
W
TSMX_INT_CLR
A '0' to '1' transition clears the interrupt of the TSMX signal.
0
R
TSMX_INT_STAT
Returns the actual interrupt status of the TSMX signal.
0
1999 Jul 20
49
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
BIT
14
15
MODE
SYMBOL
UCB1300
REMARK
RESET
W
TCLIP_INT_CLR
A '0' to '1' transition clears the interrupt of the telecom clip.
0
R
TCLIP_INT_STAT
Returns the actual interrupt status of the telecom clip.
0
W
ACLIP_INT_CLR
A '0' to '1' transition clears the interrupt of the audio clip.
0
R
ACLIP_INT_STAT
Returns the actual interrupt status of the audio clip.
0
Address 5: Telecom control register A
0 to 6
R/W
TEL_DIV[n]
Telecom codec sample rate divisor. Valid values lie between16
[0010000] and 127 [1111111].
16
7
R/W
TEL_AMPL
If '1', the additional input gain of the telecom codec is enabled
(+6dB).
0
Address 6: Telecom control register B
3
R/W
TEL_VOICE_ENA
If '1', the voice band filter in the telecom input path is enabled. 0
4
R
TEL_CLIP_STAT
Returns the telecom clip detection status. (the telecom clip
status will remain set until cleared by the user).
0
W
TEL_CLIP_CLR
A '0' to '1' transition clears the telecom clip detection status.
0
6
R/W
TEL_ATT
If '1', the telecom input attenuation (-6 dB) is enabled. This
control overrides the TEL_AMPL control.
0
11
R/W
TEL_SIDE_ENA
If '1', the sidetone suppression circuit is activated.
0
13
R/W
TEL_MUTE
If '1', the telecom output is muted.
0
14
R/W
TEL_IN_ENA
If '1', the telecom input path is activated.
0
15
R/W
TEL_OUT_ENA
If '1', the telecom output path is activated.
0
Address 7: Audio control register A
0 to 6
R/W
AUD_DIV[n]
Audio codec sample rate divisor. Valid values lie between 6
[0000110] and 127 [1111111].
9
7 to 11
R/W
AUD_GAIN[n]
Audio input gain setting. Values range from 0 dB [00000] to
46.5 dB [11111]
0
Address 8: Audio control register B
0 to 4
R/W
AUD_ATT[n]
Audio output attenuation setting. Values range from 0 dB
[00000] to 69 dB [11111].
0
6
R
AUD_CLIP_STAT
Returns the audio clip detection status. If '1', the audio clip
detection circuit is activated (The audio clip status will remain
set until it is cleared by the user)
0
W
AUD_CLIP_CLR
If ‘0’ to ‘1’ transition clears the audio clip detection status.
0
8
R/W
AUD_LOOP
If '1', the loopback mode in the audio codec is activated.
0
13
R/W
AUD_MUTE
If '1', the audio output is muted.
0
14
R/W
AUD_IN_ENA
If'1, the audio codec input path is activated.
0
15
R/W
AUD_OUT_ENA
If '1', the audio codec output path is activated.
0
Address 9:Touch screen control register
0
R/W
TSMX_POW
If ‘1’, the TSMX pin is powered.
0
1
R/W
TSPX_POW
If ‘1’, the TSPX pin is powered.
0
2
R/W
TSMY_POW
If ‘1’, the TSMY pin is powered.
0
3
R/W
TSPY_POW
If ‘1’, the TSPY pin is powered.
0
1999 Jul 20
50
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
BIT
MODE
UCB1300
SYMBOL
REMARK
RESET
4
R/W
TSMX_GND
If ‘1’, the TSMX pin is grounded.
0
5
R/W
TSPX_GND
If ‘1’, the TSPX pin is grounded.
0
6
R/W
TSMY_GND
If ‘1’, the TSMY pin is grounded.
0
7
R/W
TSPY_GND
If ‘1’, the TSPY pin is grounded.
0
8 and 9
R/W
TSC_MODE[n]
Touch screen operation mode:
0
00: interrupt mode
01: pressure measurement mode
1x: position measurement mode.
11
R/W
TSC_BIAS_ENA
If ‘1’, the touch screen bias circuit is activated.
0
12
R
TSPX_LOW
This bit returns the inverted state of the TSPX pin, ‘0’ is a high
voltage (pen up), ‘1’ is a low voltage (pen down).
0
13
R
TSMX_LOW
This bit returns the inverted state of the TSMX pin, ‘0’ is a high
voltage (pen up), ‘1’ is a low voltage (pen down).
0
Address 10: ADC control register
0
R/W
ADC_SYNC_ENA
If ‘1’, the ADC sync mode is activated.
1
R/W
VREFBYP_CON
If ‘1’, the internal reference voltage is connected to VREFBYP
(pin 16).
2 to 4
R/W
ADC_INPUT[n]
ADC input select:
0
000: TSPX
100: AD0
001: TSMX
101: AD1
010: TSPY
110: AD2
011: TSMY
110: AD3
5
R/W
EXT_REF_ENA
If ‘1’, an external reference voltage has to be applied to
VREFBYP.
0
7
R/W
ADC_START
A ‘0’ to ‘1’ transition starts the ADC conversion sequence.
0
15
R/W
ADC_ENA
If ‘1’, the ADC circuit is activated.
0
Address 11: ADC data register
5 to 14
R
ADC_DATA[n]
Returns the ADC result
0
15
R
ADC_DAT_VAL
Returns '0' if an ADC conversion is in progress. Returns '1' if
the ADC conversion is completed and the ADC data is stored
in the ADC_DATA[n] register.
0
Address 12: ID register
0 to 5
R
VERSION[n]
Returns 0001010 for all the UCB1300 circuits meeting this
specification
0
6 to 11
R
DEVICE[n]
Returns 000000 for all the UCB1300 circuits meeting this
specification
0
SUPPLIER[n]
Returns 0001 for all the UCB1300 circuits meeting this
specification
0
12 to 15 R
1999 Jul 20
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
BIT
MODE
SYMBOL
UCB1300
REMARK
RESET
Address 13: MODE register; note 1
0
R/W
AUD_TEST
If ‘1’, the analog audio test mode is activated.(2)
0
1
R/W
TEL_TEST
If ‘1’, the analog telecom test mode is activated.(2)
0
modes.(2)
2 to 5
R/W
PROD_TEST_MODE
These bits select the built-in production test
12
R/W
DYN_VFLAG_ENA
If ‘1’, the dynamic data valid flag mode is activated for both the
audio and the telecom data valid flag.
13
R/W
AUD_OFF_CAN
If ‘1’ the offset cancelling circuit in the audio path is enabled
14
R/W
A_BIG_ENDIAN
0
15
R/W
T_BIG_ENDIAN
0
Address 14: Reserved
Reserved for future use.
Address 15: NULL register
0 to 15
R
Returns [1111111111111111] at all times
Notes
1. Activating one or more test modes changes the functionality of the UCB1300.
2. TEST (pin 13) must be HIGH when writing to these bits.
1999 Jul 20
52
0
0
0
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
PACKAGE OUTLINES
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
94-12-19
97-08-01
SOT313-2
1999 Jul 20
EUROPEAN
PROJECTION
53
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
SOLDERING
Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and
surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for
surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often
used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“IC Package Databook” (order code 9398 652 90011).
Reflow soldering
Reflow soldering techniques are suitable for all LQFP packages.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the
printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between
50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following conditions must be observed:
• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering
technique should be used.
• The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less
than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a
dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
1999 Jul 20
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
RIGHT TO MAKE CHANGES
Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsiblility or liability for the use of any of these products, conveys no license or title
under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these
products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Philips Semiconductors
@ Copyright PHilips Electronics North America Corporation 1999
811 East Arques Avenue
All rigths reserved. Printed in U.S.A.
P.O. Box 3409
Date of release: 07-99
Sunnyvale, California 94088-3409
Telephone 800-234-7381
Document order number:
1999 Jul 20
55
9397 750 06225
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
1999 Jul 20
56
UCB1300