Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 FEATURES PIN CONFIGURATION • Specifically designed for Video applications • Combines the 74F373, two 74F157s, and the 74F166 functions in PE 1 24 VCC CP 2 23 D3B D4A 3 22 D3A D4B 4 21 D2B D5A 5 20 D2A D5B 6 19 D1B D6A 7 18 D1A D6B 8 17 D0B DESCRIPTION D7A 9 16 D0A The 74F835 is a high speed 8-bit parallel/serial-in, serial-out shift register whose parallel inputs have been connected to an internal octal two-to-one multiplexer with all the “B” inputs connected to an octal latch. D7B 10 one package • Interleaved loading with 2:1 mux • Dual 8-bit parallel inputs • Transparent latch on all “B” inputs • Guaranteed serial shift frequency to 100MHz • Expandable to 16-bits or more with serial input 15 DS Q7 11 14 SA/B GND 12 13 LE SF01355 This 24-pin part is specifically designed for video bit shifting, where interleaved loading is desired and parts count is critical. It is useful in any design where a 2:1 mux input with a transparent latch is needed. ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PACKAGE DRAWING NUMBER TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 24-pin plastic Slim DIP (300 mil) N74F835N SOT222-1 74F835 150MHz 45mA 24-pin plastic SOL N74F835D SOT137-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0A – D7A Parallel data inputs 1.0/1.0 20µA/0.6mA D0B – D7B Latched Parallel data inputs 1.0/1.0 20µA/0.6mA DS Serial data input 1.0/1.0 20µA/0.6mA CP Shift Register Clock input (active rising edge) 1.0/1.0 20µA/0.6mA Mux Select 1.0/1.0 20µA/0.6mA LE Latch Enable input (for B inputs) 1.0/1.0 20µA/0.6mA PE Parallel Enable input 1.0/1.0 20µA/0.6mA Q7 Output 50/33 1.0mA/20mA SA/B NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. 1990 Jan 08 1 853–0615 99490 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 LOGIC SYMBOL IEC/IEEE SYMBOL SRG 8 2 15 16 17 18 19 20 21 22 23 3 4 5 6 7 8 C1 9 10 MUX 1 13 DS 2 CP D0B D1B D2B D3B D4B D5B D6B D7B D0A D1A D2A D3A D4A D5A D6A D7A 1 PE 13 LE 14 SA/B 14 15 16 17 Q7 18 M4 EN3 G2 1,4 1, 2, 3, 4 1, 2, 3, 4 19 20 21 11 22 VCC = PIN 24 GND = PIN 12 23 SF01356 3 4 5 6 7 8 9 11 10 SF01357 TYPICAL TIMING DIAGRAM UNLOAD B LATCH LOAD A PE SHIFT A SHIFT B CP ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉ ÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ LOAD B LATCH LE SA/B D0A D7A D0B D7B q7A q6A ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ SET B q1A q0A q7B q6B q5B ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ q0B Q7 SF01359 1990 Jan 08 2 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 LOGIC DIAGRAM D0A 16 D0B 17 D1B 19 D2B 21 D1A 18 D3B 23 D2A 20 D4B 4 D3A 22 D4A 3 D5A 5 D5B 6 D6B 8 D7B 10 D6A 7 D7A 9 13 LE D Q SA/B PE DS E D Q D Q E D Q E D Q E D Q E D Q E D Q E 14 1 15 D Q D CP CP E Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q 11 Q7 CP 2 VCC = PIN 24 GND = PIN 12 SF01358 FUNCTION TABLE INTERNAL INPUTS OPERATING MODE PE CP LE SERIAL REGISTER OUTPUT SA/B DnA DnB DS B LATCH Q0 Q1–6 Q7 X X X X X X H L H L H L Parallel load A data L ↑ X L h l Latch B data X X L X X X h l X X H L X X X X X X Parallel load B data (from Latch) L ↑ L H X X X X X X h l H L H L H L Parallel load B data (Transparent Mode) L ↑ H H X X h l X X h l H L H L H L Serial Shift H ↑ X X X X X X h l X X H L qn–1 qn–1 q6 q6 H L h l X qn ↑ = = = = = = = High voltage level Low voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level one setup time prior to the Low-to-High clock transition Don’t care Lower case letters indicate the state of the referenced flop cell one cycle prior to the Low-to-High clock transition Low-to-High clock transition 1990 Jan 08 3 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature range –30 to +5 mA –0.5 to VCC V 40 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range +70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 LIMITS MIN ±10% VCC 2.5 ±5% VCC 2.7 TYP2 MAX UNIT V VOH High-level output voltage VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX VOL Low-level output voltage VCC = MIN, VIL = MAX VIH = MIN, IOHL= MAX VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOS Short circuit output current3 VCC = MAX –150 mA ICC Supply current (total) VCC = MAX 65 mA 3.4 V ±10% VCC 0.30 0.50 V ±5% VCC 0.30 0.50 V –0.73 –1.2 V 100 µA –60 45 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V. Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other tests. In any sequence of parameter tests, IOS tests should be performed last. 1990 Jan 08 4 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITION MIN TYP Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MAX MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 130 150 tPLH tPHL Propagation delay CP to Q7 (Load) Waveform 1 5.0 5.0 7.0 7.0 9.5 9.5 100 5.0 5.0 10.0 10.0 MHz ns tPLH tPHL Propagation delay CP to Q7 (Shift) Waveform 1 5.0 5.0 7.0 7.0 9.5 9.5 5.0 5.0 10.0 10.0 ns TEST CONDITION Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER MIN ts(H) ts(L) Setup time DnA or DnB to CP th(H) th(L) TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX Waveform 2 3.5 3.5 3.5 3.5 ns Hold time DnA or DnB to CP Waveform 2 1.0 1.0 1.5 1.5 ns ts(H) ts(L) Setup time DS to CP Waveform 2 1.0 1.0 1.5 1.5 ns th(H) th(L) Hold time DS to CP Waveform 2 2.0 2.0 2.5 2.5 ns ts(H) ts(L) Setup time PE to CP Waveform 2 3.5 3.5 4.0 4.0 ns th(H) th(L) Hold time PE to CP Waveform 2 0.0 0.0 0.0 0.0 ns ts(H) ts(L) Setup time DnB to LE Waveform 2 0.0 0.0 0.0 0.0 ns th(H) th(L) Hold time DnB to LE Waveform 2 3.0 3.0 4.0 4.0 ns ts(H) ts(L) Setup time SA/B to CP Waveform 2 4.5 4.5 5.0 5.0 ns th(H) th(L) Hold time SA/B to CP Waveform 2 0.0 0.0 0.0 0.0 ns tw(H) tw(L) clock pulse width, High or Low Waveform 1 4.5 4.5 5.5 5.0 ns tw(H) Latch Enable pulse width, High Waveform 1 4.5 5.0 ns 1990 Jan 08 5 Philips Semiconductors Product specification 8-bit shift register with 2:1 mux-in, latched “B” inputs, and serial out 74F835 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP VM DS, PE VM tW(H) VM DnA, DnB SA/B VM VM th(H) ts(H) tW(L) ts(L) VM th(L) tPLH tPHL CP, LE Q7 VM VM VM VM VM SF00287 SF01360 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Waveform 2. Data and Select Setup and Hold Times TEST CIRCUIT AND WAVEFORMS VCC VIN tw 90% NEGATIVE PULSE 10% D.U.T. RT CL RL AMP (V) VM VM VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% POSITIVE PULSE VM VM 10% Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1990 Jan 08 6