Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 FEATURES PIN CONFIGURATION • Buffered clock and control inputs • Shift right and parallel load capability • Fully synchronous data transfers • J-K(D) inputs to first stage • Clock enable for hold (do nothing) mode • Asynchronous Master Reset K 1 DESCRIPTION The 74F199 is an 8-bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. The device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial-to-parallel, or parallel–to-serial data transfers at very high speeds. 24 VCC J 2 23 PE D0 3 22 D7 Q0 4 21 Q7 D1 5 20 D6 Q1 6 19 Q6 D2 7 18 D5 Q2 8 17 Q5 D3 9 16 D4 Q3 10 15 Q4 CE 11 14 MR GND 12 13 CP SF00152 The 74F199 operates in two primary modes: shift right (Q0→Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is High, and is shifted one bit in the direction Q0→Q1→Q2 following each Low-to-High clock transition. The J and K inputs provide the flexibility of the J-K type input for special applications, and by tying the two together the simple D-type input is made for general applications. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F199 95MHz 70mA ORDERING INFORMATION The device appears as eight common clocked D flip-flops when the PE input is Low. After the Low-to-High clock transition, data on the parallel inputs (D0–D7) is transferred to the respective Q0–Q7 outputs. All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The 74F199 utilizes edge-triggered, therefore there is no restriction on the activity of the J, K, Dn, and PE inputs for logic operation, other than the setup and hold time requirements. DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 24-pin plastic slim DIP (300mil) N74F199N 24-pin plastic SOL N74F199D A Low on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously forcing all bit positions to a Low state. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Parallel data inputs 1.0/1.0 20µA/0.6mA J, K J and K inputs 1.0/1.0 20µA/0.6mA PE Parallel Enable input 1.0/1.0 20µA/0.6mA CE Clock Enable input 1.0/1.0 20µA/0.6mA DP Clock Pulse inputs (Active rising edge) 1.0/1.0 20µA/0.6mA MR Master Reset input (Active Low) 1.0/1.0 20µA/0.6mA Data outputs 50/33 1.0mA/20mA D0–D7 Q0–Q7 DESCRIPTION NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. June 15, 1988 1 853–0082 93568 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 LOGIC SYMBOL IEEE/IEC SYMBOL 3 5 7 9 16 18 SRG8 20 22 D0 D1 D2 D3 D4 D5 D6 D7 23 PE 2 J 1 11 1 13 1 23 C3 14 R & K 2 2J 13 CP 1 2K 11 CE 3 2, 3D 14 MR 5 2, 3D Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 6 8 10 15 17 19 21 VCC = Pin 24 GND = Pin 12 C2/→ 4 6 7 8 9 10 16 15 18 17 20 19 22 21 SF00153 SF00154 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES MR CP CE PE J K Dn Q0 Q1 … Q6 Q7 L X X X X X X L L … L L Reset (clear H ↑ l h h h X H q0 … q5 q6 Shift, set First stage H ↑ l h l l X L q0 … q5 q6 Shift, reset First stage H ↑ l h h l X q0 q0 … q5 q6 Shift, toggle First stage H ↑ l h l h X q0 q0 … q5 q6 Shift, retain First stage H ↑ l l X X dn d0 d1 … d6 d7 Parallel load H ↑ h X X X X q0 q1 … q6 q7 Hold (do nothing) H h L l X ↑ dn(qn) = = = = = = = High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior t the Low-to-High clock transition Don’t care Low-to-High clock transition Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition June 15, 1988 2 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 LOGIC DIAGRAM CE 11 CP 13 PE 23 J 2 K 1 R CP MR 14 D0 3 D1 5 S Q Q0 Q RD R CP 4 S Q 6 Q1 RD D2 7 R CP S Q 8 Q2 RD D3 9 R CP S Q 10 Q3 RD D4 16 R CP S Q 15 Q4 RD D5 18 R CP S Q 17 Q5 RD D6 20 R CP S Q 19 Q6 RD D7 22 R CP S Q 21 Q7 RD SF00155 June 15, 1988 3 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 TYPICAL TIMING DIAGRAM CP CE MR SERIAL INPUTS J K PE D0 H L D1 D2 PARALLEL DATA INPUTS D3 H L D4 D5 H L D6 H D7 H Q0 Q1 Q2 OUTPUTS Q3 Q4 Q5 Q6 Q7 H H L L H L H H INHIBIT SERIAL SHIFT SERIAL SHIFT CLEAR LOAD Typical Load, Serial-Shift, Inhibit and Clear Sequences SF00156 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL RATING UNIT VCC Supply voltage PARAMETER –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range +70 °C June 15, 1988 0 4 V V Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL LIMITS TEST CONDITIONS1 PARAMETER MIN TYP2 UNIT MAX VCC = MIN, VIL = MAX ±10%VCC 2.5 VIH = MIN, IOH = MAX ±5%VCC 2.7 VCC = MIN, VIL = MAX ±10%VCC 0.35 0.50 VIH = MIN, IOL = MAX ±5%VCC 0.35 0.50 –0.73 –1.2 V VCC = MAX, VI = 7.0V 100 µA High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOS Short-circuit output current3 VCC = MAX –150 mA ICC Supply current (total) VOH High-level output voltage VOL Low-level output voltage VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage IIH ICCH ICCL VCC = MAX V 3.4 V –60 65 90 75 105 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. June 15, 1988 5 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω TEST CONDITION MIN TYP VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MAX MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 80 95 70 MHz tPLH tPHL Propagation delay CP to Qn Waveform 1 5.5 6.5 8.0 9.5 11.0 12.5 4.5 3.5 12.0 13.5 ns tPHL Propagation delay MR to Qn Waveform 2 5.5 8.0 10.5 5.0 12.0 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω TEST CONDITION MIN TYP MAX VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN UNIT MAX tS(H) tS(L) Setup time, High or Low Dn to CP Waveform 3 0.0 1.5 0.0 2.5 ns th(H) th(L) Hold time, High or Low Dn to CP Waveform 3 2.0 4.5 2.5 5.5 ns ts(H) ts(L) Setup time, High or Low J, K to CP Waveform 3 0.0 2.5 0.0 3.0 ns th(H) th(L) Hold time, High or Low J, K to CP Waveform 3 0.0 3.5 0.0 4.0 ns ts(H) ts(L) Setup time, High or Low CE to CP Waveform 3 0.0 2.5 0.0 3.0 ns th(H) th(L) Hold time, High or Low CE to CP Waveform 3 0.0 4.5 0.0 5.5 ns ts(H) ts(L) Setup time, High or Low PE to CP Waveform 3 8.0 8.0 9.0 9.0 ns th(H) th(L) Hold time, High or Low PE to CP Waveform 3 0.0 0.0 0.0 0.0 ns tw(H) CP pulse width, High Waveform 1 4.5 5.5 ns tw(L) MR pulse width, Low Waveform 2 4.0 4.5 ns trec Recovery time MR to CP Waveform 2 5.5 6.5 ns June 15, 1988 6 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. MR 1/fMAX CP VM VM VM tw(L) VM tREC CP tw(H) VM tPLH tPHL tPHL Qn VM Qn VM SF00157 SF00158 Waveform 1. Propagation Delay, Clock Input to Output, Clock Widths, and Maximum Clock Frequency CE VM ts(L) PE VM ts(H) VM VM th = 0 ts(L) th = 0 VM th J, K VM STABLE ts CP th = 0 VM STABLE ts VM th ts(L) Dn Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time VM VM th VM VM SF00159 Waveform 3. Setup Time and Hold Time June 15, 1988 7 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 TEST CIRCUIT AND WAVEFORMS VCC VIN tw 90% NEGATIVE PULSE 10% D.U.T. RT CL RL AMP (V) VM VM VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% POSITIVE PULSE VM VM 10% Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 June 15, 1988 8