Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) FEATURES 74F674 PIN CONFIGURATION • 16-bit serial I/O shift register • 16-bit parallel-in/serial-out converter • Recirculating serial shifting • Common serial data I/O pin (3-State) CS 1 24 VCC CP 2 23 D15 R/W 3 22 D14 NC 4 21 D13 DESCRIPTION The 74F674 is a 16-bit shift register with serial and parallel load capability and serial output. A single pin serves alternately as an input for serial entry or as a 3-State serial output. In the serial out mode the data recirculates in the register. Chip Select, Read/Write and Mode inputs provide control flexibility. The 74F674 operates in one of four modes, as indicated in the Function table. Hold: A High signal on the Chip Select (CS) input prevents clocking and forces the Serial Input/Output (SI/O) 3-State buffer into the high impedance state. M 5 20 D12 SI/O 6 19 D11 D0 7 18 D10 D1 8 17 D9 D2 9 16 D8 D3 10 15 D7 D4 11 14 D6 GND 12 13 D5 Serial load: Data present on the SI/O pin shifts into the register on the falling edge of CP. Data enters the Q0 position and shifts toward Q15 on successive clocks. SF01188 Serial output: The SI/O 3-State buffer is active and the register contents are shifted out from Q15 and simultaneously shifted back into Q0. Parallel load: Data present on D0–D15 is entered into the register on the falling edge of CP. The SI/O 3-State buffer is active and represents the Q15 output. To prevent false clocking, CP must be Low during a Low-to-High transition of CS. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F674 95MHz 55mA ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 24-Pin Plastic Slim DIP (300mil) N74F674N 24-Pin Plastic SOL N74F674D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0–D15 Parallel data inputs 1.0/1.0 20µA/0.6mA CS Chip Select input (active Low) 1.0/1.0 20µA/0.6mA CP Clock Pulse input (active falling edge) 1.0/1.0 20µA/0.6mA M Mode select input 1.0/1.0 20µA/0.6mA R/W Read/Write input 1.0/1.0 20µA/0.6mA Serial data input or 3.5/1.0 70mA/0.6mA Serial 3-state output 150/40 3.0mA/24mA SI/O NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state. 1989 Feb 05 1 853–1248 92263 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) LOGIC SYMBOL 7 8 9 10 74F674 LOGIC SYMBOL (IEEE/IEC) 11 13 14 15 16 17 18 19 20 21 22 23 SRG16 5 0 0 M 3 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3 & 1 CS 2 CP 3 R/W 5 M 1 & C4(0/1/2) 2 SO 7 8 VCC = Pin 24 GND = Pin 12 EN 3, 4D 3, 4D 3, 4D 9 6 SF01189 10 11 13 FUNCTION TABLE 14 CONTROL INPUTS H L X ↓ CS R/W M CP SI/O STATUS H X X X High Z Hold L L X ↓ Data in Serial load L H L ↓ Data out L H H ↓ Active = = = = 15 OPERATING MODE 16 17 18 19 Serial output with recirculation 20 Parallel load; no shifting 22 21 23 High voltage level Low voltage level Don’t care High-to-Low transition of designed input 6 3, 4D SF01190 LOGIC DIAGRAM D0–D15 (7–11, 13–23) M CS 5 1 PE D0–D15 Q0 Q15 CP R/W VCC = GND = 2 3 Pin 24 Pin 12 1989 Feb 05 6 SI/O CP SF01191 2 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) 74F674 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5.0 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state 48 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –3 mA IOL Low-level output current 24 mA Tamb Operating free-air temperature range 70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL LIMITS TEST CONDITIONS1 PARAMETER MIN VOH High-level output voltage VOL Low-level output voltage VIK Input clamp voltage II Input current at maximum input voltage IIH VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX ±10%VCC 2.4 ±5%VCC 2.7 TYP2 UNIT MAX V 3.3 V ±10%VCC 0.35 0.50 V ±5%VCC 0.35 0.50 V –0.73 –1.2 V VCC = MIN, II = IIK SI/O only VCC = MAX, VI = 5.5V 100 µA others VCC = MAX, VI = 7.0V 100 µA High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOZH+IIH Off-state output current High-level voltage applied VCC = MAX, VO = 2.7V 70 µA IOZL+IIL Off-state output current Low-level voltage applied VCC = MAX, VO = 0.5V –600 µA IOS Short-circuit output current3 VCC = MAX –150 mA ICC Supply current (total) VCC = MAX 80 mA SI/O only –60 55 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value under the recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS should be performed last. 1989 Feb 05 3 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) 74F674 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITIONS MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MIN TYP fMAX Maximum clock frequency Waveform 1 80 95 MAX tPLH tPHL Propagation delay CP to SI/O Waveform 1 7.0 6.0 9.5 8.5 12.5 11.5 6.5 5.5 14.0 12.5 ns ns tPZH tPZL Output Enable time CS to SI/O Waveform 3 Waveform 4 5.5 7.0 8.5 9.5 11.0 12.5 5.0 6.5 12.5 14.0 ns ns tPHZ tPLZ Output Disable time CS to SI/O Waveform 3 Waveform 4 3.0 4.5 6.0 7.5 8.5 10.0 3.0 4.5 10.0 11.5 ns ns tPZH tPZL Output Enable time R/W to SI/O Waveform 3 Waveform 4 6.0 7.5 8.5 10.0 11.5 13.0 5.5 7.0 13.0 14.0 ns ns tPHZ tPLZ Output Disable time R/W to SI/O Waveform 3 Waveform 4 5.0 5.5 7.5 8.0 10.5 11.0 4.5 5.0 12.0 13.5 ns ns 70 MHz AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITION MIN ts(H) ts(L) Setup time, High or Low SI/O to CP th(H) th(L) TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX Waveform 2 2.0 2.0 2.5 2.5 ns ns Hold time, High or Low SI/O to CP Waveform 2 1.5 1.5 2.0 2.0 ns ns ts(H) ts(L) Setup time, High or Low Dn to CP Waveform 2 1.5 1.0 2.0 1.0 ns ns th(H) th(L) Hold time, High or Low Dn to CP Waveform 2 3.0 4.0 3.0 4.0 ns ns ts(H) ts(L) Setup time, High or Low M to CP Waveform 2 2.0 5.5 2.5 6.0 ns ns th(H) th(L) Hold time, High or Low M to CP Waveform 2 0.0 0.0 1.0 1.0 ns ns ts(L) Setup time, Low CS to CP Waveform 2 8.0 9.0 ns th(H) Hold time, High CS to CP Waveform 2 0.0 0.0 ns tw(H) tw(L) CP Pulse width, High or Low Waveform 1 3.5 4.5 4.0 5.0 ns ns 1989 Feb 05 4 Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register (3-State) 74F674 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP VM VM tW(L) Dn, CS, M, R/W, SI/O VM VM VM ts(H) th(H) VM ts(L) th(L) tW(H) tPLH tPHL VM CP SI/O VM VM VM VM SF01192 SF01193 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency CS, R/W VM Waveform 2. Setup and Hold Times CS, R/W VM tPZH VOH -0.3V tPHZ SI/O VM VM tPZL tPLZ SI/O VM VM 0V VOL +0.3V SF01195 SF01194 Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00777 1989 Feb 05 5