Philips Semiconductors Advanced BiCMOS Products Product specification Synchronizing dual D-type flip-flop with metastable immune characteristics FEATURES 74ABT5074 PIN CONFIGURATION • Metastable immune characteristics • Pin compatible with 74F74 and 74F5074 • Typical fMAX = 200MHz • Output skew guaranteed less than 2.0ns • High source current (IOH = 15mA) ideal for clock driver RD0 1 14 VCC D0 2 13 RD1 CP0 3 12 D1 SD0 4 11 CP1 Q0 5 10 SD1 Q0 6 9 Q1 GND 7 8 Q1 applications • Output capability: +20mA/–15mA • Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 SA00001 PIN DESCRIPTION and 200V per Machine Model DESCRIPTION PIN NUMBER SYMBOL 2, 12 D0, D1 3, 11 CP0, CP1 Clock inputs (active rising edge) 4, 10 SD0, SD1 Set inputs (active-Low) 1, 13 RD0, RD1 Reset inputs (active-Low) 5, 9 Q0, Q1 Data outputs (active-Low), non-inverting 6, 8 Q0, Q1 Data outputs (active-Low), inverting 7 GND Ground (0V) 14 VCC Positive supply voltage The 74ABT5074 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set and reset inputs; also true and complementary outputs. Set (SDn) and reset (RDn) are asynchronous active low inputs and operate independently of the clock (CPn) input. Data must be stable just one setup time prior to the low-to-high transition of the clock for guaranteed propagation delays. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output. The 74ABT5074 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74ABT5074 are: NAME AND FUNCTION Data inputs τ ≅ 94ps and To ≅ 1.3 × 107 sec where τ represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state. QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 2.8 2.4 ns tPLH tPHL Propagation delay CPn to Qn or Qn CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 3 pF ICC Total supply current Outputs disabled; VCC =5.5V 2 µA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 14-pin plastic DIP –40°C to +85°C 74ABT5074N SOT27-1 14-pin plastic SOL –40°C to +85°C 74ABT5074D SOT108-1 14-pin plastic shrink small outline SSOP Type II –40°C to +85°C 74ABT5074DB SOT337-1 14-pin plastic thin shrink small outline (TSSOP) Type I –40°C to +85°C 74ABT5074PW SOT402-1 December 15, 1994 1 853-1775 14470 Philips Semiconductors Advanced BiCMOS Products Product specification Synchronizing dual D-type flip-flop with metastable immune characteristics LOGIC SYMBOL 74ABT5074 IEC/IEEE SYMBOL 2 12 4 S D0 D1 5 3 C1 3 CP0 4 SD0 1 RD0 2 1D 6 1 11 CP1 10 SD1 13 RD1 R 10 S 9 11 C2 12 Q0 Q0 Q1 Q1 2D 8 13 R VCC = Pin 14 GND = Pin 7 5 6 9 8 SA00002 SA00003 LOGIC DIAGRAM FUNCTION TABLE INPUTS SD RD CP D OUTPUTS 4, 10 1, 13 3, 11 5, 9 Q 6, 8 Q MODE SD RD CP D Q Q L H X X H L Asynchronous set H L X X L H Asynchronous reset L L X X L H Undetermined* H H ↑ h H L Load ”1” H H ↑ l L H Load ”0” H H ↑ X NC NC 2, 12 Hold NOTES: H = High voltage level h = High voltage level one setup time prior to low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock transition NC= No change from the previous setup X = Don’t care ↑ = Low-to-high clock transition ↑ = Not low-to-high clock transition * = This setup is unstable and will change when either set or reset return to the high level VCC = Pin 14 GND = Pin 7 SF00048 December 15, 1994 OPERATING 2 Philips Semiconductors Advanced BiCMOS Products Product specification Synchronizing dual D-type flip-flop with metastable immune characteristics After determining the T0 and τ of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74ABT5074 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74ABT5074 7 nanoseconds after the clock edge. He simply plugs his number into the following equation: METASTABLE IMMUNE CHARACTERISTICS Philips Semiconductors uses the term ‘metastable immune’ to describe characteristics of some of the products in its family. By running two independent signal generators (see Figure 1) at nearly the same frequency (in this case 10MHz clock and 10.02MHz data) the device-under-test can often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build a waveform. An experiment was run by continuously operating the devices in the region where metastability will occur. SIGNAL GENERATOR D Q MTBF = e(t’/τ)/ TO*fC*fI In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t’ is the time after the clock pulse that the output is sampled (t’ > h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying fI by fC gives an answer of 1015 Hz2. From Figure 2 it is clear that the MTBF is greater than 1010 seconds. Using the above formula the actual MTBF is 1.69 × 1010 seconds or about 535 years. TRIGGER DIGITAL SCOPE SIGNAL GENERATOR CP Q 74ABT5074 INPUT SA00004 Figure 1. Test Setup E6 E13 E8 E10 E12 E14 E15 = fc*fi E12 10,000 YEARS E11 E10 MTBF (SECONDS) 100 YEARS E9 E8 ONE YEAR E7 E6 ONE WEEK E5 4 5 6 7 8 t’ (NANOSECONDS) VCC = 5V, Tamb = 25°C, τ =94ps, To = 1.3x107 sec MTBF = e(t’/τ)/TO*fC*fI Figure 2. Mean Time Between Failures (MTBF) versus t’ December 15, 1994 3 SA00005 Philips Semiconductors Advanced BiCMOS Products Product specification Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCCS AND TEMPERATURES Tamb = –40°C VCC Tamb = 25°C Tamb = 85°C τ T0 τ T0 τ T0 84ps 1.0 × 106 sec 93ps 3.8 × 106 sec 89ps 1.5 × 109 sec 5.0V 84ps 2.7 × sec 94ps 1.3 × sec 106ps 2.2 × 106 sec 4.5V 89ps 1.0 × 109 sec 103ps 2.1 × 107 sec 115ps 4.4 × 106 sec 5.5V 108 107 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA Output in Off or High state –0.5 to +5.5 V Output in Low state 40 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER UNIT DC supply voltage VI Input voltage VIH High-level input voltage MIN MAX 4.5 5.5 V 0 VCC V 2.0 V VIL Low-level Input voltage 0.8 V IOH High-level output current –15 mA IOL Low-level output current 20 mA 0 10 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range December 15, 1994 4 Philips Semiconductors Advanced BiCMOS Products Product specification Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = +25°C TEST CONDITIONS MIN Tamb = –40°C to +85°C TYP MAX –0.9 –1.2 MIN UNIT MAX VIK Input clamp voltage VCC = 4.5V; IIK = –18mA VOH High-level output voltage VCC = 4.5V; IOH = –15mA; VI = VIL or VIH VOL Low-level output voltage VCC = 4.5V; IOL = 20mA; VI = VIL or VIH 0.35 0.5 0.5 V Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI 4.5V ±5.0 ±100 ±100 µA II IOFF current1 2.5 VCC = 5.5V; VO = 2.5V –1.2 2.9 –50 2.5 V V IO Output –75 –180 –180 mA ICC Quiescent supply current VCC = 5.5V; VI = GND or VCC 2 50 –50 50 µA ∆ICC Additional supply current per input pin2 VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.25 500 500 µA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V WAVEFORM Tamb = –40 to +85°C VCC = +5.0V ±0.5V MAX MIN UNIT MIN TYP fmax Maximum clock frequency 1 180 250 MAX tPLH tPHL Propagation delay CPn to Qn or Qn 1 1.0 1.0 2.8 2.4 3.9 3.5 1.0 1.0 4.5 3.7 ns tPLH tPHL Propagation delay SDn, RDn to Qn or Qn 2 1.0 1.0 3.5 3.1 4.6 4.2 1.0 1.0 5.5 4.7 ns tsk(o) Output skew1, 2 CPn to Qn to Qn 4 2.0 ns 150 ns 1.5 NOTES: 1. | tPN actual - tPM actual | for any output compared to any other output where N and M are either LH or HL. 2. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V WAVEFORM Tamb = –40 to +85°C VCC = +5.0V ±0.5V MIN TYP MIN UNIT ts(H) ts(L) Setup time, High or Low Dn to CPn 1 2.5 2.5 1.5 1.5 2.5 2.5 ns th(H) th(L) Hold time, High or Low Dn to CPn 1 0 0 –1.4 –1.4 0 0 ns tw (H) tw (L) CPn pulse width, high or low 1 1.5 2.4 0.6 1.8 1.5 2.9 ns tw (L) SDn or RDn pulse width, low 2 2.0 1.3 2.2 ns Recovery time SDn or RDn to CPn 3 2.4 1.3 2.8 ns trec December 15, 1994 5 Philips Semiconductors Advanced BiCMOS Products Product specification Synchronizing dual D-type flip-flop with metastable immune characteristics ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ AC WAVEFORMS ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ 74ABT5074 VM = 1.5V, VIN = GND to 3.0V The shaded areas indicate when the input is permitted to change for the predictable output performance. Dn VM ts(L) VM VM th(L) ts(H) fMAX VM SDn th(H) VM VM tw(L) tw(H) tw(L) tw(L) VM RDn CPn VM VM tPLH tPLH Qn VM VM tPHL VM tPHL Qn VM Qn VM VM VM tPLH tPHL tPLH VM tPHL Qn VM VM SA00008 SA00009 Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Time, and Clock Width SDn or RDn Waveform 2. Propagation Delay for Set and Reset to Output, Set and Reset Pulse Width Qn, Qn VM tSK(0) tREC CPn VM Qn, Qn VM VM SA00010 SA00011 Waveform 3. Recovery Time for Set or Reset to Output December 15, 1994 Waveform 4. Output Skew 6 Philips Semiconductors Advanced BiCMOS Products Product specification Synchronizing dual D-type flip-flop with metastable immune characteristics 74ABT5074 TEST CIRCUIT AND WAVEFORM VCC NEGATIVE PULSE VIN tw 90% PULSE GENERATOR 10% D.U.T. RT VM VM VOUT CL RL AMP (V) 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM 10% Test Circuit for Totem-Pole Outputs 90% VM 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS FAMILY 74F amplitude rep. rate tw tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00058 December 15, 1994 7