Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) FEATURES MB2823 provide extra data width for wider data/address paths of buses carrying parity. • Output capability: +64mA/–32mA • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops • Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 The MB2823 has two 9-bit wide buffered registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model • Ideal where high speed, light loading, or increased fan–in are required with MOS microprocessors • Live insertation/extraction permitted The registers are fully edge-triggered. The state of each D input, one set–up time before the Low-to-High clock transition is transferred to the corresponding flip–flop’s Q output. DESCRIPTION • Power-up 3-State The MB2823 dual bus interface register is designed to eliminate the extra packages required to buffer existing registers and • Power-up Reset QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 4.6 ns tPLH tPHL Propagation delay nCP to nQx CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance VO = 0V or VCC; 3-state 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 500 nA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 52-Pin Plastic Quad Flat Pack –40°C to +85°C MB2823BB 1418B 52 51 50 49 48 47 46 45 44 43 42 42 41 39 38 37 36 35 34 Vcc 1D2 44 1D1 GND 1D0 1CE 1CP LOGIC SYMBOL 1MR 1OE 1Q0 1Q1 1Q2 Vcc PIN CONFIGURATION 41 40 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1Q3 1 1Q4 2 38 1D4 1Q5 3 37 1D5 GND 4 36 1D6 1Q6 5 1Q7 6 1Q8 7 2Q0 8 2Q1 9 39 1D3 È È È 46 1CP 45 1CE 47 1MR 48 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 35 1D7 MB2823 52-Pin Quad Flat Pack 34 1D8 49 50 51 1 2 3 5 6 7 33 2D0 33 32 31 29 28 27 25 24 23 32 2D1 31 2D2 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 21 2CP 2Q3 11 29 2D3 22 2CE 2Q4 12 28 2D4 20 2MR 2Q5 13 27 2D5 19 2D6 2D7 26 2CE 21 22 23 24 25 2CP 2MR 2OE 2Q8 17 18 19 20 GND 2Q7 Vcc August 24, 1993 2Q6 14 15 16 Vcc 30 GND 2D8 2Q2 10 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 8 2 9 10 11 12 13 15 16 18 853–1705 10616 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) MB2823 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 48, 19 1OE, 2OE Output enable input (active–Low) 44, 42, 41, 39, 38, 37, 36, 35, 34, 33, 32, 31, 29, 28, 27, 25, 24, 23 1D0-1D8 2D0-2D8 Data inputs 49, 50, 51, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18 1Q0-1Q8 2Q0-2Q8 Data outputs 46, 21 1CP, 2CP Clock pulse input (active rising edge) 45, 22 1CE, 2CE Clock enable input (active–Low) 47, 20 1MR, 2MR Master reset input (active–Low) 4, 17, 30, 43 GND Ground (0V) 14, 26, 40, 52 VCC Positive supply voltage LOGIC DIAGRAM nCE nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nCP CP CP nD R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R nD Q R Q nMR nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 LOGIC SYMBOL (IEEE/IEC) 48 47 45 46 44 August 24, 1993 19 EN 20 R 22 G1 21 1C2 EN R G1 1C2 49 33 42 50 32 9 41 51 31 10 39 1 29 11 38 2 28 12 37 3 27 13 36 5 25 16 35 6 24 16 13 4 7 23 18 2D 3 2D 8 nQ7 nQ8 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) MB2823 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE nOE nMR nCE nCP nDx nQ0 – nQ8 L L X X X L Clear L H L ↑ h H Load and read data L H L ↑ l L L H H ↑ X NC H = h = L = l = NC= X = Z = ↑ = ↑ = H X X X X Z High voltage level High voltage level one set-up time prior to the Low-to-High clock transition Low voltage level Low voltage level one set-up time prior to the Low-to-High clock transition No change Don’t care High impedance “off” state Low to High clock transition Not a Low-to-High clock transition Hold High impedance ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC IIK CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT MIN MAX 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range August 24, 1993 2.0 4 V Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) MB2823 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH Input clamp voltage High–level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA TYP MAX –0.9 –1.2 MIN UNIT MAX –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low–level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IOL = 1mA; VI = GND or VCC 0.13 0.55 0.55 V II Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC, VOE = Don’t care ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA –70 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 120 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 45 68 68 mA VCC = 5.5V; Outputs 3–State; VI = GND or VCC 120 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA IOFF IPU/PD IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a transistion time of up to 100µsec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM MIN TYP MAX MIN UNIT MAX fMAX Maximum clock frequency 1 140 190 tPLH tPHL Propagation delay nCP to nQx 1 2.0 2.5 3.8 4.2 5.1 5.6 2.0 2.5 5.7 6.1 ns tPHL Propagation delay nMR to nQx 2 3.2 5.3 6.6 3.2 7.5 ns tPZH tPZL Output enable time to High and Low level 4 5 1.3 2.2 3.2 4.0 4.4 5.3 1.3 2.2 5.1 5.9 ns tPHZ tPLZ Output disable time from High and Low level 4 5 1.3 1.5 3.3 3.1 4.6 4.4 1.3 1.5 5.1 5.9 ns August 24, 1993 5 140 MHz Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) MB2823 AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER +25oC Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = VCC = +5.0V WAVEFORM UNIT MIN TYP MIN 3 2.0 1.5 0.6 0.2 2.0 1.5 Hold time, High or Low nDx to nCP 3 1.5 1.5 –0.2 –0.5 tw(H) tw(L) nCP pulse width High or Low 1 3.0 3.5 1.0 2.3 3.0 3.5 ns ts(H) ts(L) Setup time, High or Low nCE to nCP 3 1.5 2.0 –0.2 1.0 1.5 2.0 ns th(H) th(L) Hold time, High or Low nCE to nCP 3 1.5 1.5 –1.2 0.3 1.5 1.5 ns tw(L) nMR pulse width, Low 2 3.0 1.6 3.0 ns trec Recovery time nMR to nCP 2 2.5 0.6 2.5 ns ts(H) ts(L) Setup time, High or Low nDx to nCP th(H) th(L) ns 1.5 1.5 AC WAVEFORMS 1/fMAX nCP nMR VM V M VM VM tw(H) tPHL VM tw(L) tw(L) tREC nCP tPLH VM tPHL nQx VM VM ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ nQx ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency nDx, nCE VM Waveform 2. Master Reset Pulse WIdth, Master Reset to Output Delay and Master Reset to Clock Recovery Time VM ts(H) VM VM th(H) VM ts(L) th(L) nCP VM VM Waveform 3. Data Setup and Hold Times nOE VM tPZH nQx nOE VM tPHZ VM VM VM tPZL VOH –0.3V nQx tPLZ VM VOL +0.3V 0V Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. August 24, 1993 6 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) MB2823 TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN VOUT PULSE GENERATOR tW 90% VM NEGATIVE PULSE 10% 0V tTHL (tF) CL tTLH (tR) tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. MB RT = Termination resistance should be equal to ZOUT of pulse generators. August 24, 1993 AMP (V) VM 10% RL D.U.T RT 90% 7 Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) MB2823 tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nCp to nQx 8 Adjustment of tPLH for Load Capacitance and # of Outputs Switching nCp to nQx 5 7 4 MAX 6 18 switching 9 switching 3 4.5VCC 4 5.5VCC 3 1 switching Offset in ns ns 5 2 1 0 MIN 2 –1 1 –2 –40 –15 10 35 60 85 0 20 40 60 80 °C 120 140 160 180 200 pF Adjustment of tPHL for Load Capacitance and # of Outputs Switching nCp to nQx tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nCp to nQx 8 100 5 7 4 18 switching 9 switching MAX 3 Offset in ns 6 5 ns 4.5VCC 4 5.5VCC 1 switching 2 1 3 0 MIN 2 –1 1 –2 –40 –15 10 35 60 85 0 20 40 60 80 °C 8 100 120 140 160 180 200 pF tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nMRx to nQx Adjustment of tPHL for Load Capacitance and # of Outputs Switching nMRx to nQx 5 MAX 4 6 4.5VCC 3 5 5.5VCC ns Offset in ns 7 4 3 18 switching 9 switching 1 switching 2 1 0 MIN 2 –1 1 –40 –2 –15 10 35 60 85 0 °C August 24, 1993 20 40 60 80 100 pF 8 120 140 160 180 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) MB2823 tPZH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 7 Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOE to nQx 5 6 4 MAX 4 ns 18 switching 9 switching 3 1 switching Offset in ns 5 4.5VCC 3 5.5VCC 2 1 2 0 MIN 1 –1 0 –2 –40 –15 10 35 60 85 0 20 40 60 80 °C 120 140 160 180 200 pF Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOE to nQx tPZL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 7 100 5 6 4 MAX 3 Offset in ns 5 4 4.5VCC ns 18 switching 9 switching 3 5.5VCC 1 switching 2 1 2 0 MIN 1 –1 0 –2 –40 –15 10 35 60 85 0 20 40 60 80 °C 8 tPHZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOEx to nQx 140 160 180 200 Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOEx to nQx 7 18 switching 9 switching 1 switching 6 5 MAX 6 Offset in ns 4 ns 5 4.5VCC 4 5.5VCC 3 3 2 1 0 –1 MIN 2 –2 1 –3 –15 10 35 60 0 85 °C August 24, 1993 120 pF 7 –40 100 20 40 60 80 100 pF 9 120 140 160 180 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) MB2823 tPLZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx 8 Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOE to nQx 6 7 18 switching 9 switching 1 switching 5 MAX 4 6 3 Offset in ns ns 5 4 4.5VCC 5.5VCC MIN 3 2 2 1 0 –1 1 –2 –40 –15 10 35 60 85 0 20 40 60 80 °C 100 120 140 160 180 200 pF Adjustment of tTLH for Load Capacitance and # of Outputs Switching nOE to nQx tTLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching 8 4 7 18 switching 9 switching 1 switching 6 3 Offset in ns ns 5 4.5VCC 5.5VCC 2 4 3 2 1 1 0 –1 0 –2 –40 –15 10 35 60 0 85 20 40 60 80 °C 100 120 140 160 180 200 pF Adjustment of tTHL for Load Capacitance and # of Outputs Switching tTHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching 4 5 18 switching 4 3 Offset in ns 4.5VCC ns 9 switching 3 2 5.5VCC 1 switching 2 1 0 1 –1 0 –40 –2 –15 10 35 60 0 85 °C August 24, 1993 20 40 60 80 100 pF 10 120 140 160 180 200 Philips Semiconductors Advanced BiCMOS Products Product specification Dual 9-bit D-type flip-flop with reset and enable (3-State) MB2823 VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0V to 3V VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0V to 3V 5 6 5 125oC 25oC –55oC 4 125oC 25oC –55oC 3 3 VOLTS VOLTS 4 125oC 2 1 2 1 25oC 0 –55oC –1 125oC 25oC –55oC –2 0 –3 0 20 40 60 80 100 120 140 0 160 180 200 pF August 24, 1993 20 40 60 80 100 120 pF 11 140 160 180 200