TI SMJ416400

SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
D
D
D
D
D
D
D
D
D
D
Organization . . . 4 194 304 × 4
Single 5-V Power Supply (10% Tolerance)
Performance Ranges:
’416400 - 70
’416400 - 80
’416400 -10
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
tRAC
tCAC
tAA
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
100 ns
25 ns
45 ns
180 ns
Enhanced Page-Mode Operation for Faster
Memory Access
CAS-Before-RAS (CBR) Refresh
Long Refresh Period
4 096 Cycles Refresh in 32 ms
3-State Unlatched Output
Low Power Dissipation
All Inputs, Outputs, and Clocks are
TTL-Compatible
Operating Free-Air Temperature Range
– 55°C to 125°C
description
The SMJ416400 series is a set of high-speed
16 777 216-bit
dynamic
random-access
memories (DRAMs), organized as 4 194 304
words of four bits each. The series employs
technology for high performance, reliability, and
low power.
These devices feature maximum RAS access
times of 70 ns, 80 ns, and 100 ns. All inputs,
outputs, and clocks are compatible with series 54
TTL. All addresses and data-in lines are latched
on-chip to simplify system design. Data out is
unlatched to allow greater system flexibility.
The SMJ416400 is offered in 450-mil 24/28-pin
surface-mount small-outline leadless chip carrier
(FNC suffix), 28-lead flatpack (HKB suffix), and
24-lead ZIP (SV suffix) packages. The packages
are characterized for operation from –55°C to
125°C.
SV PACKAGE
(TOP VIEW )
FNC PACKAGE
(TOP VIEW )
VCC
DQ1
DQ2
W
RAS
A11
A10
A0
A1
A2
A3
VCC
1
28
2
27
3
26
4
25
5
24
6
23
9
20
10
19
11
18
12
17
13
16
14
15
VSS
DQ4
DQ3
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
A9
CAS
DQ3
VCC
DQ1
RAS
A10
A1
A3
VSS
A5
A7
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
OE
DQ2
VSS
DQ4
W
A11
A0
A2
VCC
A4
A6
A8
HKB PACKAGE
( TOP VIEW )
VCC
DQ1
DQ2
W
RAS
A11
NC
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ4
DQ3
CAS
OE
A9
NC
NC
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
A0 – A11
CAS
DQ1 – DQ4
NC
OE
RAS
W
VCC
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
logic symbol†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS
CAS
W
OE
DQ1
DQ2
DQ3
DQ4
RAM 4 096K × 4
10
11
12
13
16
17
18
19
20
20D12 / 21D0
A
23
9
6
0
4 194 303
20D21 / 21D9
/ 21D10
/ 21D11
C21[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C20[COLUMN]
G24
5
25
&
4
24
23C22
23,20D
G25
2
24,25EN
A,22D
26
3
26
27
A,Z26
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FNC and HKB packages.
functional block diagram
RAS
CAS
W
OE
Timing and Control
A0
A1
8
ColumnAddress
Buffers‡
Column Decode
Sense Amplifiers
2
256K Array
R 256K Array
256K Array o 256K Array
w
A11
RowAddress
Buffers
32
D
e
c
o
d
e
32
11
256K Array
32
32
I/O
Buffers
4 of 32
Selection
256K Array
2
11
‡ Column address 10 and column address 11 are not used.
2
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DataIn
Reg.
DataOut
Reg.
4
4
DQ1 – DQ4
SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address and strobing random
column addresses onto the chip. The time required to set up and strobe row addresses for the same page is
eliminated. The maximum number of columns that can be addressed is determined by tRAS, the maximum RAS
low width.
The column-address buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output-enable. This feature allows the SMJ416400 to operate at a higher data
bandwidth than conventional page-mode parts because retrieval begins as soon as the column address is valid,
rather than when CAS goes low. The performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after tCAC maximum (access time from CAS
low) if tAA maximum (access time from column address) and tOEA have been satisfied. When the column
address for the next cycle is valid at the time CAS goes high, access time is determined by the later occurrence
of tCPA or tCAC.
address (A0 – A11)
Twenty-two address bits are required to decode one of 4 194 304 storage-cell locations. Twelve row-address
bits are set on inputs A0 through A11 and latched onto the chip by the row-address strobe, RAS. Ten
column-address bits are set on A0 through A9 and latched onto the chip by the column-address strobe, CAS.
Row address A11 is required during a normal access and during RAS-only refresh as the device requires
4 096 refresh cycles. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip-enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select,
activating the output buffer, as well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable ( W ) input. A logic high on W selects the read mode
and a logic low selects the write mode. W can be driven from standard TTL circuits without a pullup resistor.
The data input is disabled when the read mode is selected. When W goes low prior to CAS (early write), data
out remains in the high-impedance state for the entire cycle permitting a write operation that is independent of
the state of OE. This permits an early-write operation to be completed with OE grounded.
data in/data out (DQ1 – DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-chip data latch. In the early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed write or read-modify-write
cycle, CAS is already low; data is strobed in by W with setup and hold times referenced to this signal.
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
series 54 TTL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle,
the output becomes valid at the latest occurrence of tRAC, tAA, tCAC, or tCPA and remains valid while CAS is low.
CAS going high returns it to the high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change, but retains the state just read.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. Both RAS and CAS must be brought low for the output buffers to go into the low-impedance state. Once
in the low-impedance state, the output buffers remain in this state until either OE or CAS is brought high.
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3
SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
refresh
A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing
each of the 4 096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at a high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed by holding CAS at VIL after a read operation and by cycling RAS after
the specified precharge period, similar to a RAS-only refresh cycle except with CAS held low. Valid data is
maintained at the output throughout the hidden-refresh cycle. An internal-refresh address provides the refresh
address during hidden refresh.
CAS-before-RAS (CBR) refresh
CBR refresh is used by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS
falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. For this
mode of refresh, the external addresses are ignored and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh
( RAS-only or CBR ) cycle.
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
VIH
Supply voltage
4.5
5
5.5
UNIT
V
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
–1
0.8
V
°C
TA
Operating free-air temperature
– 55
125
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
4
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SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
IOH = – 5 mA
IOL = 4.2 mA
’416400 - 80
MAX
MIN
’416400 - 10
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
± 10
± 10
± 10
µA
80
70
60
mA
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and CAS high
2
2
2
mA
VIH = VCC – 0.05 V (CMOS),
After one memory cycle,
RAS and CAS high
1
1
1
mA
II
Input current (leakage)
IO
Output current (leakage)
VO = 0 V to VCC, CAS high
ICC1
Read- or write-cycle current
(see Note 3)
VCC = 5.5 V,
Standby current
MIN
2.4
VI = 0 V to 6.5 V,
All others = 0 V to VCC
ICC2
’416400 - 70
Minimum cycle
ICC3
Average refresh current
(RAS only or CBR)†
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
80
70
60
mA
ICC4
Average page current
(see Note 4)†
RAS low,
65
60
55
mA
ICC7
Standby current
output enable†
RAS = VIH,
CAS = VIL,
Data out = enabled
5
5
5
mA
CAS cycling
† Minimum cycle, VCC = 5.5 V
NOTES: 3. Measured with a maximum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A11 ‡
9
pF
Ci(RC)
8
pF
Ci(OE)
Input capacitance, RAS and CAS ‡
Input capacitance, OE ‡
8
pF
Ci(W)
Input capacitance, W ‡
8
pF
Co
Output capacitance
14
pF
‡ Input capacitance for ZIP (SV suffix) package is 12 pF.
NOTE 5: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are open.
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5
SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 6)
’416400 - 70
PARAMETER
MIN
MAX
’416400 - 80
MIN
MAX
’416400 - 10
MIN
MAX
UNIT
tAA
tCAC
Access time from column-address
35
40
45
ns
Access time from CAS low
18
20
25
ns
tCPA
tRAC
Access time from column precharge
40
45
50
ns
Access time from RAS low
70
80
100
ns
tOEA
tOFF
Access time from OE low
18
20
25
ns
25
ns
Output disable time after CAS high (see Note 7)
0
18
0
20
0
tOEZ
Output disable time after OE high (see Note 7)
0
18
0
20
0
25
ns
NOTES: 6. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data
state prior to the specified access times as the outputs are driven when CAS goes low.
7. tOFF and tOEZ are specified when the outputs are no longer driven. The outputs are disabled by bringing either OE or CAS high.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’416400 - 70
’416400 - 80
’416400 - 10
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tRC
tRWC
Cycle time, random read or write (see Note 8)
130
150
180
ns
Cycle time, read-write (see Note 8)
181
205
245
ns
tPC
tPRWC
Cycle time, page mode read or write (see Notes 8 and 9)
45
50
55
ns
Cycle time, page mode read-write (see Note 8)
96
105
120
ns
tRASP
tRAS
Pulse duration, RAS low, page mode (see Note 10)
70 100 000
80 100 000
100 100 000
ns
Pulse duration, RAS low, nonpage mode (see Note 10)
70
10 000
80
10 000
100
10 000
ns
tCAS
tCP
Pulse duration, CAS low (see Note 11)
18
10 000
20
10 000
25
10 000
ns
Pulse duration, CAS high
10
10
10
ns
tRP
tWP
Pulse duration, RAS high (precharge)
50
60
70
ns
Pulse duration, W low
10
10
10
ns
tASC
tASR
Setup time, column address before CAS going low
0
0
0
ns
Setup time, row address before RAS going low
0
0
0
ns
tDS
tRCS
Setup time, data (see Note 12)
0
0
0
ns
Setup time, W high before CAS going low
0
0
0
ns
tCWL
tRWL
Setup time, W low before CAS going high
18
20
25
ns
Setup time, W low before RAS going high
18
20
25
ns
Setup time, W low before CAS going low
(early-write operation only)
0
0
0
ns
tWCS
tWRP
tCAH
Setup time, W high before RAS going low (CBR refresh only)
10
10
10
ns
Hold time, column address after CAS low
15
15
15
ns
tDH
tRAH
Hold time, data (see Note 12)
15
15
15
ns
Hold time, row address after RAS low
10
10
10
ns
tRCH
tRRH
Hold time, W high after CAS high (see Note 13)
0
0
0
ns
Hold time, W high after RAS high (see Note 13)
0
0
5
ns
NOTES: 8.
9.
10.
11.
12.
13.
6
All cycle times assume tT = 5 ns, referenced to VIH(min) and VIL(max).
To assure tPC min, tASC should be ≥ tCP .
In a read-write cycle, tRWD and tRWL must be observed.
In a read-write cycle, tCWD and tCWL must be observed.
Referenced to the later of CAS or W in write operations
Either tRRH or tRCH must be satisfied for a read cycle.
POST OFFICE BOX 1443
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SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’416400 - 70
MIN
MAX
’416400 - 80
MIN
MAX
’416400 - 10
MIN
MAX
UNIT
tWCH
tWRH
Hold time, W low after CAS low (early-write operation only)
15
15
15
ns
Hold time, W high after RAS low (CBR refresh only)
10
10
10
ns
tOEH
tROH
Hold time, OE command
18
20
25
ns
Hold time, RAS referenced to OE
10
10
10
ns
tRHCP
Hold time, RAS low after CAS precharge
40
45
50
ns
tAWD
Delay time, column address to W going low
(read-write operation only)
63
70
80
ns
tCHR
tCRP
Delay time, RAS low to CAS going high (CBR refresh only)
10
10
20
ns
Delay time, CAS high to RAS going low
5
5
5
ns
tCSH
tCSR
Delay time, RAS low to CAS going high
70
80
100
ns
5
5
10
ns
tCWD
tOED
Delay time, CAS low to W going low (read-write operation only)
46
50
60
ns
Delay time, OE to data
18
20
25
ns
tRAD
tRAL
Delay time, RAS low to column address (see Note 14)
15
Delay time, column address to RAS going high
35
40
45
ns
tCAL
tRCD
Delay time, column address to CAS going high
35
40
45
ns
Delay time, RAS low to CAS low (see Note 14)
20
tRPC
tRSH
Delay time, RAS high to CAS going low
0
Delay time, CAS low to RAS going high
18
tRWD
Delay time, RAS low to W going low (read-write operation only)
98
tCPW
Delay time, W going low after CAS precharge
(read-write operation only)
63
70
Delay time, CAS low to RAS going low (CBR refresh only)
35
52
15
20
0
40
60
15
20
55
75
ns
ns
0
ns
20
25
ns
110
135
ns
80
ns
tREF
Refresh time interval
32
32
32
ms
†
†
†
†
†
†
tT
Transition time
3
30
3
30
3
30
ns
† Transition times (rise and fall) for RAS and CAS are to be a minimum of 3 ns and a maximum of 30 ns. This is assured by design but not tested.
NOTE 14: The maximum value is specified only to assure access time.
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7
SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
1.31 V
5V
R1 = 828 Ω
RL = 218 Ω
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
R2 = 295 Ω
(b) ALTERNATE LOAD CIRCUIT
VIH / VOH MIN
VIL / VOL MAX
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and fixture capacitance.
B. The ac timing parameters are specified with reference to the minimum valid high-level voltage and the maximum valid
low-level voltage for each signal. This corresponds to 2.4 V and 0.8 V for inputs; 2.4 V and 0.4 V for outputs with the
given load circuit.
Figure 1. Load Circuits and Voltage Waveforms
8
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SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCAS
tASR
CAS
tCP
tRAD
tASC
tRAH
tCAL
tRAL
A0 – A11
Row
Column
Don’t Care
tRCS
tRRH
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tOFF
tAA
DQ1 – DQ4
Hi-Z
Valid Data Out
See Note A
tRAC
tOEZ
tOEA
tROH
OE
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
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9
SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
tCAL
RAS
tRP
tT
tRSH
tRCD
tCAS
tCRP
tCSH
CAS
tASR
tCP
tASC
tRAL
tRAH
A0 – A11
tCAH
Row
Don’t Care
Column
tCWL
tRWL
tRAD
W
tWCH
tWCS
Don’t Care
Don’t Care
tWP
tDH
tDS
DQ1 – DQ4
Valid Data
Don’t Care
Don’t Care
OE
Figure 3. Early-Write-Cycle Timing
10
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SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCAS
tCRP
tCSH
tASR
tASC
CAS
tCP
tRAL
tCAL
tRAH
tCAH
Row
A0 – A11
Don’t Care
Column
tRAD
tCWL
tRWL
W
Don’t Care
Don’t Care
tWP
tDS
tDH
DQ1 – DQ4
Don’t Care
Don’t Care
Valid Data
tOED
tOEH
OE
Don’t Care
Don’t Care
Figure 4. Write-Cycle Timing
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SMJ416400
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DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tT
tRP
tRCD
tCRP
tCAS
CAS
tASR
tCP
tRAH
tCAH
tT
tRAD
tASC
A0–A11
Row
Column
Don’t Care
tRCS
tCWL
tRWL
tRWD
tWP
tAWD
W
Don’t Care
tCWD
tDS
tCAC
tAA
DQ1–DQ4
See Note A
tDH
Data
Out
Data
In
Don’t Care
tRAC
tOEZ
tOEH
tOED
tOEA
OE
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-Cycle Timing
12
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SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCRP
tPC
tRCD
tCP
tCSH
tRSH
tCAS
CAS
tRAH
tCAH
tCAL
tASR
tASC
A0 – 11
Row
tRAL
Don’t Care
Column
Column
tRRH
tAA†
tRCS
tRCH
See NoteA
W
tCAC†
tRAD
tCPA†
tCAC
tAA
tOFF
tRAC
DQ1 – DQ4
Valid
Out
See Note A
Valid
Out
tOEZ
tOEZ
tOEA
tOEA
OE
Don’t Care
† Access time is tCPA-, tCAC- or tAA-dependent.
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
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DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tPC
tRCD
tCRP
tRSH
tCAS
tCAL
tASC
CAS
tCP
tRAH
tCAH
tASR
A0 – A11
tRAL
Row
Column
Don’t Care
Column
tRAD
tCWL
tCWL
tRWL
tWP
W
Don’t Care
Don’t Care
Don’t Care
tDH
tDS
See Note A
tDH
See Note A
tOEH
tDS
DQ1 – DQ4
Valid
In
Valid Data In
Don’t Care
tOEH
tOED
Don’t Care
OE
Don’t Care
NOTES: A. Referenced to CAS or W, whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with a write cycle as long as read and read-write timing specifications are not
violated.
Figure 7. Enhanced-Page-Mode Write-Cycle Timing
14
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SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRHCP
tCSH
tRSH
tPRWC
tCRP
tRCD
tCP
CAS
tCAS
tASR
tASC
tRAD
A0 – A11
tCAH
Row
Column
Column
tRAH
Don’t Care
tCWL
tCWD
tAWD
tCPW
tRWD
tRWL
tWP
W
tRCS
tCPA
tAA
tOEH
tDH
tRAC
tDS
Valid Out
(see Note A)
tCAC
Valid
In
DQ1–DQ4
Valid
In
Valid Out
tOED
tOEZ
tOEH
tOEA
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 8. Enhanced-Page-Mode Read-Write-Cycle Timing
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SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
Don’t Care
CAS
tRPC
tRAH
tASR
Don’t Care
A0 – A11
Row
W
Don’t Care
DQ1 – DQ4
Don’t Care
OE
Don’t Care
Don’t Care
Figure 9. RAS-Only Refresh Timing
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
tWRH
W
A0 – A11
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 10. Automatic-CBR-Refresh-Cycle Timing
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DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
A0 – A11
Row
Don’t Care
Col
tRRH
tWRH
tRCS
tWRH
tWRP
tWRH
tWRP
tWRP
W
tCAC
tAA
tOFF
tRAC
DQ1 – DQ4
Valid Data Out
tOEZ
tOEA
OE
Figure 11. Hidden-Refresh-Cycle (Read) Timing
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SMJ416400
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SGMS042E – MARCH 1992 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Row
A0 – A11
Don’t Care
Col
tRRH
tWRH
tWCS
tWRP
tWP
W
tWCH
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 12. Hidden-Refresh-Cycle ( Write) Timing
18
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SGMS042E – MARCH 1992 – REVISED MARCH 1996
MECHANICAL DATA
FNC (R-CDCC-N24/28)
LEADLESS CERAMIC CHIP CARRIER
0.460 (11,68)
0.440 (11,18)
0.785 (19,94)
0.765 (19,43)
0.035 (0,89) MIN
0.125 (3,18)
0.105 (2,67)
12
13
0.028 (0,71)
0.022 (0,56)
0.008 (0,20) RAD TYP
0.050 (1,27)
1
24
0.125 (3,18)
0.080 (2,03)
0.105 (2,67)
0.070 (1,78)
4040142 / B 10/94
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
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SMJ416400
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DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
MECHANICAL DATA
SV (R-CZIP-T**)
CERAMIC ZIG-ZAG PACKAGE
20 PIN SHOWN
0.130 (3,30)
0.100 (2,54)
A
B
Seating Plane
0.200 (5,08)
0.125 (3,18)
0.050 (1,27)
0.015 (0,38)
0.060 (1,52)
0.040 (1,02)
0.015 (0,38)
0.008 (0,20)
0.100 (2,54)
1
0.115 (2,92)
0.085 (2,16)
19
PINS **
20
24
28
A MAX
1.065
(27,05)
1.265
(32,13)
1.465
(37,21)
A MIN
1.035
(26,29)
1.235
(31,37)
1.435
(36,45)
B MAX
0.380
(9,65)
0.465
(11,81)
0.465
(11,81)
B MIN
0.355
(9,02)
0.440
(11,18)
0.440
(11,18)
C MAX
0.910
(23,11)
1.110
(28,19)
1.310
(33,27)
C MIN
0.890
(22,61)
1.090
(27,69)
1.290
(32,77)
DIM
C
0.023 (0,58)
0.015 (0,38)
2
4
6
8
10
12
14
16
18
20
0.375 (9,53)
0.355 (9,02)
0.070 (1,78)
0.040 (1,02)
4040002 / C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
20
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SMJ416400
4194304 BY 4-BIT
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SGMS042E – MARCH 1992 – REVISED MARCH 1996
MECHANICAL DATA
HKB (R-CDFP-F28)
CERAMIC DUAL FLATPACK
0.045 (1,14)
0.026 (0,66)
Lid
0.009 (0,23)
0.004 (0,10)
0.130 (3,32)
0.090 (2,29)
0.400 (10,16)
0.350 (8,89)
0.030 (0,76) MIN
2 Places
0.010 (0,25) MIN
4 Places
0.370 (9,40)
0.250 (6,35)
0.460 (11,68)
0.440 (11,18)
14
15
0.050 (1,27)
0.790 (20,01)
0.760 (19,30)
0.021 (0,53)
0.015 (0,38)
1
28
4040120 / C 03/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
POST OFFICE BOX 1443
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21
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