TJA1041A High-speed CAN transceiver Rev. 04 — 29 July 2008 Product data sheet 1. General description The TJA1041A provides an advanced interface between the protocol controller and the physical bus in a Controller Area Network (CAN) node. The TJA1041A is primarily intended for automotive high-speed CAN applications (up to 1 Mbit/s). The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. The TJA1041A is fully compatible to the ISO 11898 standard, and offers excellent ElectroMagnetic Compatibility (EMC) performance, very low power consumption, and passive behavior when supply voltage is off. The advanced features include: • Low-power management, supporting local and remote wake-up with wake-up source recognition and the capability to control the power supply in the rest of the node • Several protection and diagnosis functions including short circuits of the bus lines and first battery connection • Automatic adaptation of the I/O-levels, in line with the supply voltage of the controller 2. Features 2.1 Optimized for in-vehicle high-speed communication n n n n n n n n n Fully compatible with the ISO 11898 standard Communication speed up to 1 Mbit/s Very low ElectroMagnetic Emission (EME) Differential receiver with wide common-mode range, offering high ElectroMagnetic Immunity (EMI) Passive behavior when supply voltage is off Automatic I/O-level adaptation to the host controller supply voltage Recessive bus DC voltage stabilization for further improvement of EME behavior Listen-only mode for node diagnosis and failure containment Allows implementation of large networks (more than 110 nodes) 2.2 Low-power management n Very low-current in Standby and Sleep mode, with local and remote wake-up n Capability to power down the entire node, still allowing local and remote wake-up n Wake-up source recognition 2.3 Protection and diagnosis (detection and signalling) n TXD dominant clamping handler with diagnosis TJA1041A NXP Semiconductors High-speed CAN transceiver n n n n n n n n n RXD recessive clamping handler with diagnosis TXD-to-RXD short circuit handler with diagnosis Overtemperature protection with diagnosis Undervoltage detection on pins VCC, VI/O and VBAT Automotive environment transient protected bus pins and pin VBAT Short circuit proof bus pins and pin SPLIT (to battery and to ground) Bus line short circuit diagnosis Bus dominant clamping diagnosis Cold start diagnosis (first battery connection) 3. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min VCC DC voltage on pin VCC operating range VI/O DC voltage on pin VI/O IBAT VBAT input current Max Unit 4.75 - 5.25 V operating range 2.8 - 5.25 V normal or pwon/listen-only mode 15 30 40 µA standby mode; VCC > 4.75 V; VI/O = 2.8 V; VINH = VWAKE = VBAT = 12 V 10 20 30 µA sleep mode; VINH = VCC = VI/O = 0 V; VWAKE = VBAT = 12 V 10 20 30 µA VCANH DC voltage on pin CANH 0 V < VCC < 5.25 V; no time limit −27 - +40 V VCANL DC voltage on pin CANL 0 V < VCC < 5.25 V; no time limit −27 - +40 V VSPLIT DC voltage on pin SPLIT 0 V < VCC < 5.25 V; no time limit −27 - +40 V Vesd electrostatic discharge voltage Human Body Model (HBM) tPD(TXD-RXD) propagation delay TXD to RXD Tvj [1] [1] pins CANH, CANL and SPLIT −6 - +6 kV pins TXD, RXD, VI/O and STB −3 - +3 kV all other pins −4 - +4 kV 40 - 255 ns −40 - +150 °C VSTB = 0 V virtual junction temperature Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor (6 kV level with pin GND connected to ground). TJA1041A_4 Product data sheet Typ © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 2 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 4. Ordering information Table 2. Ordering information Type number Package Name Description Version TJA1041AT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 TJA1041AU - bare die; 1920 × 3190 × 380 µm - 5. Block diagram VI/O VCC 3 5 VBAT 10 TJA1041A TXD 7 1 TIME-OUT EN TEMPERATURE PROTECTION LEVEL ADAPTOR 6 13 STB INH DRIVER 14 12 CANH CANL VBAT WAKE 9 VCC WAKE COMPARATOR MODE CONTROL + FAILURE DETECTOR + WAKE-UP DETECTOR VI/O ERR 8 RXD RECESSIVE DETECTION VI/O SPLIT 11 SPLIT VBAT LOW POWER RECEIVER VCC RXD 4 NORMAL RECEIVER 2 mnb115 GND Fig 1. Block diagram TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 3 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 6. Pinning information 6.1 Pinning TXD 1 14 STB GND 2 13 CANH VCC 3 12 CANL RXD 4 VI/O 5 EN 6 INH 7 TJA1041A 11 SPLIT 10 VBAT 9 WAKE 8 ERR 001aag910 Fig 2. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin Description TXD 1 transmit data input GND 2 ground VCC 3 transceiver supply voltage input RXD 4 receive data output; reads out data from the bus lines VI/O 5 I/O-level adapter voltage input EN 6 enable control input INH 7 inhibit output for switching external voltage regulators ERR 8 error and power-on indication output (active LOW) WAKE 9 local wake-up input VBAT 10 battery voltage input SPLIT 11 common-mode stabilization output CANL 12 LOW-level CAN bus line CANH 13 HIGH-level CAN bus line STB 14 standby control input (active LOW) 7. Functional description The primary function of a CAN transceiver is to provide the CAN physical layer as described in the ISO 11898 standard. In the TJA1041A this primary function is complemented with a number of operating modes, fail-safe features and diagnosis features, which offer enhanced system reliability and advanced power management functionality. TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 4 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 7.1 Operating modes The TJA1041A can be operated in five modes, each with specific features. Control pins STB and EN select the operating mode. Changing between modes also gives access to a number of diagnostics flags, available via pin ERR. The following sections describe the five operating modes. Table 4 shows the conditions for selecting these modes. Figure 3 illustrates the mode transitions when VCC, VI/O and VBAT are present. Table 4. Operating mode selection Control pins Internal flags STB EN UVNOM UVBAT pwon; wake-up X X set X cleared set L L H H L H L H cleared cleared cleared cleared cleared cleared cleared cleared Operating mode Pin INH X[1] Sleep mode[2] floating one or both set Standby mode H both cleared no change from Sleep mode floating Standby mode from any other mode H one or both set Standby mode H both cleared no change from Sleep mode floating Standby mode from any other mode H one or both set Standby mode H both cleared no change from Sleep mode floating Go-to-sleep command mode from any other mode[3] H[3] X Pwon/Listen-only mode H X mode[4] H [1] Setting the pwon flag or the wake-up flag will clear the UVNOM flag. [2] The transceiver directly enters Sleep mode and pin INH is set floating when the UVNOM flag is set (so after the undervoltage detection time on either VCC or VI/O has elapsed before that voltage level has recovered). [3] When Go-to-sleep command mode is selected for longer than the minimum hold time of the go-to-sleep command, the transceiver will enter Sleep mode and pin INH is set floating. [4] On entering Normal mode the pwon flag and the wake-up flag will be cleared. TJA1041A_4 Product data sheet Normal © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 5 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver STB = H and EN = H STB = H and EN = L PWON/LISTENONLY MODE STB = H and EN = H STB = H and EN = L STB = H and EN = L NORMAL MODE STB = H and EN = H STB = L and (EN = L or flag set) STB = L and EN = H and flags cleared STB = L and EN = L GO-TO-SLEEP COMMAND MODE STB = L and EN = H and flags cleared STANDBY MODE STB = L and EN = H STB = L and (EN = L or flag set) STB = H and EN = L and UVNOM cleared flags cleared and t > th(min) STB = L and flag set SLEEP MODE STB = H and EN = H and UVNOM cleared LEGEND: = H, = L flag set flags cleared Fig 3. logical state of pin setting pwon and/or wake-up flag pwon and wake-up flag both cleared mgu983 Mode transitions when VCC, VI/O and VBAT are present 7.1.1 Normal mode Normal mode is the mode for normal bidirectional CAN communication. The receiver will convert the differential analog bus signal on pins CANH and CANL into digital data, available for output to pin RXD. The transmitter will convert digital data on pin TXD into a differential analog signal, available for output to the bus pins. The bus pins are biased at 0.5VCC (via Ri(cm)). Pin INH is active, so voltage regulators controlled by pin INH (see Figure 4) will be active too. 7.1.2 Pwon/Listen-only mode In Pwon/Listen-only mode the transmitter of the transceiver is disabled, effectively providing a transceiver listen-only behavior. The receiver will still convert the analog bus signal on pins CANH and CANL into digital data, available for output to pin RXD. As in Normal mode the bus pins are biased at 0.5VCC, and pin INH remains active. TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 6 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 7.1.3 Standby mode The Standby mode is the first-level power saving mode of the transceiver, offering reduced current consumption. In Standby mode the transceiver is not able to transmit or receive data and the low-power receiver is activated to monitor bus activity. The bus pins are biased at ground level (via Ri(cm)). Pin INH is still active, so voltage regulators controlled by this pin INH will be active too. Pins RXD and ERR will reflect any wake-up requests (provided that VI/O and VCC are present). 7.1.4 Go-to-sleep command mode The Go-to-sleep command mode is the controlled route for entering Sleep mode. In Go-to-sleep command mode the transceiver behaves as if in Standby mode, plus a Go-to-sleep command is issued to the transceiver. After remaining in Go-to-sleep command mode for the minimum hold time (th(min)), the transceiver will enter Sleep mode. The transceiver will not enter the Sleep mode if the state of pins STB or EN is changed or the UVBAT, pwon or wake-up flag is set before th(min) has expired. 7.1.5 Sleep mode The Sleep mode is the second-level power saving mode of the transceiver. Sleep mode is entered via the Go-to-sleep command mode, and also when the undervoltage detection time on either VCC or VI/O elapses before that voltage level has recovered. In Sleep mode the transceiver still behaves as described for Standby mode, but now pin INH is set floating. Voltage regulators controlled by pin INH will be switched off, and the current into pin VBAT is reduced to a minimum. Waking up a node from Sleep mode is possible via the wake-up flag and (as long as the UVNOM flag is not set) via pin STB. 7.2 Internal flags The TJA1041A makes use of seven internal flags for its fail-safe fallback mode control and system diagnosis support. Table 4 shows the relation between flags and operating modes of the transceiver. Five of the internal flags can be made available to the controller via pin ERR. Table 5 shows the details on how to access these flags. The following sections describe the seven internal flags. Table 5. Accessing internal flags via pin ERR Internal flag Flag is available on pin ERR[1] Flag is cleared UVNOM no by setting the pwon or wake-up flag UVBAT no when VBAT has recovered pwon in Pwon/Listen-only mode (coming from Standby mode, Go-to-sleep command mode, or Sleep mode) on entering Normal mode wake-up in Standby mode, Go-to-sleep command on entering Normal mode, or by setting mode, and Sleep mode (provided that VI/O the pwon or UVNOM flag and VCC are present) TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 7 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver Table 5. Accessing internal flags via pin ERR …continued Internal flag Flag is available on pin ERR[1] wake-up source in Normal mode (before the fourth on leaving Normal mode, or by setting dominant to recessive edge on pin TXD[2]) the pwon flag bus failure in Normal mode (after the fourth dominant on reentering Normal mode to recessive edge on pin TXD[2]) local failure in Pwon/Listen-only mode (coming from Normal mode) Flag is cleared on entering Normal mode or when RXD is dominant while TXD is recessive (provided that all local failures are resolved) [1] Pin ERR is an active-LOW output, so a LOW-level indicates a set flag and a HIGH-level indicates a cleared flag. Allow pin ERR to stabilize for at least 8 µs after changing operating modes. [2] Allow for a TXD dominant time of at least 4 µs per dominant-recessive cycle. 7.2.1 UVNOM flag UVNOM is the VCC and VI/O undervoltage detection flag. The flag is set when the voltage on pin VCC drops below VCC(sleep) for longer than tUV(VCC) or when the voltage on pin VI/O drops below VI/O(sleep) for longer than tUV(VI/O). When the UVNOM flag is set, the transceiver will enter Sleep mode to save power and not disturb the bus. In Sleep mode the voltage regulators connected to pin INH are disabled, avoiding the extra power consumption in case of a short circuit condition. After a waiting time (fixed by the same timers used for setting UVNOM) any wake-up request or setting of the pwon flag will clear UVNOM and the timers, allowing the voltage regulators to be reactivated at least until UVNOM is set again. 7.2.2 UVBAT flag UVBAT is the VBAT undervoltage detection flag. The flag is set when the voltage on pin VBAT drops below VBAT(stb). When UVBAT is set, the transceiver will try to enter Standby mode to save power and not disturb the bus. UVBAT is cleared when the voltage on pin VBAT has recovered. The transceiver will then return to the operating mode determined by the logic state of pins STB and EN. 7.2.3 Pwon flag Pwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT has recovered after it dropped below VBAT(pwon), particularly after the transceiver was disconnected from the battery. By setting the pwon flag, the UVNOM flag and timers are cleared and the transceiver cannot enter Sleep mode. This ensures that any voltage regulator connected to pin INH is activated when the node is reconnected to the battery. In Pwon/Listen-only mode the pwon flag can be made available on pin ERR. The flag is cleared when the transceiver enters Normal mode. 7.2.4 Wake-up flag The wake-up flag is set when the transceiver detects a local or a remote wake-up request. A local wake-up request is detected when a logic state change on pin WAKE remains stable for at least twake. A remote wake-up request is detected after two bus dominant states of at least tBUSdom (with each dominant state followed by a recessive state of at least tBUSrec). The wake-up flag can only be set in Standby mode, Go-to-sleep command mode or Sleep mode. Setting of the flag is blocked during the UVNOM flag waiting time. By setting the wake-up flag, the UVNOM flag and timers are cleared. The wake-up flag is TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 8 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver immediately available on pins ERR and RXD (provided that VI/O and VCC are present). The flag is cleared at power-on, or when the UVNOM flag is set or the transceiver enters Normal mode. 7.2.5 Wake-up source flag Wake-up source recognition is provided via the wake-up source flag, which is set when the wake-up flag is set by a local wake-up request via pin WAKE. The wake-up source flag can only be set after the pwon flag is cleared. In Normal mode the wake-up source flag can be made available on pin ERR. The flag is cleared at power-on or when the transceiver leaves Normal mode. 7.2.6 Bus failure flag The bus failure flag is set if the transceiver detects a bus line short circuit condition to VBAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, when trying to drive the bus lines dominant. In Normal mode the bus failure flag can be made available on pin ERR. The flag is cleared when the transceiver reenters Normal mode. 7.2.7 Local failure flag In Normal mode or Pwon/Listen-only mode the transceiver can recognize five different local failures and will combine them into one local failure flag. The five local failures are: TXD dominant clamping, RXD recessive clamping, a TXD-to-RXD short circuit, bus dominant clamping, and overtemperature. Nature and detection of these local failures is described in Section 7.3. In Pwon/Listen-only mode the local failure flag can be made available on pin ERR. The flag is cleared when entering Normal mode or when RXD is dominant while TXD is recessive, provided that all local failures are resolved. 7.3 Local failures The TJA1041A can detect five different local failure conditions. Any of these failures will set the local failure flag. In most cases the transmitter of the transceiver will be disabled. The following sections give the details. 7.3.1 TXD dominant clamping detection A permanent LOW-level on pin TXD (due to a hardware or software application failure) would drive the CAN bus into a permanent dominant state, blocking all network communication. The TXD dominant time-out function prevents such a network lockup by disabling the transmitter of the transceiver if pin TXD remains at a LOW level for longer than the TXD dominant time-out tdom(TXD). The tdom(TXD) timer defines the minimum possible bit rate of 40 kbit/s. The transmitter remains disabled until the local failure flag is cleared. 7.3.2 RXD recessive clamping detection An RXD pin clamped to HIGH-level will prevent the controller connected to this pin from recognizing a bus dominant state. So the controller can start messages at any time, which is likely to disturb all bus communication. RXD recessive clamping detection prevents this effect by disabling the transmitter when the bus is in dominant state without RXD reflecting this. The transmitter remains disabled until the local failure flag is cleared. TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 9 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 7.3.3 TXD-to-RXD short-circuit detection A short circuit between pins RXD and TXD would keep the bus in a permanent dominant state once the bus is driven dominant, because the low-side driver of RXD is typically stronger than the high-side driver of the controller connected to TXD. The TXD-to-RXD short circuit detection prevents such a network lockup by disabling the transmitter. The transmitter remains disabled until the local failure flag is cleared. 7.3.4 Bus dominant clamping detection A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network nodes could result in a differential voltage on the bus high enough to represent a bus dominant state. Because a node will not start transmission if the bus is dominant, the normal bus failure detection will not detect this failure, but the bus dominant clamping detection will. The local failure flag is set if the dominant state on the bus persists for longer than tdom(bus). By checking this flag, the controller can determine if a clamped bus is blocking network communication. There is no need to disable the transmitter. Note that the local failure flag does not retain a bus dominant clamping failure and is released as soon as the bus returns to recessive state. 7.3.5 Overtemperature detection To protect the output drivers of the transceiver against overheating, the transmitter will be disabled if the virtual junction temperature exceeds the shutdown junction temperature Tj(sd). The transmitter remains disabled until the local failure flag is cleared. 7.4 Recessive bus voltage stabilization In recessive state the output impedance of transceivers is relatively high. In a partially powered network (supply voltage is off in some of the nodes) any deactivated transceiver with a significant leakage current is likely to load the recessive bus to ground. This will cause a common-mode voltage step each time transmission starts, resulting in increased EME. Using pin SPLIT of the TJA1041A in combination with split termination (see Figure 5) will reduce this step effect. In Normal mode and Pwon/Listen-only mode pin SPLIT provides a stabilized 0.5VCC DC voltage. In Standby mode, Go-to-sleep command mode and Sleep mode pin SPLIT is set floating. 7.5 I/O level adapter The TJA1041A is equipped with a built-in I/O-level adapter. By using the supply voltage of the controller (to be supplied at pin VI/O) the level adapter ratiometrically scales the I/O-levels of the transceiver. For pins TXD, STB and EN the digital input threshold level is adjusted, and for pins RXD and ERR the HIGH-level output voltage is adjusted. This allows the transceiver to be directly interfaced with controllers on supply voltages between 2.8 V and 5.25 V, without the need for glue logic. 7.6 Pin WAKE Pin WAKE of the TJA1041A allows local wake-up triggering by a LOW-to-HIGH state change as well as a HIGH-to-LOW state change. This gives maximum flexibility when designing a local wake-up circuit. To keep current consumption at a minimum, after a twake delay the internal bias voltage of pin WAKE will follow the logic state of this pin. A HIGH level on pin WAKE is followed by an internal pull-up to VBAT. A LOW level on pin WAKE is TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 10 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver followed by an internal pull-down towards GND. To ensure EMI performance in applications not using local wake-up it is recommended to connect pin WAKE to pin VBAT or to pin GND. 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter DC voltage on pin VCC VCC DC voltage on pin VI/O VI/O VBAT DC voltage on pin VBAT Conditions Min Max Unit no time limit −0.3 +6 V operating range 4.75 5.25 V no time limit −0.3 +6 V operating range 2.8 5.25 V no time limit −0.3 +40 V operating range 5 27 V load dump - 40 V VTXD DC voltage on pin TXD −0.3 VI/O + 0.3 V VRXD DC voltage on pin RXD −0.3 VI/O + 0.3 V VSTB DC voltage on pin STB −0.3 VI/O + 0.3 V VEN DC voltage on pin EN −0.3 VI/O + 0.3 V VERR DC voltage on pin ERR −0.3 VI/O + 0.3 V VINH DC voltage on pin INH −0.3 VBAT + 0.3 V VWAKE DC voltage on pin WAKE −0.3 VBAT + 0.3 V IWAKE DC current on pin WAKE - −15 mA VCANH DC voltage on pin CANH 0 < VCC < 5.25 V; no time limit −27 +40 V VCANL DC voltage on pin CANL 0 < VCC < 5.25 V; no time limit −27 +40 V VSPLIT DC voltage on pin SPLIT 0 < VCC < 5.25 V; no time limit −27 +40 V Vtrt transient voltages on pins according to ISO 7637; CANH, CANL, SPLIT see Figure 6 and VBAT −200 +200 V Vesd electrostatic discharge voltage pins CANH, CANL and SPLIT −6 +6 kV pins TXD, RXD, VI/O and STB −3 +3 kV Human Body Model (HBM) [1] −4 +4 kV [2] −200 +200 V [3] −40 +150 °C −55 +150 °C all other pins Machine Model (MM) Tvj virtual junction temperature Tstg storage temperature [1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor (6 kV level with pin GND connected to ground). [2] Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor and a 10 Ω series resistor. [3] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tvj = Tamb + P × Rth(vj-amb), where Rth(vj-amb) is a fixed value. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 11 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 9. Thermal characteristics Table 7. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in SO14 package in free air 120 K/W Rth(j-s) thermal resistance from junction to substrate of bare die in free air 40 K/W 10. Characteristics Table 8. Characteristics VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol Parameter Conditions Min Typ Max Unit Supplies (pins VBAT, VCC and VI/O) VCC(sleep) VCC undervoltage detection VBAT = 12 V (fail-safe) level for forced Sleep mode 2.75 3.3 4.5 V VI/O(sleep) VI/O undervoltage detection level for forced Sleep mode 0.5 1.5 2 V VBAT(stb) VBAT voltage level for fail-safe fallback mode VCC = 5 V (fail-safe) 2.75 3.3 4.5 V VBAT(pwon) VBAT voltage level for setting pwon flag VCC = 0 V 2.5 3.3 4.1 V ICC VCC input current normal mode; VTXD = 0 V (dominant) 25 55 80 mA normal or pwon/listen-only mode; VTXD = VI/O (recessive) 2 6 10 mA standby or sleep mode - 1 10 µA normal mode; VTXD = 0 V (dominant) 100 350 1000 µA normal or pwon/listen-only mode; VTXD = VI/O (recessive) 15 80 200 µA standby or sleep mode - 0 5 µA normal or pwon/listen-only mode 15 30 40 µA standby mode; VCC > 4.75 V; VI/O = 2.8 V; VINH = VWAKE = VBAT = 12 V 10 20 30 µA sleep mode; VINH = VCC = VI/O = 0 V; VWAKE = VBAT = 12 V 10 20 30 µA II/O IBAT VI/O input current VBAT input current Transmitter data input (pin TXD) VIH HIGH-level input voltage 0.7VI/O - VCC + 0.3 V VIL LOW-level input voltage −0.3 - 0.3VI/O V IIH HIGH-level input current normal or pwon/listen-only mode; VTXD = VI/O −5 0 +5 µA IIL LOW-level input current normal or pwon/listen-only mode; VTXD = 0.3VI/O −70 −250 −500 µA Ci input capacitance not tested - 5 10 pF TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 12 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver Table 8. Characteristics …continued VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol Parameter Conditions Min Typ Max Unit Receiver data output (pin RXD) IOH HIGH-level output current VRXD = VI/O − 0.4 V; VI/O = VCC −1 −3 −6 mA IOL LOW-level output current VRXD = 0.4 V; VTXD = VI/O; bus dominant 2 5 12 mA Standby and enable control inputs (pins STB and EN) VIH HIGH-level input voltage 0.7VI/O - VCC + 0.3 V VIL LOW-level input voltage −0.3 - 0.3VI/O V IIH HIGH-level input current VSTB = VEN = 0.7VI/O 1 4 10 µA IIL LOW-level input current VSTB = VEN = 0 V - 0 −1 µA Error and power-on indication output (pin ERR) IOH HIGH-level output current VERR = VI/O − 0.4 V; VI/O = VCC −4 −20 −50 µA IOL LOW-level output current VERR = 0.4 V 0.1 0.2 0.35 mA Local wake-up input (pin WAKE) IIH HIGH-level input current VWAKE = VBAT − 1.9 V −1 −5 −10 µA IIL LOW-level input current VWAKE = VBAT − 3.1 V 1 5 10 µA Vth threshold voltage VSTB = 0 V VBAT − 3 VBAT − 2.5 VBAT − 2 V Inhibit output (pin INH) ∆VH HIGH-level voltage drop IINH = −0.18 mA 0.05 0.2 0.8 V IL leakage current sleep mode - 0 5 µA pin CANH 3 3.6 4.25 V pin CANL 0.5 1.4 1.75 V −0.1 - +0.15 V VTXD = 0 V (dominant); 45 Ω < RL < 65 Ω 1.5 - 3.0 V VTXD = VI/O (recessive); no load −50 - +50 mV normal or pwon/listen-only mode; VTXD = VI/O; no load 2 0.5VCC 3 V standby or sleep mode; no load −0.1 0 +0.1 V Bus lines (pins CANH and CANL) VO(dom) dominant output voltage VO(dom)(m) matching of dominant output voltage (VCC − VCANH − VCANL) VO(dif)(bus) differential bus output voltage (VCANH − VCANL) VO(reces) IO(sc) IO(reces) recessive output voltage short-circuit output current recessive output current VTXD = 0 V VTXD = 0 V (dominant) pin CANH; VCANH = 0 V −40 −70 −95 mA pin CANL; VCANL = 40 V 40 70 95 mA −2.5 - +2.5 mA −27 V < VCAN < 32 V TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 13 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver Table 8. Characteristics …continued VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol Parameter Conditions Min Typ Max Unit Vdif(th) differential receiver threshold voltage normal or pwon/listen-only mode (see Figure 7); −12 V < VCANH < 12 V; −12 V < VCANL < 12 V 0.5 0.7 0.9 V standby or sleep mode; −12 V < VCANH < 12 V; −12 V < VCANL < 12 V 0.4 0.7 1.15 V Vhys(dif) differential receiver hysteresis voltage normal or pwon/listen-only mode (see Figure 7); −12 V < VCANH < 12 V; −12 V < VCANL < 12 V 50 70 100 mV ILI input leakage current VCC = 0 V VCANH = VCANL = 5 V 100 170 250 µA Ri(cm) common-mode input resistance 15 25 35 kΩ Ri(cm)(m) common-mode input resistance matching −3 0 +3 % Ri(dif) differential input resistance 25 50 75 kΩ Ci(cm) common-mode input capacitance VTXD = VCC; not tested - - 20 pF Ci(dif) differential input capacitance VTXD = VCC; not tested - - 10 pF Rsc(bus) detectable short-circuit resistance between bus lines and VBAT, VCC and GND normal mode 0 - 50 Ω VCANH = VCANL Common-mode stabilization output (pin SPLIT) Vo output voltage normal or pwon/listen-only mode; −500 µA < ISPLIT < 500 µA 0.3VCC 0.5VCC 0.7VCC V IL leakage current standby or sleep mode; −22 V < VSPLIT < 35 V - 0 5 µA Timing characteristics; see Figure 8) and 9 td(TXD-BUSon) delay TXD to bus active normal mode 25 70 110 ns td(TXD-BUSoff) delay TXD to bus inactive normal mode 10 50 95 ns td(BUSon-RXD) delay bus active to RXD normal or pwon/listen-only mode 15 65 115 ns td(BUSoff-RXD) delay bus inactive to RXD normal or pwon/listen-only mode 35 100 160 ns tPD(TXD-RXD) propagation delay TXD to RXD VSTB = 0 V 40 - 255 ns tUV(VCC) undervoltage detection time on VCC 5 10 12.5 ms tUV(VI/O) undervoltage detection time on VI/O 5 10 12.5 ms tdom(TXD) TXD dominant time-out VTXD = 0 V 300 600 1000 µs tdom(bus) bus dominant time-out Vdif > 0.9 V 300 600 1000 µs th(min) minimum hold time of go-to-sleep command 20 35 50 µs TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 14 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver Table 8. Characteristics …continued VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol Parameter Conditions Min Typ Max Unit tBUSdom dominant time for wake-up via bus standby or sleep mode; VBAT = 12 V 0.75 1.75 5 µs tBUSrec recessive time for wake-up standby or sleep mode; VBAT = 12 V via bus 0.75 1.75 5 µs twake minimum wake-up time after receiving a falling or rising edge 5 25 50 µs 155 165 180 °C standby or sleep mode; VBAT = 12 V Thermal shutdown Tj(sd) [1] shutdown junction temperature All parameters are guaranteed over the virtual junction temperature range by design, but only 100 % tested at Tamb = 125 °C for dies on wafer level and in addition to this, 100 % tested at Tamb = 125 °C for cased products, unless specified otherwise. For bare dies, all parameters are only guaranteed with the reverse side of the die connected to ground. 11. Application information 3V 5V BAT VBAT WAKE VCC INH 10 7 VI/O 3 5 14 9 6 8 TJA1041A GND 4 2 13 CANH 11 SPLIT 12 CANL 1 VCC STB EN Port x, y, z ERR RXD TXD MICROCONTROLLER RXD TXD mnb116 CAN bus wires Fig 4. Typical application with 3 V microcontroller TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 15 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver VCC TJA1041A CANH 60 Ω R VSPLIT = 0.5VCC VSPLIT SPLIT in normal mode and pwon/listen-only mode; otherwise floating 60 Ω R CANL mnb117 GND Fig 5. Stabilization circuitry and application 12. Test information + 12 V +5 V 47 µF 100 nF VI/O 5 TXD EN STB WAKE VCC 3 10 µF VBAT 10 1 13 CANH 6 12 14 9 TJA1041A 11 8 500 kHz 7 4 CANL 1 nF 1 nF TRANSIENT GENERATOR SPLIT ERR INH RXD 2 GND mnb118 (1) The waveforms of the applied transients will be in accordance with ISO 7637 part 1, test pulses 1, 2, 3a, 3b, 5, 6 and 7. Fig 6. Test circuit for automotive transients TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 16 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver VRXD HIGH LOW hysteresis 0.5 0.9 Vi(dif)(bus) (V) mgs378 Fig 7. Hysteresis of the receiver + 12 V +5 V 47 µF 100 nF VI/O 5 TXD EN STB WAKE VCC 3 10 µF VBAT 10 13 1 CANH RL 60 Ω 6 14 9 12 TJA1041A 11 8 7 4 2 CL 100 pF CANL SPLIT ERR INH RXD 15 pF GND mnb119 Fig 8. Test circuit for timing characteristics TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 17 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver HIGH TXD LOW CANH CANL dominant (BUS on) 0.9 V Vi(dif)(bus)(1) 0.5 V recessive (BUS off) HIGH RXD 0.7VCC 0.3VCC td(TXD-BUSon) LOW td(TXD-BUSoff) td(BUSon-RXD) tPD(TXD-RXD) td(BUSoff-RXD) tPD(TXD-RXD) mgs377 (1) Vi(dif)(bus) = VCANH − VCANL. Fig 9. Timing diagram 12.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for use in automotive applications. TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 18 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 13. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT108-1 (SO14) TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 19 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 14. Bare die outline 1 14 2 13 3 12 4 TJA1041AU 11 10 5 x 9 0 6 0 7 8 mdb634 y (1) The reverse side of the bare die must be connected to ground. Fig 11. Bonding pad locations Table 9. Symbol Bonding pad locations Pad x y TXD 1 664.25 3004.5 GND 2 75.75 3044.25 VCC 3 115.5 2573 RXD 4 115.5 1862.75 VI/O 5 115.5 115.5 EN 6 264.5 114 INH 7 667.75 85 ERR 8 1076.75 115.5 WAKE 9 1765 85 VBAT 10 1765 792.5 SPLIT 11 1765 1442.25 CANL 12 1765 2115 CANH 13 1751 3002.5 STB 14 940.75 3004.5 [1] All x/y coordinates represent the position of the center of each pad (in µm) with respect to the left hand bottom corner of the top aluminium layer. TJA1041A_4 Product data sheet Coordinates[1] © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 20 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 21 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 12) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11 Table 10. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 11. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 12. TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 22 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 12. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes TJA1041A_4 20080729 Product data sheet - TJA1041A_3 Modifications: • Table 8: corrected unit for IOH - pin ERR TJA1041A_3 20071204 Product data sheet - TJA1041A_2 TJA1041A_2 20040220 Product specification - TJA1041A_1 TJA1041A_1 20030929 Objective specification - - TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 23 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TJA1041A_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 29 July 2008 24 of 25 TJA1041A NXP Semiconductors High-speed CAN transceiver 19. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.6 8 9 10 11 12 12.1 13 14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Optimized for in-vehicle high-speed communication . . . . . . . . . . . . . . . . . . . . . . . . . 1 Low-power management . . . . . . . . . . . . . . . . . 1 Protection and diagnosis (detection and signalling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pwon/Listen-only mode . . . . . . . . . . . . . . . . . . 6 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Go-to-sleep command mode . . . . . . . . . . . . . . 7 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Internal flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 UVNOM flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 UVBAT flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pwon flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Wake-up flag. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Wake-up source flag . . . . . . . . . . . . . . . . . . . . . 9 Bus failure flag . . . . . . . . . . . . . . . . . . . . . . . . . 9 Local failure flag . . . . . . . . . . . . . . . . . . . . . . . . 9 Local failures. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TXD dominant clamping detection . . . . . . . . . . 9 RXD recessive clamping detection . . . . . . . . . . 9 TXD-to-RXD short-circuit detection . . . . . . . . 10 Bus dominant clamping detection. . . . . . . . . . 10 Overtemperature detection . . . . . . . . . . . . . . . 10 Recessive bus voltage stabilization . . . . . . . . 10 I/O level adapter . . . . . . . . . . . . . . . . . . . . . . . 10 Pin WAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal characteristics. . . . . . . . . . . . . . . . . . 12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information. . . . . . . . . . . . . . . . . . 15 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Quality information . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 20 15 15.1 15.2 15.3 15.4 16 17 17.1 17.2 17.3 17.4 18 19 Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 21 22 23 24 24 24 24 24 24 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 29 July 2008 Document identifier: TJA1041A_4