DISCRETE SEMICONDUCTORS DATA SHEET PHC20306 Complementary enhancement mode MOS transistor Objective specification File under Discrete Semiconductors, SC13b 1998 Feb 18 Philips Semiconductors Objective specification Complementary enhancement mode MOS transistor PHC20306 FEATURES PINNING - SOT96-1 (SO8) • Very low on-state resistance PIN SYMBOL DESCRIPTION • High-speed switching 1 s1 source 1 • No secondary breakdown. 2 g1 gate 1 3 s2 source 2 APPLICATIONS 4 g2 gate 2 • Motor and actuator driver 5 d2 drain 2 • Power management 6 d2 drain 2 • Synchronized rectification. 7 d1 drain 1 8 d1 drain 1 DESCRIPTION One N-channel and one P-channel enhancement mode MOS transistor in an 8-pin SOT96-1 (SO8) plastic package. 8 handbook, halfpage d1 d1 5 d2 d2 CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. 4 1 MAM118 g1 s1 s2 g2 Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per channel VDS VSD drain-source voltage (DC) N-channel − 30 V P-channel − −30 V source-drain diode forward voltage N-channel VGD = 0; IS = 1.25 A − 1 V P-channel VGD = 0; IS = −1.25 A − −1.3 V open drain − ±20 V VGSO gate-source voltage (DC) VGSth gate-source threshold voltage ID RDSon Ptot 1998 Feb 18 V N-channel VDS = VGS; ID = 1 mA 1 − V P-channel VDS = VGS ; ID = −1 mA −1 − V N-channel − 8.2 A P-channel − −5.6 A drain current (DC) Ts = 80 °C drain-source on-state resistance N-channel VGS = 10 V; ID = 4 A − 30 mΩ P-channel VGS = −10 V; ID = −2.8 A − 65 mΩ Ts = 80 °C − 3.5 W total power dissipation 2 Philips Semiconductors Objective specification Complementary enhancement mode MOS transistor PHC20306 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per channel VDS drain-source voltage (DC) − 30 V − −30 V − ±20 V N-channel − 8.2 A P-channel − −5.6 A − 33 A N-channel P-channel VGSO gate-source voltage (DC) open drain ID drain current (DC) Ts = 80 °C; note 1 IDM peak drain current note 2 N-channel − −22.5 A Ts = 80 °C; note 3 − 3.5 W Tamb = 25 °C; note 4 − 2.6 W Tamb = 25 °C; note 5 − 1.1 W Tamb = 25 °C; note 6 − 1.5 W P-channel Ptot total power dissipation Tstg storage temperature −55 +150 °C Tj operating junction temperature −55 +150 °C N-channel − 3.5 A P-channel − −2.7 A N-channel − 14 A P-channel − −10.8 A Source-drain diode IS ISM Ts = 80 °C source current (DC) peak pulsed source current note 2 Notes 1. Ts is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time. 4. Maximum permissible dissipation per MOS transistor. Device mounted on a printed-circuit board with an Rth a-tp (ambient to tie-point) of 27.5 K/W. 5. Maximum permissible dissipation per MOS transistor. Device mounted on a printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted a on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 1998 Feb 18 3 Philips Semiconductors Objective specification Complementary enhancement mode MOS transistor PHC20306 THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER VALUE UNIT 20 K/W thermal resistance from junction to soldering point CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per channel V(BR)DSS VGSth IDSS IGSS RDSon Ciss Coss Crss QG QGS 1998 Feb 18 drain-source breakdown voltage N-channel VGS = 0; ID = 10 µA 30 − − V P-channel VGS = 0; ID = −10 µA −30 − − V N-channel VGS = VDS ; ID = 1 mA 1 − − V P-channel VGS = VDS ; ID = −1 mA −1 − − V N-channel VGS = 0; VDS = 24 V − − 100 nA P-channel VGS = 0; VDS = −24 V − − −100 nA N-channel − − ±100 nA P-channel − − ±100 nA gate-source threshold voltage drain-source leakage current gate leakage current VGS = ±20 V; VDS = 0 drain-source on-state resistance N-channel VGS = 4.5 V; ID = 2 A − − 45 mΩ VGS = 10 V; ID = 4 A − − 30 mΩ P-channel VGS = −4.5 V; ID = −1.4 A − − 100 mΩ VGS = −10 V; ID = −2.8 A − − 65 mΩ N-channel VGS = 0; VDS = 24 V; f = 1 MHz − 700 850 pF P-channel VGS = 0; VDS = −24 V; f = 1 MHz − tbf tbf pF N-channel VGS = 0; VDS = 24 V; f = 1 MHz − 260 320 pF P-channel VGS = 0; VDS = −24 V; f = 1 MHz − tbf tbf pF N-channel VGS = 0; VDS = 24 V; f = 1 MHz − 110 135 pF P-channel VGS = 0; VDS = −24 V; f = 1 MHz − tbf tbf pF N-channel VGS = 10 V; VDD = 15 V; ID = 4 A − 16 30 nC P-channel VGS = −10 V; VDD = −15 V; ID = −2.8 A − tbf tbf nC input capacitance output capacitance reverse transfer capacitance total gate charge gate-source charge N-channel VDD = 15 V; ID = 4 A − 2 − nC P-channel VDD = −15 V; ID = −2.8 A − tbf − nC 4 Philips Semiconductors Objective specification Complementary enhancement mode MOS transistor SYMBOL QGD PHC20306 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT gate-drain charge N-channel VDD = 15 V; ID = 4 A − 6.5 − nC P-channel VDD = −15 V; ID = −2.8 A − tbf − nC N-channel VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 8 − ns P-channel VGS = 0 to −10 V; VDD = −20 V; ID = −1 A; Rgen = 6 Ω − tbf − ns N-channel VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 21 − ns P-channel VGS = 0 to −10 V; VDD = −20 V; ID = −1 A; Rgen = 6 Ω − tbf − ns N-channel VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 17 25 ns P-channel VGS = 0 to −10 V; VDD = −20 V; ID = −1 A; Rgen = 6 Ω − tbf tbf ns N-channel VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 19 − ns P-channel VGS = −10 to 0 V; VDD = −20 V; ID = −1 A; Rgen = 6 Ω − tbf − ns N-channel VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 9 − ns P-channel VGS = −10 to 0 V; VDD = −20 V; ID = −1 A; Rgen = 6 Ω − tbf − ns N-channel VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 Ω − 40 60 ns P-channel VGS = −10 to 0 V; VDD = −20 V; ID = −1 A; Rgen = 6 Ω − tbf tbf ns N-channel VGD = 0; IS =1.25 A − − 1 V P-channel VGD = 0; IS = −1.25 A − − −1.3 V N-channel IS = 1.25 A; di/dt = −100 A/µs − 45 − ns P-channel IS = −1.25 A; di/dt = 100 A/µs − tbf − ns Switching times td(on) tr ton td(off) tf toff turn-on delay time rise time turn-on switching time turn-off delay time fall time turn-off switching time Source-drain diode VSD trr 1998 Feb 18 source-drain diode forward voltage reverse recovery time 5 Philips Semiconductors Objective specification Complementary enhancement mode MOS transistor PHC20306 PACKAGE OUTLINE SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 θ Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1998 Feb 18 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 6 o 8 0o Philips Semiconductors Objective specification Complementary enhancement mode MOS transistor PHC20306 DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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