INTEGRATED CIRCUITS DATA SHEET UDA1360TS Low-voltage low-power stereo audio ADC Preliminary specification Supersedes data of 1998 Oct 02 File under Integrated Circuits, IC01 2000 Feb 08 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC UDA1360TS FEATURES General • Low power consumption • 2.4 to 3.6 V power supply • Supports 256 and 384fs system clock • Supports sampling frequency range of 5 to 55 kHz • Small package size (SSOP16) • Integrated high-pass filter to cancel DC offset GENERAL DESCRIPTION • Power-down mode The UDA1360TS is a single chip stereo Analog-to-Digital Converter (ADC) employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording functions. • Supports 2 V (RMS) input signals • Easy application • Non-inverting ADC plus decimation filter. Multiple format output interface The UDA1360TS supports the I2S-bus data format and the MSB-justified data format with word lengths of up to 20 bits. • I2S-bus and MSB-justified format compatible • Up to 20 significant bits serial output. Advanced audio configuration • Stereo single-ended input configuration • High linearity, dynamic range and low distortion. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage 2.4 3.0 3.6 V VDDD digital supply voltage 2.4 3.0 3.6 V IDDA analog supply current − 9 − mA IDDD digital supply current − 3.5 − mA Tamb operating ambient temperature −40 − +85 °C ADC Vi(rms) input voltage (RMS value) see Table 1 − 1.0 − V (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB − −85 −80 dB at −60 dB; A-weighted − −37 −33 dB S/N signal-to-noise ratio VI = 0 V; A-weighted αcs channel separation − 97 − dB − 100 − dB ORDERING INFORMATION TYPE NUMBER UDA1360TS 2000 Feb 08 PACKAGE NAME SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm 2 VERSION SOT369-1 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC UDA1360TS BLOCK DIAGRAM handbook, full pagewidth VDDA VSSA 16 15 Vref(p) Vref(n) 5 4 Vref 2 UDA1360TS VINL 1 ADC (Σ∆) 8 DECIMATION FILTER VINR DATAO BCK WS CLOCK CONTROL 14 7 FSEL PWON 3 ADC (Σ∆) 13 11 12 DIGITAL INTERFACE DC-CANCELLATION FILTER 9 10 6 MGM967 SFOR Fig.1 Block diagram. 2000 Feb 08 SYSCLK 3 VDDD VSSD Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC UDA1360TS PINNING SYMBOL PIN DESCRIPTION VINL 1 left channel input Vref 2 reference voltage VINR 3 right channel input Vref(n) 4 Vref(p) 5 SFOR 6 data format selection input PWON 7 power control input SYSCLK 8 system clock input 256 or 384fs VDDD 9 digital supply voltage VSSD 10 digital ground PWON 7 BCK 11 bit clock input SYSCLK 8 WS 12 word selection input DATAO 13 data output FSEL 14 system clock frequency select VSSA 15 analog ground VDDA 16 analog supply voltage handbook, halfpage VINL 1 16 VDDA ADC negative reference voltage Vref 2 15 VSSA ADC positive reference voltage VINR 3 14 FSEL Vref(n) 4 Vref(p) 5 12 WS SFOR 6 11 BCK 10 VSSD 9 VDDD MGM968 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION Ritchie-coder architecture in a differential switched capacitor implementation. The over-sampling ratio is 128. System clock The UDA1360TS accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable via the static FSEL pin, and the system clock must be locked in frequency to the digital interface input signals. Input level The overall system gain is proportional to VDDA. The 0 dB input level is defined as that which gives a −1 dB FS digital output (relative to the full-scale swing). In addition, an input gain switch is incorporated with the above definitions. The UDA1360TS front-end is equipped with a selectable 0 or 6 dB gain, in order to supports 2 V (RMS) input using a series resistor of 12 kΩ. The options are 256fs (FSEL = LOW) and 384fs (FSEL = HIGH). The sampling frequency range is 5 to 55 kHz. For the definition of the pin settings for 1 or 2 V (RMS) mode given in Table 1, it is assumed that this resistor is present as a default component. The BCK clock can be up to 128fs, or in other words the BCK frequency is 128 times the Word Select (WS) frequency or less: fBCK ≤ 128 × fWS. If the 2 V (RMS) signal input is not needed, the external resistor should not be used. Notes: 1. The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface. 2. For MSB justified formats it is important to have a WS signal with 50% duty factor. Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1360TS consists of two 3rd-order Sigma-Delta modulators. They have a modified 2000 Feb 08 13 DATAO UDA1360TS 4 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC Table 1 Mute Application modes using input gain stage RESISTOR (12 kΩ) INPUT GAIN SWITCH MAXIMUM INPUT VOLTAGE Present 0 dB 2 V (RMS) Present 6 dB 1 V (RMS) Absent 0 dB 1 V (RMS) Absent 6 dB 0.5 V (RMS) UDA1360TS On recovery from power-down, the serial data output DATAO is held LOW until valid data is available from the decimation filter. This time tracks with the sampling frequency: 12288 t = ---------------- = 279 ms ; where fs = 44.1 kHz. fs Multiple format output interface Power-down mode The UDA1360TS supports the following data output formats; The PWON pin can control the power saving together with the optional gain switch for 2 V (RMS) or 1 V (RMS) input. When the PWON pin is set LOW, the ADC is set to power-down. When PWON is set to HIGH or to half the power supply, then either 6 dB gain or 0 dB gain in the analog front-end is selected. • I2S-bus with data word length of up to 20 bits • MSB-justified serial format with data word length of up to 20 bits. The output format can be set by the static SFOR pin. When SFOR is LOW, the I2S-bus is selected, when SFOR is set HIGH the MSB-justified format is selected. Application modes The UDA1360TS can be set to different modes using two 3-level pins and one 2-level pin. The selection of modes is given in Table 3. The data formats are illustrated in Fig.4. Left and right data channel words are time multiplexed. Decimation filter Table 3 The decimation from 128fs is performed in two stages. The first stage realizes 3rd-order sin x/x characteristic. This filter decreases the sample rate by 16. The second stage (an FIR filter) consists of 3 half-band filters, each decimating by a factor of 2. Table 2 PIN DC cancellation filter characteristics ITEM VALUE (dB) CONDITION Pass-band ripple none Pass-band gain 0 Stop band >0.55fs −60 Droop at 0.00045fs 0.031 Attenuation at DC at 0.00000036fs >40 Dynamic range 0 to 0.45fs >110 2000 Feb 08 5 Mode selection summary 1⁄ V 2 DD VSS SFOR I2S-bus PWON power-down 0 dB gain FSEL 256fs test mode − VDD MSB 6 dB gain 384fs Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC UDA1360TS handbook, full pagewidth WS tBCK(H) ts;WS tr tf th;WS BCK tBCK(L) td;DAT td;DAT(WS) Tcy th;DAT DATAO MGM969 Fig.3 Serial interface timing. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground, VDDD = VDDA = 3 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage note 1 − 5.0 VDDA analog supply voltage note 1 − 5.0 V Txtal(max) maximum crystal temperature − 150 °C Tstg storage temperature −65 +125 °C Tamb operating ambient temperature Ves electrostatic handling V −40 +85 °C note 2 −3000 +3000 V note 3 −300 +300 V Notes 1. All VDD and VSS connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2000 Feb 08 PARAMETER VALUE thermal resistance from junction to ambient 6 in free air VALUE UNIT 140 K/W Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC UDA1360TS DC CHARACTERISTICS VDDD = VDDA = 3 V; Tamb = 25 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage note 1 VDDD digital supply voltage note 1 2.4 3.0 3.6 V IDDA analog supply current operation mode − 9 − mA power-down mode − 3.5 − mA operation mode − 3.5 − mA power-down mode − 0.5 − mA IDDD digital supply current 2.4 3.0 3.6 V Digital inputs PINS BCK, FSEL, SYSCLK AND WS VIH HIGH-level input voltage 0.8VDDD − VDDD + 0.5 V VIL LOW-level input voltage −0.5 − 0.2VDDD V ILI input leakage current − − 10 µA CI input capacitance − − 10 pF PINS PWON AND SFOR VIH HIGH-level input voltage 0.8VDDD − VDDD + 0.5 V VIM MIDDLE-level input voltage 0.3VDDD − 0.7VDDD V VIL LOW-level input voltage −0.5 − 0.2VDDD V Digital output; Pin DATAO VOH HIGH-level output voltage IOH = −2 mA 0.85VDDD − − V VOL LOW-level output voltage IOL = 2 mA − − 0.4 V Vref reference voltage referenced to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V RI input resistance − 12 − kΩ CI input capacitance − 20 − pF Analog Note 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2000 Feb 08 7 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC UDA1360TS AC CHARACTERISTICS (ANALOG) VDDD = VDDA = 3 V; fi = 1 kHz; Tamb = 25 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT 1.0 − V 0.1 − dB at 0 dB −85 −80 dB at −60 dB; A-weighted −37 −33 dB VI = 0 V; A-weighted 97 − dB channel separation 100 − dB power supply rejection ratio 30 − dB Vi(rms) input voltage (RMS value) ∆Vi unbalance between channels (THD + N)/S total harmonic distortion plus noise-to-signal ratio S/N signal-to-noise ratio αcs PSRR see Table 1 AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = 2.7 to 3.6 V; Tamb = −20 to +85 °C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Timing Tsys clock cycle tCWL fsys LOW-level pulse width tCWH fsys HIGH-level pulse width fsys = 256fs 71 89 782 ns fsys = 384fs 47 59 522 ns 0.4Tsys − 0.6Tsys ns 0.4Tsys − 0.6Tsys ns − − ns − ns Serial data timing (see Fig.3) Tcy bit clock cycle 1⁄ tBCK(H) bit clock HIGH time 100 − tBCK(L) bit clock LOW time 100 − − ns tr rise time − − 20 ns tf fall time − − 20 ns td;DAT data output delay time (from BCK falling edge) − − 80 ns td;DAT(WS) data output delay time (from WS edge) − − 80 ns th;DAT data output hold time 0 − − ns ts;WS word selection set-up time 20 − − ns 2000 Feb 08 MSB-justified format 8 64fs This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2 3 ≥8 1 2 LSB MSB ≥8 3 BCK DATA MSB B2 B2 LSB MSB MSB B2 I2S-BUS FORMAT 9 WS RIGHT LEFT 1 2 3 ≥8 1 2 3 Philips Semiconductors 1 RIGHT Low-voltage low-power stereo audio ADC handbook, full pagewidth 2000 Feb 08 LEFT WS ≥8 BCK DATA MSB B2 LSB MSB B2 LSB MSB-JUSTIFIED FORMAT Preliminary specification UDA1360TS Fig.4 Serial interface formats. MGM970 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC UDA1360TS APPLICATION INFORMATION handbook, full pagewidth C11 Rin VINL X5 1 16 R3 VDDA 47 µF (16 V) C6 47 µF (16 V) C7 100 nF (63 V) C3 47 µF (16 V) Vref 2 15 C10 100 nF (63 V) VSSA VSSA VSSA C12 Rin VDDA 1Ω VINR X6 3 14 VDDD R7 47 kΩ FSEL 47 µF (16 V) X3-1 X3-2 X3-3 R6 47 kΩ VSSA Vref(n) C4 47 µF (16 V) C8 100 nF (63 V) R1 VDDA 4 13 DATAO VSSD X1-1 X1-2 X1-3 X1-4 X1-5 X1-6 X1-7 X1-8 X1-9 X1-10 UDA1360TS Vref(p) 5 12 6 11 WS 1Ω X4 VSSD SFOR VDDD BCK VSSD VDDD VSSD R4 47 kΩ X2-1 X2-2 X2-3 PWON R5 47 kΩ VSSD 7 10 VSSD C5 47 µF (16 V) VSSD R10 SYSCLK 47 Ω 8 9 C9 100 nF (63 V) R2 VDDD 1Ω VSSD R11 47 Ω L1 BLM32A07 VD VDDD L2 BLM32A07 VDDA C1 100 µF (16 V) VSSA C2 100 µF (16 V) VSSD Fig.5 Application diagram. 2000 Feb 08 10 MGM971 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC UDA1360TS PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 2000 Feb 08 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-152 11 o Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC SOLDERING UDA1360TS If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2000 Feb 08 12 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC UDA1360TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 2000 Feb 08 13 Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC NOTES 2000 Feb 08 14 UDA1360TS Philips Semiconductors Preliminary specification Low-voltage low-power stereo audio ADC NOTES 2000 Feb 08 15 UDA1360TS Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/02/pp16 Date of release: 2000 Feb 08 Document order number: 9397 750 05031