INTEGRATED CIRCUITS DATA SHEET TDA8765 10-bit high-speed Analog-to-Digital Converter (ADC) Preliminary specification Supersedes data of 1998 May 08 File under Integrated Circuits, IC02 1999 Jan 06 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 FEATURES APPLICATIONS • 10-bit resolution • High-speed analog-to-digital conversion for • Sampling rate up to 55 MHz – Video signal digitizing • −3 dB bandwidth of 200 MHz – High Definition TV (HDTV) • 5 V power supplies – Imaging (camera scanner) • Binary or twos-complement CMOS outputs – Medical imaging • In-range CMOS-compatible output – Telecommunication • TLL- CMOS-compatible static digital inputs – Base-station receiver. • 3 to 5 V CMOS-compatible digital outputs • Differential clock input; Positive Emitter Coupled Logic (PECL) compatible GENERAL DESCRIPTION The TDA8765 is a bipolar 10-bit Analog-to-Digital Converter (ADC) optimized for telecommunications and professional imaging. It converts the analog input signal into 10-bit binary coded digital words at a maximum sampling rate of 55 MHz. All static digital inputs (SH, CE and OTC) are TTL and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. • Power dissipation 325 mW (typical) • Low analog input capacitance (typical 2 pF), no buffer amplifier required • Integrated sample-and-hold amplifier • Differential analog input • External amplitude range control • Voltage controlled regulator included. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 5.25 V ICCA analog supply current − 33 tbf mA ICCD digital supply current − 30 tbf mA ICCO output supply current fCLK = 4 MHz; fi = 400 kHz − 3.2 tbf mA INL integral non-linearity fCLK = 4 MHz; fi = 400 kHz − ±0.5 ±1.75 LSB DNL differential non-linearity fCLK = 4 MHz; fi = 400 kHz − ±0.3 ±0.5 LSB fCLK(max) maximum clock frequency Ptot TDA8765H/4 40 − − MHz TDA8765H/5 55 − − MHz − 325 tbf mW total power dissipation ORDERING INFORMATION TYPE NUMBER TDA8765H/4 TDA8765H/5 1999 Jan 06 PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm 2 VERSION SOT307-2 SAMPLING FREQUENCY (MHz) 40 55 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 BLOCK DIAGRAM VCCA1 VCCA2 VCCA3 VCCA4 handbook, full pagewidth 2 9 3 41 CLK CLK VCCD1 VCCD2 36 35 37 15 OTC CE 19 18 21 D9 TDA8765 CLOCK DRIVER MSB 22 D8 23 D7 Vref 24 D6 11 25 D5 CMOS OUTPUTS VI 43 VI 42 27 D3 ANALOG-TO-DIGITAL CONVERTER AMP LATCHES 28 D2 29 D1 sampleand-hold SH n.c. data outputs 26 D4 30 D0 LSB 39 33 1, 5 to 8, 12 to 14, 16, 31 and 32 44 10 AGND1 AGND2 OVERFLOW/ UNDERFLOW LATCH 4 20 CMOS OUTPUT 40 38 17 34 AGND4 DGND1 DGND2 OGND VCCO IR MGK801 AGND3 Fig.1 Block diagram. 1999 Jan 06 3 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION n.c. 1 not connected D7 23 data output; bit 7 VCCA1 2 analog supply voltage 1 (+5 V) D6 24 data output; bit 6 VCCA3 3 analog supply voltage 3 (+5 V) D5 25 data output; bit 5 AGND3 4 analog ground 3 D4 26 data output; bit 4 n.c. 5 not connected D3 27 data output; bit 3 n.c. 6 not connected D2 28 data output; bit 2 n.c. 7 not connected D1 29 data output; bit 1 n.c. 8 not connected D0 30 data output; bit 0 (LSB) VCCA2 9 analog supply voltage 2 (+5 V) n.c. 31 not connected AGND2 10 analog ground 2 n.c. 32 not connected Vref 11 reference voltage input VCCO 33 output supply voltage (3 to 5.25 V) n.c. 12 not connected OGND 34 output ground n.c. 13 not connected CLK 35 complementary clock input; active LOW n.c. 14 not connected VCCD2 15 digital supply voltage 2 (+5 V) CLK 36 clock input 37 digital supply voltage 1 (+5 V) n.c. 16 not connected VCCD1 DGND2 17 digital ground 2 DGND1 38 digital ground 1 control input twos complement output; active HIGH SH 39 18 sample-and-hold enable input (CMOS level; active HIGH) chip enable input (CMOS level; active LOW) AGND4 40 analog ground 4 19 VCCA4 41 analog supply voltage 4 (+5 V) IR 20 in-range output VI 42 positive analog input voltage D9 21 data output; bit 9 (MSB) VI 43 negative analog input voltage D8 22 data output; bit 8 AGND1 44 analog ground 1 OTC CE 1999 Jan 06 4 Philips Semiconductors Preliminary specification 34 OGND n.c. 1 33 VCCO VCCA1 2 32 n.c. VCCA3 3 31 n.c. AGND3 4 30 D0 n.c. 5 29 D1 TDA8765H 26 D4 VCCA2 9 25 D5 AGND2 10 24 D6 Vref 11 23 D7 5 D8 22 D9 21 IR 20 28 D2 CE 19 OTC 18 8 DGND2 17 n.c. n.c. 16 27 D3 VCCD2 15 7 n.c. 14 n.c. n.c. 13 6 n.c. 12 n.c. Fig.2 Pin configuration. 1999 Jan 06 35 CLK 36 CLK 37 VCCD1 38 DGND1 TDA8765 39 SH 40 AGND4 41 VCCA4 42 VI 44 AGND1 handbook, full pagewidth 43 VI 10-bit high-speed Analog-to-Digital Converter (ADC) MGK800 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO output supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage difference VCCA − VCCD −1.0 +1.0 V VCCD − VCCO −1.0 +4.0 V VCCA − VCCO −1.0 +4.0 V VI input voltage at pins 42 and 43 0.3 VCCA V Vi(p-p) input voltage at pins 35 and 36 for differential clock drive (peak-to-peak value) − VCCD V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 +85 °C Tj junction temperature − 150 °C referenced to AGND Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply voltage differences ∆VCC are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1999 Jan 06 PARAMETER CONDITION thermal resistance from junction to ambient 6 in free air VALUE UNIT 75 K/W Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 CHARACTERISTICS VCCA = V2 to V44, V9 to V10, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to 85 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C, VI(p-p) − VI(p-p) = 2.0 V and CL = 10 pF; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 5.25 V ICCA analog supply current − 33 45 mA ICCD digital supply current ICCO output supply current − 30 37 mA fCLK = 4 MHz; fi = 400 kHz − 3.2 tbf mA fCLK = 40 MHz; fi = 4.43 MHz − 11 tbf mA 3.19 − 3.52 V Inputs CLK AND CLK (REFERENCED TO DGND) VIL LOW-level input voltage VCCD = 5 V; note 1 VIH HIGH-level input voltage VCCD = 5 V; note 1 3.83 − 4.12 V IIL LOW-level input current VCLK or VCLK = 3.19 V −10 − − µA IIH HIGH-level input current VCLK or VCLK = 3.83 V − − 10 µA Zi input impedance fCLK = 40 MHz 2 − − kΩ Ci input capacitance fCLK = 40 MHz − − 2 pF ∆VCLK(p-p) differential AC input voltage for switching (VCLK − VCLK; peak-to-peak value) DC voltage level = 2.5 V 0.5 − 2.0 V OTC, SH AND CE (REFERENCED TO DGND); see Tables 2 and 3 VIL LOW-level input voltage 0 − 0.8 V 2.0 − VCCD V VIH HIGH-level input voltage IIL LOW-level input current VIL = 0.8 V −20 − − µA IIH HIGH-level input current VIH = 2.0 V − − 20 µA VI AND VI (REFERENCED TO AGND; see Table 1); VREF = VCCA − 1.825 V IIL LOW-level input current − 10 − µA IIH HIGH-level input current − 10 − µA Ri input resistance fi = 4.43 MHz 100 − − kΩ Ci input capacitance fi = 4.43 MHz − − 2 pF VI(CM) common mode input voltage VI = VI; output code 511 1999 Jan 06 VCCA = 5 V tbf 3.6 tbf V VCCA = 4.75 V tbf 3.35 tbf V VCCA = 5.25 V tbf 3.85 tbf V 7 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8765 CONDITIONS MIN. TYP. MAX. UNIT Voltage controlled regulator input Vref (referenced to AGND); note 2 Vref full-scale fixed voltage VI(p-p) − VI(p-p) input voltage amplitude (peak-to-peak value) Iref VCCA = 5 V − 3.175 − V Vref = VCCA − 1.825 V − 2.0 − V − 0.5 10 µA 0 − 0.5 V input current at Vref Outputs (referenced to OGND) DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND) VOL LOW-level output voltage IOL = 2 mA VOH HIGH-level output voltage IOH = −0.4 mA VCCO − 0.5 − VCCO V Io output current in 3-state output level between 0.5 V and VCCO −20 − +20 µA SH = HIGH − − 1 MHz SH = LOW − − 1 kHz TDA8765H/4 40 − − MHz TDA8765H/5 55 − − MHz Switching characteristics CLOCK FREQUENCY fCLK; see Fig.5 fCLK(min) fCLK(max) minimum clock frequency maximum clock frequency tCLKH clock pulse width HIGH 8.5 − − ns tCLKL clock pulse width LOW 8.5 − − ns Analog signal processing; 50% clock duty factor; VI − VI = 2.0 V; Vref = VCCA− 1.825 V; see Table 1 LINEARITY INL integral non-linearity fCLK = 4 MHz; fi = 400 kHz − ±0.5 ±1.75 LSB DNL differential non-linearity fCLK = 4 MHz; fi = 400 kHz; no missing code − ±0.3 ±0.5 LSB Eoffset offset error VCCA = VCCD = VCCO = 5 V; Tamb = 25 °C; VI = VI; output code = 511 tbf −11 tbf mV EG gain error amplitude; spread from device to device VCCA = VCCD = VCCO = 5 V; Tamb = 25 °C; VI(p-p) − VI(p-p) = 2.0 V −5 − +5 %FS −3 dB; full-scale input tbf 200 − MHz BANDWIDTH (fCLK = 55 MHz); note 3 B 1999 Jan 06 analog bandwidth 8 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8765 CONDITIONS MIN. TYP. MAX. UNIT HARMONICS (fCLK = 40 MHz) Hfund(FS) fundamental harmonics (full scale) fi = 4.43 MHz Htot(FS) harmonics (full scale); all components fi = 4.43 MHz second harmonic − 0 dB − −75 − dB − −70 − dB total harmonic distortion fi = 4.43 MHz; note 4 − −66 − dB thermal noise (RMS value) grounded input; fCLK = 40 MHz − 0.2 tbf LSB fi = 4.43 MHz tbf 71 − dB fi = 10 MHz tbf 68 − dB fi = 20 MHz tbf 67 − dB without harmonics; fCLK = 40 MHz; fi = 4.43 MHz − 59 − dB fi = 4.43 MHz 9.0 9.6 − bits fi = 10 MHz − 9.6 − bits fi = 15 MHz − 9.5 − bits fi = 4.43 MHz − 9.6 − bits fi = 10 MHz − 9.4 − bits fi = 15 MHz − 9.3 − bits fi = 20 MHz − 9.1 − bits third harmonic THD − THERMAL NOISE Nth(rms) SPURIOUS FREE DYNAMIC RANGE DRsf spurious free dynamic range SIGNAL-TO-NOISE RATIO; note 5 S/N signal-to-noise ratio EFFECTIVE NUMBER OF BITS; see Figs 3 and 4 and note 5 Nbit effective number of bits TDA8765H/4 (fCLK = 40 MHz) effective number of bits TDA8765H/5 (fCLK = 55 MHz) INTERMODULATION; note 6 TTIR two-tone intermodulation rejection fCLK = 40 MHz tbf 66 − dB d3 third-order intermodulation distortion fCLK = 40 MHz tbf 67 − dB fCLK = 40 MHz; fi = 4.43 MHz; VI = ±16 LSB at code 511 − 10−15 tbf times/ sample BIT ERROR RATE BER 1999 Jan 06 bit error rate 9 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8765 CONDITIONS MIN. TYP. MAX. UNIT Timing (CL = 10 pF); see Fig.5 and note 7 td(s) sampling delay time th output hold time td output delay time − − 2 ns 4 − − ns VCCO = 5.25 V − 10 15 ns VCCO = 3.0 V − 13 18 ns 3-state output delay times; see Fig.6 tdZH enable HIGH − 14 18 ns tdZL enable LOW − 16 20 ns tdHZ disable HIGH − 16 20 ns tdLZ disable LOW − 14 18 ns Notes 1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation: a) PECL mode 1 (DC level varies equal to DC level of VCCD): CLK and CLK inputs are at differential PECL levels. b) PECL mode 2 (DC level varies equal to DC level of VCCD): CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. c) PECL mode 3 (DC level varies equal to DC level of VCCD): CLK input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor. 2. It is possible with an external reference connected to pin Vref to adjust the ADC input range. This voltage has to be referenced to VCCA. For VCCA − 1.825 V, the differential input voltage amplitude is 2 V (p-p). 3. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. 4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics: F THD = 20 log --------------------------------------------------------------------------------------------------------------2 2 2 2 2 (2nd) + (3rd) + (4th) + (5th) + (6th) where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input. 5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR: SNR = Nbit × 6.02 + 1.76 dB. 6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full scale for each input signal). d3 is the ratio of the RMS-value of either input tone to the RMS-value of the worst case third order intermodulation product. 7. Output data acquisition: the output data is available after the maximum delay of td. 1999 Jan 06 10 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) Table 1 TDA8765 Output coding with differential inputs (typical values to AGND); Vi(p-p) − Vi(p-p) = 2.0 V; Vref = VCCA − 1.825 V CODE Vi(p-p) Vi(p-p) BINARY OUTPUTS TWOS COMPLEMENT OUTPUTS D9 TO D0 D9 TO D0 1000000000 IR Underflow <3.1 >4.1 0 0000000000 0 3.1 4.1 1 0000000000 1 0 0 0 0 0 0 0 00 1 − − 1 0000000001 1000000001 ↓ − − ↓ ↓ ↓ 511 3.6 3.6 1 0111111111 1111111111 ↓ − − ↓ ↓ ↓ 1022 − − 1 1111111110 0111111110 1023 4.1 3.1 1 1111111111 0111111111 Overflow >4.1 <3.1 0 1111111111 0111111111 Table 2 Mode selection OTC CE D0 TO D9 AND IR 0 0 binary; active 1 0 twos complement; active X(1) 1 high impedance Note 1. X = don’t care. Table 3 Sample-and-hold selection SH SAMPLE-AND-HOLD 1 active 0 inactive; tracking mode 1999 Jan 06 11 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 MGL430 0 amplitude (dB) −20 handbook, full pagewidth −40 −60 −80 −100 −120 −140 −160 0 5 10 15 f (MHz) 20 Effective bits: 9.68; THD = −70.8 dB. Harmonic levels (dB): 2nd = −80.3; 3rd = −74.5; 4th = −87.7; 5th = −76.4; 6th = −78.6. Fig.3 Typical fast Fourier transform (fCLK = 40 MHz; fi = 4.43 MHz). MGL431 0 amplitude (dB) −20 handbook, full pagewidth −40 −60 −80 −100 −120 −140 −160 0 5 10 15 20 Effective bits: 9.12; THD = −62.5 dB. Harmonic levels (dB): 2nd = −73.0; 3rd = −63.4; 4th = −80.9; 5th = −78.1; 6th = −74.4. Fig.4 Typical fast Fourier transform (fCLK = 50 MHz; fi = 21.4 MHz). 1999 Jan 06 12 f (MHz) 25 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 tCLKL handbook, full pagewidth tCLKH HIGH 50% CLK LOW sample N + 1 sample N sample N + 2 VI th td(s) HIGH DATA D0 to D9 DATA N−2 DATA N−1 DATA N DATA N+1 50% LOW td MBH427 Fig.5 Timing diagram. handbook, full pagewidth VCCD 50 % CE 0V tdHZ tdZH HIGH 90 % output data 50 % tdLZ LOW tdZL HIGH output data 50 % LOW 10 % VCCD 3.3 kΩ TDA8765 S1 15 pF CE TEST S1 tdLZ VCCD tdZL VCCD tdHZ DGND tdZH DGND MBH423 fCE = 100 kHz. Fig.6 Timing diagram and test conditions of 3-state output delay time. 1999 Jan 06 13 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 APPLICATION INFORMATION handbook, full pagewidth 220 nF 1:1 5V VI IN 100 nF 100 Ω SH mode 5V 100 nF 100 Ω CLK VI (1) CLK VCCA 5V R1 n.c. 5V 4.7 µF 10 nF R2 100 nF 100 nF 5V 100 nF Vref (3) 44 43 42 41 40 39 38 37 36 35 34 1 100 nF 33 2 32 3 31 n.c. 4 30 D0 (LSB) 29 D1 28 D2 n.c n.c. 5 n.c. 6 n.c. 7 27 D3 n.c. 8 26 D4 9 25 D5 10 24 D6 11 23 D7 TDA8765 12 13 14 15 16 17 18 19 20 21 22 n.c. n.c. n.c. n.c. 5V 100 nF IR D8 D9 (MSB) MGK802 chip select input output format select The analog, digital and output supplies should be separated and decoupled. (1) Single-ended clock signals can be applied if required. (2) R1 and R2 must be determined in order to obtain a middle voltage of 3.6 V; see common mode input voltage. In addition, the minimum current into these resistors should be about 1 mA in order to ensure a sufficient analog input stability. (3) Vref must be decoupled to VCCA. Fig.7 Application diagram. 1999 Jan 06 14 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 1999 Jan 06 EUROPEAN PROJECTION 15 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 If wave soldering is used the following conditions must be observed for optimal results: SOLDERING Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. 1999 Jan 06 When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 16 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Jan 06 17 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 NOTES 1999 Jan 06 18 Philips Semiconductors Preliminary specification 10-bit high-speed Analog-to-Digital Converter (ADC) TDA8765 NOTES 1999 Jan 06 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/750/02/pp20 Date of release: 1999 Jan 06 Document order number: 9397 750 04716