REVISIONS LTR DESCRIPTION DATE APPROVED A Make change to VIH and VIL as specified under paragraph 1.4. 03-10-31 R. MONNIN B Add device type 02. Make changes to 1.3, 1.4, table I, figure 1, figure 2, figure 3, and figure 4. - ro 05-09-29 R. MONNIN C Update boilerplate paragraphs to current requirements. - PHN 13-10-28 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV C C C C C C C C C C C C C PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY TOM HESS 03-04-08 TITLE MICROCIRCUIT, DIGITAL-LINEAR, LOW POWER, DUAL, 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN, MONOLITHIC SILICON APPROVED BY RAYMOND MONNIN SIZE CODE IDENT. NO. A REV AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DWG NO. V62/03628 16236 C PAGE 1 OF 13 5962-V004-14 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low power, dual, digital-to-analog converter with internal reference and power down microcircuit, with an operating temperature ranges of -40°C to +125°C for device type 01 and of -55°C to +125°C for device type 02. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/03628 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 TLV5638Q-EP 02 TLV5638M-EP Circuit function Low power, dual, digital-to-analog converter with internal reference and power down Low power, dual, digital-to-analog converter with internal reference and power down 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 8 JEDEC PUB 95 Package style MS-012 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage (VDD to AGND) ....................................................................... 7 V Reference input voltage range ........................................................................ -0.3 V VDD +0.3 V Digital input voltage range ............................................................................... Storage temperature range .............................................................................. Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds .................... Package thermal impedance, (θJA) ................................................................. -0.3 V VDD +0.3 V -65°C to +150°C 260°C 131°C/W 1.4 Recommended operating conditions. 2/ Supply voltage (VDD): With VDD = 5 V ............................................................................................ 4.5 V to 5.5 V With VDD = 3 V ............................................................................................ 2.7 V to 3.3 V Power on reset (POR) ..................................................................................... 0.55 V to 2.0 V High level digital input voltage (VIH): With VDD = 2.7 V ......................................................................................... 2.0 V minimum With VDD = 5.5 V ......................................................................................... 2.4 V minimum Low level digital input voltage (VIL): With VDD = 2.7 V ......................................................................................... 0.6 V maximum With VDD = 5.5 V ......................................................................................... 0.8 V maximum Reference voltage (Vref to REF terminal): With VDD = 5 V ............................................................................................ AGND to VDD-1.5 3/ With VDD = 3 V ............................................................................................ AGND to VDD-1.5 3/ Load resistance (RL) ....................................................................................... 2 kΩ minimum Load capacitance (CL) .................................................................................... 100 pF maximum Clock frequency (fCLK) .................................................................................... 20 MHz maximum Ambient operating temperature range (TA) : Device type 01 ............................................................................................. -40°C to +125°C 4/ Device type 02 ............................................................................................. -55°C to +125°C 4/ 1/ 2/ 3/ 4/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Due to the x2 output buffer, a reference input voltage ≥ (VDD – 0.4 V) / 2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference in used. Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, TA Limits Min Unit Max Power supply section Power supply current IDD VDD = 5 V, internal reference, fast no load, all inputs = AGND or VDD, DAC latch = 0x800 VDD = 5 V, internal reference, slow -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 7 mA 3.6 no load, all inputs = AGND or VDD, DAC latch = 0x800 6.3 VDD = 3 V, internal reference, fast no load, all inputs = AGND or VDD, DAC latch = 0x800 3.0 VDD = 3 V, internal reference, slow no load, all inputs = AGND or VDD, DAC latch = 0x800 6.3 VDD = 5 V, external reference, fast no load, all inputs = AGND or VDD, DAC latch = 0x800 3.0 VDD = 5 V, external reference, slow no load, all inputs = AGND or VDD, DAC latch = 0x800 5.7 VDD = 3 V, external reference, fast no load, all inputs = AGND or VDD, DAC latch = 0x800 2.6 VDD = 3 V, external reference, slow no load, all inputs = AGND or VDD, DAC latch = 0x800 Power down supply current Power supply rejection 10 PSRR ratio Zero scale 3/ -65 typical Full scale 4/ -65 typical µA dB See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 5 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Limits Min Unit Max Static DAC specifications section Resolution Integral nonlinearity, end point adjusted INL 5/ Differential nonlinearity DNL 6/ Zero scale error (offset error at zero scale) EZS 7/ Zero scale error temperature coefficient EZS TC 8/ Gain error EG 9/ Gain error temperature coefficient EG TC 10/ -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 12 Bits ±6 LSB ±1 LSB ±24 mV 10 typical ±0.6 10 typical ppm/°C % full scale V ppm/°C Output specifications section Output voltage VO Output load regulation accuracy RL = 10 kΩ VO = 4.096 V, 2.048 V, RL = 2 kΩ -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 0 VDD – 0.4 V ±0.25 % full scale V -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 1.003 1.045 V 2.027 2.069 V 1 mA Reference pin configured as output (REF) section Low reference voltage Vref (OUTL) High reference voltage Vref (OUTH) Output source current Iref (source) Output sink current Iref (sink) VDD > 4.75 V -1 mA See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Limits Min Unit Max Reference pin configured as output (REF) section – continued Load capacitance CL Power supply rejection ratio PSRR -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 100 pF -65 typical dB 0 V Reference pin configured as output (REF) section Input voltage -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 VI Input resistance RI Input capacitance CI Reference input bandwidth Reference feedthrough VDD – 1.5 10 typical MΩ 5 typical pF REF = 0.2 VPP + 1.024 V dc, fast 1.3 typical MHz REF = 0.2 VPP + 1.024 V dc, slow 525 typical KHz REF = 1 VPP at 1 kHz + 1.024 V dc 11/ -80 typical dB 1 µA Digital inputs section High level digital input current IIH VI = VDD Low level digital input current IIL VI = 0 V Input capacitance CI -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 µA -1 8 typical pF Analog output dynamic performance section Output settling time, full scale tS(FS) RL = 10 kΩ, CL = 100 pF, fast 12/ RL = 10 kΩ, CL = 100 pF, slow 12/ Output settling time, code to code tS(CC) -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 3 µs 7 RL = 10 kΩ, CL = 100 pF, fast 13/ 1.5 RL = 10 kΩ, CL = 100 pF, slow 13/ 2 µs See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Limits Min Unit Max Analog output dynamic performance section – continued Slew rate SR RL = 10 kΩ, CL = 100 pF, fast 14/ RL = 10 kΩ, CL = 100 pF, slow 14/ Glitch energy DIN = 0 to 1, FCLK = 100 kHz, -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 12 typical V/µs 1.8 typical 5 typical nV-s CS = VDD Signal to noise ratio SNR fS = 480 kSPS, fout = 1 kHz, 69 dB 58 dB RL = 10 kΩ, CL = 100 pF Signal to noise + distortion S/(N+D) Total harmonic distortion THD fS = 480 kSPS, fout = 1 kHz, RL = 10 kΩ, CL = 100 pF -57 fS = 480 kSPS, fout = 1 kHz, dB RL = 10 kΩ, CL = 100 pF Spurious free dynamic range fS = 480 kSPS, fout = 1 kHz, 57 dB 10 ns 10 ns RL = 10 kΩ, CL = 100 pF Digital input timing requirement section Setup time, CS low before first negative SCLK edge tSU (CS-CK) See figure 4 Setup time, 16 th negative SCLK edge (when D0 is sampled) tSU (C16-CS) See figure 4 SCLK pulse width high tWH See figure 4 25 ns SCLK pulse width low tWL See figure 4 25 ns -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 before CS rising edge See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 8 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Limits Min Unit Max Digital input timing requirement section – continued. Setup time, data ready before SCLK falling edge tsu(D) See figure 4 Hold time, data held valid after SCLK falling edge th(D) See figure 4 -40°C to +125°C for device type 01 and -55°C to +125°C for device type 02 10 ns 5 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VDD = 2.7 V to 5.5 V, Vref = 2.048 V, Vref = 1.024 V. 3/ Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [ (EZS (VDDmax) – EZS (VDDmin)) / VDDmax ]. 4/ Power supply rejection ratio at full scale error is measured by varying VDD and is given by: 7/ PSRR = 20 log [ (EG (VDDmax) – EG (VDDmin)) / VDDmax ]. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors. Tested from code 32 to 4095. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measure and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Zero scale error is the deviation from zero voltage output when the digital input code is zero. 8/ Zero scale error temperature coefficient is given by: EZS TC = [ EZS (Tmax) – EZS (Tmin) ] / Vref x 10 / (Tmax – Tmin). 9/ Gain error is the deviation from the ideal output (2 Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. 5/ 6/ 6 6 10/ Gain temperature coefficient is given by: EG TC = [ EG (Tmax) – EG (Tmin) ] / Vref x 10 / (Tmax – Tmin). 11/ Reference feedthrough is measured at the DAC output with an input code = 0x000. 12/ Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 13/ Settling time is the time for the output signal to remain with ±0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 14/ Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full scale voltage. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 9 Case X FIGURE 1. Case outlines. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 10 Case X Dimensions Millimeters Symbol Min Max Symbol Inches Min Max A A1 b c D --0.069 0.004 0.010 0.012 0.020 0.008 nominal 0.189 0.197 --1.75 0.10 0.25 0.31 0.51 0.20 nominal 4.80 5.00 E E1 e L Inches Min Max 0.150 0.157 0.228 0.244 0.050 0.016 0.050 Millimeters Min Max 3.80 5.80 4.00 6.20 1.27 0.40 1.27 NOTE: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.006 inch (0.15 mm). 3. Falls within JEDEC MS-012-AA. FIGURE 1. Case outline. – continued. Device types 01 and 02 Terminal number Terminal symbol I/O/P Description 1 DIN I Digital serial data input 2 SCLK I Digital serial clock input 3 CS I Chip select. Digital input active low, used to enable/disable inputs. 4 OUTPUT A O DAC A analog output 5 AGND P Ground 6 REF I/O 7 OUTPUT B O DAC B analog output 8 VDD P Positive power supply Analog reference voltage input / output FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 11 FIGURE 3. Block diagram. FIGURE 4. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 12 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number Top-side marking V62/03628-01XE 01295 TLV5638QDREP 5638QE V62/03628-02XE 01295 TLV5638MDREP 5638ME 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/03628 PAGE 13