REVISIONS LTR DESCRIPTION A Add a footnote to Table I. Add footnotes to figure 1. Update boilerplate paragraphs to current requirements. - ro DATE APPROVED 10-10-19 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY TOM HESS 04-02-11 TITLE MICROCIRCUIT, DIGITAL-LINEAR, 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN, MONOLITHIC SILICON APPROVED BY RAYMOND MONNIN SIZE A REV AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 CODE IDENT. NO. DWG NO. V62/04646 16236 A PAGE 1 OF 14 5962-V075-10 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance low power dual 12-bit digital-to-analog converter (DAC) with power down microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: - V62/04646 Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Generic Device type 01 Circuit function TLV5618A-EP 2.7 V to 5.5 V low power dual 12-bit digital-to-analog converter with power down 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 8 JEDEC PUB 95 Package style MS-012-AA Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 2 1.3 Absolute maximum ratings. 1/ Supply voltage (VDD to AGND) .......................................................................... 7 V Reference input voltage range ............................................................................ -0.3 V VDD +0.3 V Digital input voltage range .................................................................................. -0.3 V VDD +0.3 V Operating free-air temperature range (TA) ......................................................... Storage temperature range ................................................................................ Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ....................... Package thermal impedance (RJA) .................................................................. -55C to +125C 2/ -65C to +150C 2/ +260C 131C/W 1.4 Recommended operating conditions. 3/ Supply voltage (VDD): With VDD = 5 V ............................................................................................... 4.5 V minimum to 5.5 V maximum With VDD = 3 V ............................................................................................... 2.7 V minimum to 3.3 V maximum Power on reset ................................................................................................... 0.55 V minimum to 2 V maximum High level digital input voltage (VIH): With VDD = 2.7 V ............................................................................................ 2 V minimum With VDD = 5.5 V ............................................................................................ 2.4 V minimum Low level digital input voltage (VIL): With VDD = 2.7 V ............................................................................................ 0.6 V maximum With VDD = 5.5 V ............................................................................................ 1 V maximum Reference voltage, Vref to REF terminal: With VDD = 5 V ............................................................................................... AGND to VDD – 1.5 V 4/ With VDD = 3 V ............................................................................................... AGND to VDD – 1.5 V 4/ Load resistance (RL) .......................................................................................... 2 k minimum Load capacitance (CL) ........................................................................................ 100 pF maximum Clock frequency (fCLK) ....................................................................................... 20 MHz maximum Operating free air temperature range (TA) .......................................................... -55C to +125C 1/ 2/ 3/ 4/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Due to the x2 output buffer, a reference input voltage (VDD – 0.4 V) / 2 causes clipping of the transfer function. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions Temperature, TA Device type Limits Min Unit Max Power supply section Power supply current IDD Fast, no load, DAC latch = All ones, All inputs = AGND or VDD, 01 -55C to +125C 2.3 mA VDD = 2.7 V to 5.5 V Slow, no load, DAC latch = All ones, All inputs = AGND or VDD, 1 VDD = 2.7 V to 5.5 V Power down supply current Power supply rejection ration PSRR Zero scale 2/ -55C to +125C 01 1 typical A -55C to +125C 01 -65 typical dB Full scale 3/ -65 typical Static DAC specifications section Resolution -55C to +125C 01 12 bits Integral nonlinearity INL 4/ -55C to +125C 01 4 LSB Differential nonlinearity DNL 5/ -55C to +125C 01 1 LSB Zero scale error (offset error at zero scale) EZS 6/ -55C to +125C 01 12 mV Zero scale error temperature coefficient EZS(TC) 7/ -55C to +125C 01 Gain error EG VDD = 2.7 V – 5.5 V -55C to +125C 01 Gain error temperature coefficient EG(TC) 9/ -55C to +125C 01 RL = 10 k -55C to +125C 01 VO = 4.096 V, 2.048 V, -55C to +125C 01 8/ 3 typical 0.6 ppm / C % full scale V 1 typical ppm / C Output specifications section Output voltage range VO Output load regulation accuracy 0 VDD 0.4 V 0.29 % FS RL = 2 k to 10 k See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 5 TABLE I. Electrical performance characteristics – continued. 1/ Test Symbol Conditions Temperature, TA Device type Limits Unit Min Max 0 VDD – 1.5 Reference input section Input voltage range VI -55C to +125C 01 Input resistance RI -55C to +125C 01 10 typical M Input capacitance CI -55C to +125C 01 5 typical pF -55C to +125C 01 1.3 typical MHz 525 typical kHz Reference input bandwidth Fast, REF = 0.2 VPP + 1.024 V dc Slow, REF = 0.2 VPP + 1.024 V dc Reference feedthrough V 10/ REF = 1 VPP at 1 kHz + 1.024 V dc -55C to +125C 01 -80 typical dB 1 A Digital inputs section High level digital input current IIH VI = VDD -55C to +125C 01 Low level digital input current IIL VI = 0 V -55C to +125C 01 Input capacitance CI -55C to +125C 01 -55C to +125C 01 A -1 8 typical pF Analog output dynamic performance section Output settling time, full scale ts(FS) Fast, RL = 10 k, CL = 100 pF 11/ 10 Slow, RL = 10 k, CL = 100 pF 11/ Output settling time, code to code ts(CC) Fast, RL = 10 k, CL = 100 pF 12/ 01 -55C to +125C SR Fast, RL = 10 k, CL = 100 pF 13/ 01 -55C to +125C DIN = 0 to 1, FCLK = 100 kHz, 3 typical V/s 0.5 typical Slow, RL = 10 k, CL = 100 pF 13/ Glitch energy s 1 typical 2 typical Slow, RL = 10 k, CL = 100 pF 12/ Slew rate s 3 01 -55C to +125C 5 typical nV-s CS = VDD See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 6 TABLE I. Electrical performance characteristics – continued. 1/ Test Symbol Conditions Temperature, TA Device type Limits Min Unit Max Analog output dynamic performance section - continued Signal to noise ratio SNR fs = 102 kSPS, fout = 1 kHz, -55C to +125C 01 76 typical dB -55C to +125C 01 68 typical dB -55C to +125C 01 -68 typical dB -55C to +125C 01 72 typical dB RL = 10 k, CL = 100 pF Signal to noise + distortion SINAD Total harmonic distortion THD Spurious free dynamic range SFDR fs = 102 kSPS, fout = 1 kHz, RL = 10 k, CL = 100 pF fs = 102 kSPS, fout = 1 kHz, RL = 10 k, CL = 100 pF fs = 102 kSPS, fout = 1 kHz, RL = 10 k, CL = 100 pF Digital input timing requirements section Setup time, CS low before first negative SCLK edge tsu (CS CK) -55C to +125C 01 10 ns Setup time, 16 th negative SCLK edge tsu (C16 CS) -55C to +125C 01 10 ns SCLK pulse width high tWH -55C to +125C 01 25 ns SCLK pulse width low tWL -55C to +125C 01 25 ns Setup time, data ready before SCLK falling edge tsu(D) -55C to +125C 01 8 ns Hold time, data held valid after SCLK falling edge th(D) -55C to +125C 01 10 ns Hold time, CS high between cycles th(CSH) -55C to +125C 01 25 ns before CS rising edge VDD = 5 V 50 VDD = 3 V See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 7 TABLE I. Electrical performance characteristics – continued. 1/ 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [ EZS ( VDD max ) – ( EZS ( VDD min ) / VDD max ) ]. 3/ Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [ EG ( VDD max ) – ( EG ( VDD min ) / VDD max ) ]. 4/ The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale, excluding the effects of zero code and full scale errors. 5/ The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. 6/ Zero scale error is the deviation from zero voltage output when the digital input code is zero. 7/ Zero scale error temperature coefficient is given by: 6 EZS TC = [ EZS ( Tmax ) – EZS ( Tmin ) ] / 2Vref x 10 / ( Tmax – Tmin ). 8/ Gain error is the deviation from the ideal output ( 2Vref – 1 LSB ) with an output load of 10 k. 9/ Gain temperature coefficient is given by: EG TC = [EG ( Tmax ) – Eg( Tmin )] / 2Vref x 10 / ( Tmax – Tmin ). 10/ 6 Reference feedthrough is measured at the DAC output with an input code = 0x000. 11/ Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 12/ Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design 13/ Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full scale voltage. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 8 Case X FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 9 Case X Dimensions Inches Symbol Millimeters Min Max Min Max A --- 0.069 --- 1.75 A1 0.004 0.010 0.10 0.25 b 0.012 0.020 0.31 0.51 c 0.005 0.010 0.13 0.25 D 0.189 0.197 4.80 5.00 e 0.050 BSC 1.27 BSC E 0.150 0.157 3.80 4.00 E1 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 n 8 leads 8 leads NOTE: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs shall not exceed 0.006 inch (0.15 mm) per end. 3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed 0.017 inch (0.43 mm) per side. 4. Falls within reference to JEDEC MS-012-AA. FIGURE 1. Case outline. – continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol I/O/P Description 1 DIN I Digital serial data input. 2 SCLK I Digital serial clock input. 3 CS I Chip select. Digital input active low, used to enable/disable inputs. 4 OUTA O DAC A analog voltage output. 5 AGND P Ground. 6 REF I Analog reference voltage input. 7 OUTB O DAC B analog voltage output. 8 VDD P Positive power supply. FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 11 FIGURE 3. Block diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 12 FIGURE 4. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 13 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code V62/04646-01XE 01295 Package 2/ SOIC (D) Tape and reel Vendor part number Top side marking TLV5618AMDREP 5618ME 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ Package drawings, standard packaging quantities, thermal data, symbolization, and printed circuit board (PCB) design guidelines are available at www.ti.com/sc/package. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/04646 PAGE 14