Cypress Semiconductor Product Qualification Report QTP# 014405 VERSION 2.0 February 2004 Neuron Device Family CY7C53150* / CY7C53120* Neuron Chip Network Processor S4D-5 Technology Derivative, Fab 2 Echelon, LonWorks, LonTalk and Neuron are registered trademarks of Echelon Corporation CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Rene Rodgers Principal Reliability Engineer (408) 943-2732 Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 2 of 16 February 2004 PRODUCT QUALIFICATION HISTORY Qual Report Description of Qualification Purpose Date Comp 010702 New Technology S4AD-5 / New Product, Programmable Clock Generator, CY2414ZC, its product family and bond option. April 01 003605 Technology Derivative S4D-5 /New Neuron Devices, CY7C53150 and CY7C53120 Jul 01 014406 100K Endurance cycle qualification for Devices CY7C53120 and CY7C53150 Dec 01 014405 5 layer change to enhance functionality Dec 01 Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 3 of 16 February 2004 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: Qualify 5 layer change to CY7C53150* and CY7C53120* technology S4D-5, Fab 2 Marketing Part #: CY7C53150* and CY7C53120* Device Description: 5V, Industrial, available in 44/64-pin TQFP and 32-lead SOIC package Cypress Division: Cypress Semiconductor Corporation – Interface Product Division (IPD) WA Overall Die (or Mask) REV Level (pre-requisite for qualification): Rev. C What ID markings on 7C53150/7C53120A Die: FT3150/FT3120A TECHNOLOGY/FAB PROCESS DESCRIPTION S4D-5 Number of Metal Layers: 2 Metal Composition: Metal 1: 500A Ti/6,000A Al 0.5% Cu /1,200A TiW Metal 2: 500A Ti/8,000A Al 0.5% Cu/300A TiW Passivation Type and Materials: 3,000A TeOs / 6,000A Si3N4 Free Phosphorus contents in top glass layer(%): 0% Number of Transistors in Device: 450,000 Number of Gates in Device 168,000 Generic Process Technology/Design Rule ( -drawn): Single Poly, Double Metal, 0.35 m Gate Oxide Material/Thickness (MOS): SiO2 / 110A Name/Location of Die Fab (prime) Facility: Cypress Semiconductor - Round Rock, TX Die Fab Line ID/Wafer Process ID: Fab2, S4D-5 PACKAGE AVAILABILITY PACKAGE ASSEMBLY SITE FACILITY 32-lead SOIC CSPI-R 44, 64-pin TQFP ASE, Taiwan / CSPI-R Note: Package Qualification details upon request. Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 4 of 16 February 2004 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: Mold Compound Flammability Rating: S32 32-lead Plastic Small Outline IC (SOIC) NITTO MP8000CH V-O per UL94 Oxygen Rating Index: >28% Lead Frame Material: Copper Lead Finish, Composition / Thickness: Solder Plated, 85% Sn, 15%Pb Die Backside Preparation Method/Metallization: N/A Die Separation Method: Wafer Saw Die Attach Supplier: Dexter Die Attach Material: QMI 509 Die Attach Method: Epoxy Bond Diagram Designation: 10-04008 Wire Bond Method: Thermosonic Wire Material/Size: Au, 1.0mil Thermal Resistance Theta JA °C/W: 52.5°C/W Package Cross Section Yes/No: N/A Assembly Process Flow: 11-21000 Name/Location of Assembly (prime) facility: Cypress Philippines (CSPI-R) ELECTRICAL TEST / FINISH DESCRIPTION Test Location: Cypress Philippines (CSPI-R) Fault Coverage: 100% Note: Please contact a Cypress Representative for other packages availability Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 5 of 16 February 2004 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT Stress/Test Test Condition (Temp/Bias) High Temperature Operating Life Dynamic Operating Condition, Vcc Max=5.75V, 125°C Early Failure Rate Dynamic Operating Condition, Vcc Max=5.75V, 150°C High Temperature Operating Life Dynamic Operating Condition, Vcc Max=5.75V, 125°C Latent Failure Rate Dynamic Operating Condition, Vcc Max=5.75V, 150°C Result P/F P Dynamic Operating Condition, Vcc Max=3.8V, 150°C P Dynamic Operating Condition, Vcc Max=3.8V, 150°C High Temperature Steady State life 150°C, 3.63V, Vcc Max P Low Temperature Operating Life -30C, 4.3V, 8MHZ 130°C, 5.5V,85%RH Precondition: JESD22 Moisture Sensitivity Level 3 P High Accelerated Saturation Test (HAST) P 192 Hrs, 30C/60%RH+3IR-Reflow, 235°C+5, 0°C 130°C, 3.63V,85%RH Precondition: JESD22 Moisture Sensitivity Level 1 Temperature Cycle 168 Hrs, 85C/85%RH+3IR-Reflow, 235°C+5, 0°C 130°C, 5.5V,85%RH Precondition: JESD22 Moisture Sensitivity Level 3 P 192 Hrs, 30C/60%RH+3IR-Reflow, 235°C+5, 0°C 130°C, 3.63V,85%RH Precondition: JESD22 Moisture Sensitivity Level 1 168 Hrs, 85C/85%RH+3IR-Reflow, 235°C+5, 0°C Pressure Cooker 130°C, 5.5V,85%RH Precondition: JESD22 Moisture Sensitivity Level 3 P 192 Hrs, 30C/60%RH+3IR-Reflow, 235°C+5, 0°C 130°C, 3.63V,85%RH Precondition: JESD22 Moisture Sensitivity Level 1 168 Hrs, 85C/85%RH+3IR-Reflow, 235°C+5, 0°C Electrostatic Discharge 2,000V Human Body Model (ESD-HBM) MIL-STD-883, Method 3015.7 Electrostatic Discharge 500V Charge Device Model (ESD-CDM) Cypress Spec. 25-00020 Data Retention 150°C ± 5°C no bias P Age Bond Strength 200C, 4hrs P MIL-STD-883, Method 883-2011 P P Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 6 of 16 February 2004 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT (continuation) Stress/Test Test Condition (Temp/Bias) Result P/F Current Density Cypress Spec 22-00029 P SEM Analysis MIL-STD-883, Method 883-2018-2 P Endurance test MIL-STD-883-Method 1033 P Acoustic Microscopy, Level 1 & 3 Cypress Spec. 25-00104 P Latchup Sensitivity ± 300mA P In accordance with JEDEC 17. Cypress Spec. 01-00081 Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 7 of 16 February 2004 RELIABILITY FAILURE RATE SUMMARY Device Tested/ Device Hours # Fails Activation Energy Thermal3 A.F Failure Rate High Temperature Operating Life Early Failure Rate1 3033 Devices @125C 1 N/A N/A 329 PPM High Temperature Operating Life Early Failure Rate1 3999 Devices @150C 1 N/A N/A 250 PPM High Temperature Operating Life1,2 Long Term Failure Rate 685,075 DHRs 1 0 .7 170 9 FITs Stress/Test 1 2 3 Assuming an ambient temperature of 55°C and a junction temperature rise of 15°C. Chi-squared 60% estimations used to calculate the failure rate with only zero reject Thermal Acceleration Factor is calculated from the Arrhenius equation E 1 1 AF = exp A - k T 2 T1 where: EA =The Activation Energy of the defect mechanism. k = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 8 of 16 February 2004 Reliability Test Data QTP #: Device Fab Lot # 010702 Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: ACOUSTIC-MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 15 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 3.8V, Vcc Max CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 48 1005 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 48 1004 1 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 48 1005 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 3.8V, Vcc Max CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 500 120 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 500 120 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 80 120 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 500 120 0 STRESS: AGE BOND STRENGTH CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 15 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 15 0 TAIWN-T COMP 3 0 TAIWN-T 500 48 0 STRESS: DYNAMIC LATCH-UP TESTING, 11.5V CY2414ZC (7C841400A) 2101502 610106170/1/2 STRESS: LOW TEMPERATURE OPERATING LIFE, -30C, 4.3V CY2414ZC (7C841400A) 2101502 610106170/1/2 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 9 0 NON VISUAL Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 9 of 16 February 2004 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 010702 Assy Loc Duration Samp Rej Failure Mechanism STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,000V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 9 0 CY2414ZC (7C841400A) 2103764 610106177 TAIWN-T COMP 10 0 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, ±300mA CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T COMP 3 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T COMP 3 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T COMP 3 0 STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 3.63V), PRE COND 168 HR 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 128 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 256 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 128 48 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 128 48 0 STRESS: HIGH TEMP STEADY STATE LIFE TEST, 150C, 3.63V CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 80 80 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 80 0 610106170/1/2 TAIWN-T COMP 45 0 STRESS: ENDURANCE TEST CY2414ZC (7C841400A) 2101502 STRESS: DATA RETENTION, PLASTIC, 150C CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 552 80 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 552 80 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 168 80 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 552 80 0 STRESS: PRESSURE COOKER TEST, 121C, 100%RH), PRE COND 168 HR 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 168 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 168 49 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 168 51 0 Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 10 of 16 February 2004 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 010702 Assy Loc Duration Samp Rej STRESS: TC COND. C -65C TO 150C, PRECONDITION 168 HRS 85C/85%RH, MSL1 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2101502 610106170/1/2 TAIWN-T 1000 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 500 50 0 CY2414ZC (7C841400A) 2052404 610106173/4/5 TAIWN-T 1000 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 300 50 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T 500 50 0 1000 49 0 CY2414ZC (7C841400A) 2103764 610106176/7/8 TAIWN-T Failure Mechanism Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 11 of 16 February 2004 Reliability Test Data QTP #: Device Fab Lot # 003605 Assy Lot # Assy Loc Duration Samp Rej CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G COMP 15 0 CY7C53150-AI(7C53150B) 2110601 610115306 TAIWN-G COMP 15 0 CY7C53150-AI (7C53150B) 2113874 340100160/1 TAIWN-G COMP 15 0 Failure Mechanism STRESS: ACOUSTIC-MSL3 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 5.75V, Vcc Max CY7C53120-SI (7C53120B) 2110601 610119962 CSPI-R 80 394 0 CY7C53120-SI (7C53120B) 2113874 610119334 CSPI-R 80 591 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 5.75V, Vcc Max CY7C53120-SI (7C53120B) 2110601 610119962 CSPI-R 96 609 1 CY7C53120-SI (7C53120B) 2113874 610119334/7707 CSPI-R 96 414 0 MISSING LICON STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 5.75V, Vcc Max CY7C53120-SI (7C53120B) 2110601 610119962 CSPI-R 197 393 0 CY7C53120-SI (7C53120B) 2110601 610119962 CSPI-R 500 393 0 CY7C53120-SI (7C53120B) 2113874 610119334 CSPI-R 197 400 1 CY7C53120-SI (7C53120B) 2113874 610119334 CSPI-R 500 399 0 COMP 9 0 COMP 9 0 UNKNOWN STRESS: ESD-CHARGE DEVICE MODEL, 500V CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,000V CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G STRESS: STATIC LATCH-UP TESTING, 125C, 12V, ±300mA CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G COMP 3 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G COMP 3 0 STRESS: HI-ACCEL SATURATION TEST, 130C, 85%RH, 5.5V, PRE COND 192 Hrs., 30ºC/60%RH, MSL3 CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G 128 48 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 128 46 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 256 46 0 TAIWN-G 1000 48 0 STRESS: ENDURANCE TEST, -25C/+85 CY7C53150-AI (7C53150B) 2110601 610115306 Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 12 of 16 February 2004 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 003605 Assy Loc Duration Samp Rej STRESS: DATA RETENTION, PLASTIC, 150C CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 500 266 0 CY7C53150-AI (7C53150B) 2113874 340100160/1 TAIWN-G 500 266 0 STRESS: PRESSURE COOKER TES, 121C, 100%RH), PRE COND 192 HR 30ºC/60%RH, MSL3 CY7C53150-AI (7C53150A) 2104858 610109389/90 TAIWN-G 168 50 0 CY7C53150-AI (7C53150B) 2110601 610115306 TAIWN-G 168 48 0 Failure Mechanism Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 13 of 16 February 2004 Reliability Test Data QTP #: Device 014406 Fab Lot # Assy Lot # Assy Loc CY7C53120*-SI (7C531201B) 2118274 610120676 CSPI-R CY7C53120*-SI (7C531201B) 2138780 610139817 CSPI-R Duration Samp Rej COMP 50 0 COMP 50 0 STRESS: ENDURANCE TEST *Note: For Data Retention after Endurance Cycle, please see next page. Failure Mechanism Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 14 of 16 February 2004 FLASH MEMORY ENDURANCE AND DATA RETENTION Units1 cycled 90000 times or less have an expected data retention lifetime equal to or greater than 20 years2. For units cycled 100000 times or more, the data retention cummulative failure rate over time is defined below: Lifetime Cummulative Data 1 (Years ) Retention Failure Rate After 100000 Cycles 0.0 2.6 5.2 7.8 10.4 13.0 15.6 18.2 20.8 23.4 26.0 28.6 31.2 33.7 36.3 38.9 41.5 44.1 46.7 49.3 51.9 54.5 57.1 59.7 62.3 64.9 2.25% 2.84% 3.24% 3.54% 3.80% 4.02% 4.22% 4.39% 4.55% 4.69% 4.83% 4.96% 5.07% 5.18% 5.29% 5.39% 5.49% 5.58% 5.66% 5.75% 5.83% 5.91% 5.98% 6.05% 6.13% Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* 7.0% QTP# 014405, V, 2.0 Page 15 of 16 February 2004 Cummulative Data Retention Failure After 100K Cycles Failure Rate 6.0% 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% 0 10 20 30 40 Lifetime (Years) (1) Test sample size = 48 units. No rejects found on units with 90000 cycles or below. (2) Calculation assumptions are: Ea=1.1eV, Tuse =70C, Tstress=150C, delta T=0C, AF = 1137. 50 60 70 Cypress Semiconductor Neuron Chip Network Processor, S4D-5, Fab 2 Device: CY7C53150* / CY7C53120* QTP# 014405, V, 2.0 Page 16 of 16 February 2004 Reliability Test Data QTP #: Device Fab Lot # Assy Lot # 014405 Assy Loc Duration Samp Rej STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 125C, 5.75V, Vcc Max CY7C53120*-SI (7C531201B) 2138780 610139817 CSPI-R 96 2010 0 STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 125C, 5.75V, Vcc Max CY7C53120*-SI (7C531201B) 2138780 610139817 CSPI-R 168 2009 0 CSPI-R COMP 9 0 STRESS: ESD-CHARGE DEVICE MODEL, 500V CY7C53120*-SI (7C531201B) 2138780 610139165 STRESS: ESD-HUMAN BODY CIRCUIT PER MIL STD 883, METHOD 3015, 2,000V CY7C53120*-SI (7C531201B) 2138780 610139165 CSPI-R COMP 9 0 CSPI-R COMP 3 0 STRESS: STATIC LATCH-UP TESTING, 125C, 10V, ±300mA CY7C53120*-SI (7C531201B) 2138780 610139165 Failure Mechanism