PD- 91822C
SMPS MOSFET
IRFPS37N50A
HEXFET® Power MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptable Power Supply
l High Speed Power Switching
Benefits
Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss Specified (See AN
1001)
VDSS
500V
RDS(on) max
ID
0.13Ω
36A
l
SUPER-247
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
36
23
144
446
3.6
± 30
3.5
-55 to + 150
Units
A
W
W/°C
V
V/ns
°C
300 (1.6mm from case )
Typical SMPS Topologies
l
l
Full Bridge Converters
Power Factor Correction Boost
Notes
through
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are on page 8
1
12/14/99
IRFPS37N50A
Static @ TJ = 25°C (unless otherwise specified)
V(BR)DSS
RDS(on)
VGS(th)
Parameter
Drain-to-Source Breakdown Voltage
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min.
500
–––
2.0
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
0.13
Ω
VGS = 10V, I D = 22A
4.0
V
VDS = VGS, ID = 250µA
25
VDS = 500V, VGS = 0V
µA
250
VDS = 400V, VGS = 0V, TJ = 150°C
100
VGS = 30V
nA
-100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
20
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
23
98
52
80
5579
810
36
7905
221
400
Max. Units
Conditions
–––
S
V DS = 50V, ID = 22A
180
ID = 36A
46
nC
VDS = 400V
71
VGS = 10V, See Fig. 6 and 13
–––
VDD = 250V
–––
ID = 36A
ns
–––
RG = 2.15Ω
–––
R D = 7.0Ω,See Fig. 10
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 400V
Avalanche Characteristics
Parameter
EAS
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
1260
36
44
mJ
A
mJ
Typ.
Max.
Units
–––
0.24
–––
0.28
–––
40
°C/W
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Diode Characteristics
IS
ISM
VSD
trr
Qrr
ton
2
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
36
––– –––
showing the
A
G
integral reverse
––– ––– 144
S
p-n junction diode.
––– ––– 1.5
V
TJ = 25°C, IS = 36A, VGS = 0V
––– 570 860
ns
TJ = 25°C, IF = 36A
––– 8.6
13
µC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFPS37N50A
1000
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
10
4.5V
1
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
10
4.5V
100
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
1000
100
TJ = 150 ° C
TJ = 25 ° C
10
V DS = 50V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
VGS , Gate-to-Source Voltage (V)
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
1
4.0
20µs PULSE WIDTH
TJ = 150 °C
1
0.1
9.0
ID = 36A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFPS37N50A
20
V G S = 0V,
f = 1M Hz
C is s = C g s + C g d, C d sSHORTED
C rs s = C g d
C o ss = C d s + C g d
VGS , Gate-to-Source Voltage (V)
C , C apacitance (pF )
100000
10000
C iss
1000
C oss
100
C rss
10
10
100
VDS = 400V
VDS = 250V
VDS = 100V
16
12
8
4
A
1
ID = 36A
FOR TEST CIRCUIT
SEE FIGURE 13
0
1000
0
40
80
120
160
200
Q G , Total Gate Charge (nC)
V D S , D rain-to-Source Volta ge (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
I D , Drain Current (A)
100
10
TJ = 25 ° C
100us
10
1ms
1
0.1
0.2
V GS = 0 V
0.4
0.6
0.8
1.0
1.2
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10us
100
TJ = 150 ° C
1.4
1
10ms
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFPS37N50A
40
RD
VDS
I D , Drain Current (A)
VGS
D.U.T.
RG
30
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
20
Fig 10a. Switching Time Test Circuit
10
VDS
90%
0
25
50
75
100
TC , Case Temperature
125
150
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.1
0.01
0.20
0.10
0.05
0.02
0.01
P DM
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFPS37N50A
EAS , Single Pulse Avalanche Energy (mJ)
3000
1 5V
TOP
2500
D R IV E R
L
VDS
BOTTOM
ID
16A
23A
36A
2000
D .U .T
RG
+
V
- DD
IA S
20V
0 .0 1 Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp
A
1500
1000
500
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
IAS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
580
QGD
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
V D Sa v , Av alanche V oltage (V)
QGS
560
540
520
.3µF
D.U.T.
+
V
- DS
A
10
20
30
40
I av , Av alanche Current (A)
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
500
0
VGS
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
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IRFPS37N50A
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
D=
Period
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-channel HEXFET® Power MOSFETs
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IRFPS37N50A
Case Outline and Dimensions — Super-247
Dimensions are shown in millimeters
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 1.94mH
RG = 25Ω, IAS = 36A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
ISD ≤ 36A, di/dt ≤ 145A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
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Data and specifications subject to change without notice. 12/99
8
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