IRF IRF6602

PD-94363C
IRF6602/IRF6602TR1
HEXFET® Power MOSFET
l Application Specific MOSFETs
l Ideal for CPU Core DC-DC Converters
VDSS
RDS(on) max
Qg
20V
13mΩ@VGS = 10V
19mΩ@VGS = 4.5V
12nC
l Low Conduction Losses
l Low Switching Losses
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface Mount Techniques
MQ
DirectFET™ ISOMETRIC
Applicable DirectFET Package/Layout Pad (see p.9, 10 for details)
SQ
SX
MQ
ST
MX
MT
Description
The IRF6602 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to
achieve the lowest on-state resistance charge product in a package that has the footprint of an SO-8 and only 0.7 mm profile.
The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment
and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the
manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in
power systems, IMPROVING previous best thermal resistance by 80%.
The IRF6602 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction
and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the
latest generation of processors operating at higher frequencies. The IRF6602 has been optimized for parameters that are
critical in synchronous buck converters including Rds(on) and gate charge to minimize losses in the control FET socket.
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
20
V
VGS
±20
ID @ TC = 25°C
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
11
ID @ TA = 70°C
8.9
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
PD @TA = 25°C
Power Dissipation
2.3
PD @TA = 70°C
Power Dissipation
PD @TC = 25°C
Power Dissipation
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
g
g
48
c
A
89
W
1.5
42
0.018
-40 to + 150
W/°C
°C
Thermal Resistance
Parameter
RθJA
Junction-to-Ambient
f
g
h
RθJA
Junction-to-Ambient
RθJA
Junction-to-Ambient
RθJC
Junction-to-Case
RθJ-PCB
Junction-to-PCB Mounted
i
Typ.
Max.
–––
55
12.5
–––
20
–––
–––
3.0
1.0
–––
Units
°C/W
Notes  through ‡ are on page 11
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1
3/1/04
IRF6602/IRF6602TR1
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS
∆ΒVDSS/∆TJ
Min. Typ. Max. Units
20
–––
–––
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
–––
–––
22
10
–––
13
mV/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 11A
VGS(th)
∆VGS(th)
Gate Threshold Voltage
–––
1.0
14
2.0
19
2.3
VGS = 4.5V, ID = 8.8A
VDS = VGS, ID = 250µA
Gate Threshold Voltage Coefficient
–––
–––
-4.4
–––
–––
100
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
20
125
µA
VDS = 16V, VGS = 0V
VDS = 16V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
–––
–––
–––
–––
200
-200
nA
VGS = 20V
VGS = -20V
gfs
Qg
Forward Transconductance
Total Gate Charge
20
–––
–––
12
–––
18
S
VDS = 10V, ID = 8.8A
Qgs1
Qgs2
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
–––
–––
3.5
1.3
–––
–––
nC
VDS = 10V
VGS = 4.5V
Qgd
Qgodr
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
4.2
3.0
–––
–––
Output Charge
–––
–––
5.5
19
–––
–––
RG
td(on)
Gate Resistance
Turn-On Delay Time
–––
–––
2.8
33
4.2
–––
tr
td(off)
Rise Time
Turn-Off Delay Time
–––
–––
6.0
14
–––
–––
tf
Ciss
Fall Time
Input Capacitance
–––
–––
12
1420
–––
–––
Coss
Crss
Output Capacitance
Reverse Transfer Capacitance
–––
–––
960
100
–––
–––
RDS(on)
Qsw
Qoss
V
Conditions
Drain-to-Source Breakdown Voltage
VGS = 0V, ID = 250µA
e
e
V
VDS = 20V, VGS = 0V
ID = 8.8A
See Fig. 16
nC
Ω
VDS = 16V, VGS = 0V
VDD = 15V, VGS = 4.5V
ns
e
ID = 8.8A
Clamped Inductive Load
VGS = 0V
pF
VDS = 10V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
IAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
–––
–––
Max.
97
8.8
Units
mJ
A
–––
4.2
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
48
ISM
(Body Diode)
Pulsed Source Current
–––
–––
380
VSD
(Body Diode)
Diode Forward Voltage
–––
0.83
1.2
V
trr
Reverse Recovery Time
–––
42
62
ns
Qrr
Reverse Recovery Charge
–––
51
77
nC
2
c
Conditions
MOSFET symbol
A
D
showing the
integral reverse
G
S
p-n junction diode.
TJ = 25°C, IS = 8.8A, VGS = 0V
e
TJ = 25°C, IF = 8.8A
di/dt = 100A/µs
e
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IRF6602/IRF6602TR1
1000
1000
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
VGS
10V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
100
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
2.7V
100
2.7V
10
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
1
1
0.1
1
10
100
0.1
1
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
100.00
2.0
T J = 25°C
10.00
VDS = 15V
20µs PULSE WIDTH
2.5
3.0
3.5
4.0
4.5
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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5.0
I D = 11A
1.5
(Normalized)
R DS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (Α)
T J = 150°C
2.0
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1.00
10
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
TJ , Junction Temperature
80
100
120
140
160
( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF6602/IRF6602TR1
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance(pF)
10000
1000
Ciss
Coss
100
Crss
10
6.0
ID= 8.8A
VGS , Gate-to-Source Voltage (V)
100000
VDS= 16V
VDS= 10V
5.0
4.0
3.0
2.0
1.0
0.0
1
10
100
0
5
VDS, Drain-to-Source Voltage (V)
15
Q G Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
1000
ID, Drain-to-Source Current (A)
I SD , Reverse Drain Current (A)
10
TJ = 150 ° C
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
10
T J= 25 ° C
1
100µsec
10
1msec
10msec
1
Tc = 25°C
Tj = 150°C
Single Pulse
V GS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
V SD,Source-to-Drain Voltage (V)
1.4
0.1
0
1
10
100
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
Fig 8. Maximum Safe Operating
Area
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IRF6602/IRF6602TR1
3.0
VGS(th) Gate threshold Voltage (V)
12
I D , Drain Current (A)
9
6
3
2.5
2.0
ID = 250µA
1.5
1.0
0.5
0.0
0
25
50
75
100
125
150
-75
-50
-25
0
25
50
75
100
125
150
T J , Temperature ( °C )
TA, Ambient Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Ambient Temperature
Fig 10. Threshold Voltage Vs. Temperature
(Z thJA )
100
D = 0.50
0.20
10
Thermal Response
0.10
0.05
P DM
0.02
1
t1
0.01
t2
Notes:
SINGLE PULSE
(THERMAL RESPONSE)
1. Duty factor D =
2. Peak T
0.1
0.00001
0.0001
0.001
0.01
0.1
t1/ t 2
J = P DM x Z thJA
1
+T A
10
100
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF6602/IRF6602TR1
15V
250
ID
3.9A
7.0A
8.8A
TOP
DRIVER
D.U.T
RG
+
V
- DD
IAS
VGS
20V
200
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
L
VDS
BOTTOM
150
100
50
0
25
50
75
100
125
150
( ° C)
Starting Tj, Junction Temperature
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
LD
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
Fig 14a. Switching Time Test Circuit
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
10%
IG
ID
VGS
Current Sampling Resistors
td(on)
Fig 13. Gate Charge Test Circuit
6
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
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IRF6602/IRF6602TR1
D.U.T
Driver Gate Drive
+
ƒ
+
-
-
„
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
*

•
•
•
•
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
RG
Period
P.W.
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRF6602/IRF6602TR1
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
Q

+  oss × Vin × f + (Qrr × Vin × f )
 2

This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )

Qgs2
Qgd
 

+I ×
× Vin × f  +  I ×
× Vin × f 
ig
ig

 

+ (Qg × Vg × f )
+
 Qoss
× Vin × f 
 2

This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRF6602/IRF6602TR1
DirectFET™ Outline Dimension, MQ Outline
(Medium Size Can, Q-Designation)
Please see DirectFET application note AN-1035 for all details regarding the assembly of
DirectFET. This includes all recommendations for stencil and substrate designs.
NOTE: CONTROLLING
DIMENSIONS ARE IN MM
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DIMENSIONS
IMPERIAL
METRIC
MAX MIN
CODE MIN
MAX
6.35 0.246
A
6.25
0.250
5.05 0.189
B
4.80
0.199
3.95 0.152
C
3.85
0.156
0.45 0.014
D
0.35
0.018
0.72 0.027
E
0.68
0.028
0.72 0.027
F
0.68
0.028
0.73 0.027
G
0.69
0.029
0.61 0.022
H
0.57
0.024
0.27 0.009
J
0.23
0.011
1.70 0.062
K
1.57
0.067
3.12 0.116
L
2.95
0.123
0.70 0.023
M
0.59
0.028
0.08 0.001
N
0.03
0.003
9
IRF6602/IRF6602TR1
DirectFET™ Board Footprint, MQ Outline
(Medium Size Can, Q-Designation)
Please see DirectFET application note AN-1035 for all details regarding the assembly of
DirectFET. This includes all recommendations for stencil and substrate designs.
DirectFET™ Tape and Reel Dimension
(Showing Component Orientation)
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6602). For 1000 parts on 7" reel,
order IRF6602TR1
REEL DIMENSIONS
STANDARD OPTION (QTY 4800)
TR1 OPTION (QTY 1000)
IMPERIAL
METRIC
METRIC
IMPERIAL
MAX
MIN
CODE
MIN
MAX
MAX
MAX
MIN
MIN
N.C
6.9
A
12.992
N.C
330.0
177.77 N.C
N.C
0.75
0.795
N.C
B
20.2
19.06
N.C
N.C
N.C
0.50
0.53
C
0.504
13.2
12.8
12.8
13.5
0.520
0.059
D
0.059
N.C
1.5
1.5
N.C
N.C
N.C
2.31
E
3.937
N.C
100.0
58.72
N.C
N.C
N.C
N.C
F
N.C
0.53
N.C
N.C
0.724
18.4
13.50
0.47
G
0.488
N.C
12.4
11.9
14.4
12.01
0.567
H
0.47
0.469
N.C
11.9
11.9
0.606
15.4
12.01
10
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IRF6602/IRF6602TR1
DirectFET™ Part Marking
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 2.5mH
RG = 25Ω, IAS = 8.8A. (See Figure 14).
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ Surface mounted on 1 in. square Cu board.
… Used double sided cooling , mounting pad.
† Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
‡ TC measured with thermal couple mounted to top (Drain) of
part.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/04
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11