PD - 97115A
IRFB4310ZPbF
IRFS4310ZPbF
IRFSL4310ZPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
D
G
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
100V
4.8m:
6.0m:
127A c
ID (Package Limited)
75A
D
D
D
G
D
S
G
D
S
G
D2Pak
IRFS4310ZPbF
TO-220AB
IRFB4310ZPbF
D
S
TO-262
IRFSL4310ZPbF
G
D
S
G ate
Drain
Source
Absolute Maximum Ratings
Max.
Units
ID @ TC = 25°C
Symbol
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Parameter
127c
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
90c
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
75
IDM
Pulsed Drain Current d
560
PD @TC = 25°C
Maximum Power Dissipation
250
W
W/°C
V
Linear Derating Factor
1.7
VGS
Gate-to-Source Voltage
± 20
dv/dt
TJ
Peak Diode Recovery f
18
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
V/ns
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy e
IAR
Avalanche Currentc
EAR
Repetitive Avalanche Energy g
130
mJ
See Fig. 14, 15, 22a, 22b,
A
mJ
Thermal Resistance
Typ.
Max.
RθJC
Symbol
Junction-to-Case k
–––
0.6
RθCS
Case-to-Sink, Flat Greased Surface , TO-220
0.50
–––
RθJA
Junction-to-Ambient, TO-220 k
–––
62
RθJA
Junction-to-Ambient (PCB Mount) , D Pak jk
–––
40
www.irf.com
Parameter
2
Units
°C/W
1
4/27/07
IRFB/S/SL4310ZPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
–––
–––
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient
–––
0.11
–––
V/°C Reference to 25°C, ID = 5mAd
RDS(on)
Static Drain-to-Source On-Resistance
–––
4.8
6.0
mΩ VGS = 10V, ID = 75A g
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
IDSS
Drain-to-Source Leakage Current
μA
RG
–––
–––
20
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
0.7
–––
V
Conditions
100
IGSS
Drain-to-Source Breakdown Voltage
VGS = 0V, ID = 250μA
VDS = VGS, ID = 150μA
VDS = 100V, VGS = 0V
VDS = 80V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
gfs
Forward Transconductance
150
–––
–––
S
nC
Conditions
VDS = 50V, ID = 75A
Qg
Total Gate Charge
–––
120
170
Qgs
Gate-to-Source Charge
–––
29
–––
VDS =50V
Qgd
Gate-to-Drain ("Miller") Charge
–––
35
Qsync
Total Gate Charge Sync. (Qg - Qgd)
–––
85
–––
ID = 75A, VDS =0V, VGS = 10V
ID = 75A
VGS = 10V g
td(on)
Turn-On Delay Time
–––
20
–––
tr
Rise Time
–––
60
–––
ID = 75A
td(off)
Turn-Off Delay Time
–––
55
–––
RG = 2.7Ω
tf
Fall Time
–––
57
–––
VGS = 10V g
Ciss
Input Capacitance
–––
6860
–––
Coss
Output Capacitance
–––
490
–––
VDS = 50V
Crss
Reverse Transfer Capacitance
–––
220
–––
ƒ = 1.0MHz, See Fig. 5
Coss eff. (ER) Effective Output Capacitance (Energy Related) –––
Coss eff. (TR) Effective Output Capacitance (Time Related)h –––
570
–––
VGS = 0V, VDS = 0V to 80V i, See Fig. 11
920
–––
VGS = 0V, VDS = 0V to 80V h
ns
pF
VDD = 65V
VGS = 0V
Diode Characteristics
Symbol
Parameter
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
(Body Diode)d
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Min. Typ. Max. Units
–––
–––
Reverse Recovery Charge
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
–––
–––
–––
–––
40
–––
49
–––
58
–––
89
–––
2.5
560
1.3
A
MOSFET symbol
A
showing the
integral reverse
V
p-n junction diode.
TJ = 25°C, IS = 75A, VGS = 0V g
ns
TJ = 25°C
VR = 85V,
TJ = 125°C
IF = 75A
di/dt = 100A/μs g
nC
TJ = 25°C
D
G
S
TJ = 125°C
–––
A
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.047mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 75A, di/dt ≤ 600A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
––– 127c
Conditions
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
www.irf.com
IRFB/S/SL4310ZPbF
1000
1000
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
100
BOTTOM
10
4.5V
≤ 60μs PULSE WIDTH
Tj = 25°C
1
BOTTOM
100
4.5V
≤ 60μs PULSE WIDTH
Tj = 175°C
10
0.1
1
10
100
0.1
VDS , Drain-to-Source Voltage (V)
10
100
Fig 2. Typical Output Characteristics
2.5
1000
100
10
TJ = 25°C
1
VDS = 50V
≤ 60μs PULSE WIDTH
0.1
3.0
4.0
5.0
6.0
VGS = 10V
2.0
(Normalized)
TJ = 175°C
2.0
ID = 75A
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current(Α)
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
7.0
1.5
1.0
0.5
8.0
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
12000
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
8000
Ciss
6000
4000
Coss
2000
Crss
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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ID= 75A
VDS = 80V
16
VDS= 50V
VDS= 20V
12
8
4
0
0
1
20 40 60 80 100 120 140 160 180
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
10000
0
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
0
40
80
120
160
200
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB/S/SL4310ZPbF
10000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
1000
TJ = 175°C
100
TJ = 25°C
10
1
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
1msec
100
10msec
10
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.1
2.0
LIMITED BY PACKAGE
ID, Drain Current (A)
120
100
80
60
40
20
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage
140
50
10
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
1
VDS , Drain-toSource Voltage (V)
VSD, Source-to-Drain Voltage (V)
130
ID = 5mA
120
110
100
90
-60 -40 -20
TC, Case Temperature (°C)
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
3.0
EAS, Single Pulse Avalanche Energy (mJ)
600
2.5
2.0
Energy (μJ)
DC
0.1
0.1
1.5
1.0
0.5
0.0
ID
11A
19A
BOTTOM 75A
TOP
500
400
300
200
100
0
0
20
40
60
80
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100μsec
100
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRFB/S/SL4310ZPbF
1
Thermal Response ( Z thJC )
D = 0.50
0.20
0.10
0.1
0.05
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
R3
R3
R4
R4
τC
τ2
τ1
τ2
τ3
τ4
τ3
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
τ4
τ
Ri (°C/W)
0.018756
0.159425
0.320725
0.101282
τι (sec)
0.000373
0.000734
0.005665
0.115865
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
0.01
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
140
120
EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 75A
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB/S/SL4310ZPbF
24
ID = 1.0A
ID = 1.0mA
ID = 250μA
ID = 150μA
4.0
3.5
20
16
IRRM - (A)
VGS(th) Gate threshold Voltage (V)
4.5
3.0
2.5
12
8
2.0
IF = 30A
VR = 85V
4
1.5
1.0
TJ = 125°C
TJ = 25°C
0
-75
-50 -25
0
25
50
75
100 125 150 175
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
Fig 16. Threshold Voltage Vs. Temperature
Fig. 17 - Typical Recovery Current vs. dif/dt
24
600
20
500
16
400
QRR - (nC)
IRRM - (A)
TJ , Temperature ( °C )
12
8
4
0
300
200
IF = 45A
VR = 85V
IF = 30A
VR = 85V
100
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
dif / dt - (A / μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
600
500
QRR - (nC)
400
300
200
100
0
IF = 45A
VR = 85V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB/S/SL4310ZPbF
Driver Gate Drive
D.U.T
+
-
-
*
RG
•
•
•
•
D.U.T. ISD Waveform
+
VDD
**
P.W.
Period
***
Reverse
Recovery
Current
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V(BR)DSS
15V
D.U.T
RG
VGS
20V
DRIVER
L
VDS
tp
+
V
- DD
IAS
tp
A
0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
-VDD
10%
VGS
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
td(off)
tr
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
20K
1K
VCC
S
Vgs(th)
Qgodr
Fig 24a. Gate Charge Test Circuit
www.irf.com
Qgd
Qgs2 Qgs1
Fig 24b. Gate Charge Waveform
7
IRFB/S/SL4310ZPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
AS S EMBLED ON WW 19, 2000
IN T HE AS S EMBLY LINE "C"
Note: "P" in ass embly line pos ition
indicates "Lead - Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
8
www.irf.com
IRFB/S/SL4310ZPbF
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
AS S EMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
INT ERNATIONAL
RECTIFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNATIONAL
RECTIFIER
LOGO
AS S EMBLY
LOT CODE
www.irf.com
PART NUMBER
DAT E CODE
P = DES IGNATES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S ITE CODE
9
IRFB/S/SL4310ZPbF
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
F530S
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
AS S EMBLY
LOT CODE
T HIS IS AN IRF530S WIT H
LOT CODE 8024
For GB Production
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
LOT CODE
10
PART NUMBER
F530S
DAT E CODE
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IRFB/S/SL4310ZPbF
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/07
www.irf.com
11