INTEGRATED CIRCUITS PCK2010 CK98 (100/133MHz) Spread Spectrum System Clock Generator Preliminary specification 1999 Mar 01 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator FEATURES PCK2010 PIN CONFIGURATION • Mixed 2.5V and 3.3V operation • Four CPU clocks at 2.5V • Eight PCI clocks at 3.3V, one free-running VSS 1 56 VDD25V REF0 2 55 APIC2 REF1 3 54 APIC1 VDD3V 4 53 APIC0 XTAL_IN 5 52 VSS XTAL_OUT 6 51 VDD25V VSS 7 50 CPUDIV2_1 PCICLK_F 8 49 CPUDIV2_0 PCICLK1 9 48 VSS (synchronous with CPU clocks) • Four 3.3V fixed clocks @ 66MHz • Two 2.5V CPUDIV2 clocks @ CPU clock frequency • Three 2.5V IOAPIC clocks @ 16.67 MHz • One 3.3V 48MHz USB clock • Two 3.3V reference clocks @ 14.318 MHz • Reference 14.31818 MHz Xtal oscillator input • 133 MHz or 100 MHz operation • Power management control input pins • LOW CPU clock jitter ≤ 250 ps cycle-cycle • LOW skew outputs • 0.0ns – 1.5ns CPU - 3V66 delay • 1.5ns – 4.0ns 3V66 - PCI delay • 1.5ns – 4.0 ns CPU - IOAPIC delay • Available in 56-pin SSOP package • ±0.5% center spread spectrum capability via select pins; –0.5% VDD3V 10 47 VDD25V PCICLK2 11 46 CPUCLK3 PCICLK3 12 45 CPUCLK2 VSS 13 44 VSS PCICLK4 14 43 VDD25V PCICLK5 15 42 CPUCLK1 VDD3V 16 41 CPUCLK0 PCICLK6 17 40 VSS PCICLK7 18 39 VDD3V VSS 19 38 VSS VSS 20 37 PCISTOP 3V66_0 21 36 CPUSTOP 3V66_1 22 35 PWRDWN VDD3V 23 34 SPREAD VSS 24 33 SEL1 3V66_2 25 32 SEL0 DESCRIPTION 3V66_3 26 31 VDD3V The PCK2010 is a clock synthesizer/driver chip for a PentiumII and other similar processors. VDD3V 27 30 48MHz SEL133/100 28 29 VSS down spread spectrum capability via select pins The PCK2010 has four CPU clock outputs at 2.5V, two CPUDIV2 clock outputs running at CPU clock frequency (66MHz or 50MHz depending on the state of SEL133/100) and four 3V66 clocks running at 66MHz. There are eight PCI clock outputs running at 33MHz. One of the PCI clock outputs is free-running. Additionally, the part has three 2.5V IOAPIC clock outputs at 16.67MHz and two 3.3V reference clock outputs at 14.318MHz. All clock outputs meet Intel’s drive strength, rise/fall time, jitter, accuracy, and skew requirements. SW00352 The part possesses dedicated power-down, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on-chip and ensure glitch-free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs and 3V66 clock outputs are driven LOW. When the PCISTOP input is asserted, the PCI clock outputs are driven LOW. Finally, when the PWRDWN input pin is asserted, the internal reference oscillator and PLLs are shut down, and all outputs are driven LOW. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER 56-Pin Plastic SSOP 0°C to +70°C PCK2010 DL PCK2010 DL SOT371-1 Intel and Pentium are registered trademarks of Intel Corporation. 1999 Mar 01 2 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 2,3 REF [0–1] 3.3V 14.318 MHz clock output 5 XTAL_IN 14.318 MHz crystal input 6 XTAL_OUT 14.318 MHz crystal output 3.3V free running PCI clock 8 PCICLK_F 9, 11, 12, 14, 15, 17, 18 PCICLK [1–7] 21, 22, 25, 26 3V66 [0–3] 28 SEL133/100 30 48MHz 32, 33 SEL [0–1] Logic select pins. TTL levels. 34 SPREAD 3.3V LVTTL input. Enables spread spectrum mode when held LOW. 35 PWRDWN 3.3V LVTTL input. Device enters powerdown mode when held LOW. 36 CPUSTOP 3.3V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW. CPUDIV_2 output remains on all the time. 37 PCISTOP 3.3V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW. 41, 42, 45, 46 CPUCLK [0–3] 2.5V CPU output. 133MHz or 100MHz depending on state of input pin SEL133/100. 49, 50 CPUDIV_2 [0–1] 2.5V output running at 1/2 CPU clock frequency. 66MHz or 50MHz depending on state of input pin SEL133/100. 53, 54, 55 IOAPIC [0–2] 2.5V clock outputs running divide synchronous with the CPU clock frequency. Fixed 16.67 MHz limit. 4, 10, 16, 23, 27, 31, 39 VDD3V 1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52 VSS 43, 47, 51, 56 VDD25V 3.3V PCI clock outputs 3.3V fixed 66MHz clock outputs Select input pin for enabling 133MHz or 100MHz CPU outputs. H = 133MHz, L = 100MHz 3.3V fixed 48MHZ clock output 3.3V power supply. Ground 2.5V power supply NOTES: 1. VDD3V, VDD25V and VSS in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on the performance of the device. In reality, the platform will be configured with the VDD25V pins tied to a 2.5V supply, all remaining VDD pins tied to a common 3.3V supply and all VSS pins being common. 1999 Mar 01 3 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 BLOCK DIAGRAM LOGIC PWRDWN LOGIC X REF [0–1](14.318 MHz) USBPLL PWRDWN LOGIC X 48MHz SYSPLL STOP X CPUCLK [0–3] STOP X 3V66 [0–3] (66MHz) XTAL_IN X XTAL_OUT X 14.318 MHZ OSC LOGIC PWRDWN LOGIC X CPUDIV2 [0–1] PWRDWN LOGIC X PCICLK_F (33MHz) SEL0 X SEL1 X SPREAD X SEL133/100 X PCISTOP X CPUSTOP X STOP PWRDWN X PWRDWN LOGIC X PCICLK [1–7] (33MHz) X APIC [0–2] ( PCI) SW00353 1999 Mar 01 4 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM 168-pin SDR SDRAM DIMM BACK SIDE FRONT SIDE AVC AVC AVC PCK2509S or PCK2510S The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW00403 FUNCTION TABLE SEL 133/100 SEL1 SEL0 CPU CPUDIV2 3V66 PCI 48MHz REF IOAPIC NOTES 0 0 0 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1 0 0 1 N/A N/A N/A N/A N/A N/A N/A 2 0 1 0 100MHz 50MHz 66MHz 33MHz HI-Z 14.318MHz 16.67MHz 3 0 1 1 100MHz 50MHz 66MHz 33MHz 48MHz 14.318MHz 16.67MHz 4, 7, 8 1 0 0 TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 5, 6 1 0 1 N/A N/A N/A N/A N/A N/A N/A 2 1 1 0 133MHz 66MHz 66MHz 33MHz HI-Z 14.318MHz 16.67MHz 3 1 1 1 133MHz 66MHz 66MHz 33MHz 48MHz 14.318MHz 16.67MHz 4, 7, 8 NOTES: 1. Required for board level ‘‘bed-of-nails” testing. 2. Used to support Intel confidential application. 3. 48MHz PLL disabled to reduce component jitter. 48MHz outputs to be held Hi-Z instead of driven to LOW state. 4. ‘‘Normal” mode of operation. 5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133MHz CPU select logic. 6. Required for DC output impedance verification. 7. Frequency accuracy of 48MHz must be +167 PPM to match USB default. 8. Range of reference frequency allowed is MIN = 14.316MHz, NOMINAL = 14.31818MHz, MAX = 14.32MHz CLOCK OUTPUT TARGET FREQUENCY (MHz) ACTUAL FREQUENCY (MHz) PPM USBCLK7 48.0 48.008 167 1999 Mar 01 5 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 CLOCK ENABLE CONFIGURATION CPUSTOP PWRDWN PCISTOP CPUCLK CPUDIV2 APIC 3V66 PCI PCIF REF 48MHz OSC VCOs X 0 X LOW LOW LOW LOW LOW LOW LOW OFF OFF 0 1 0 LOW ON ON LOW LOW ON ON ON ON 0 1 1 LOW ON ON LOW ON ON ON ON ON 1 1 0 ON ON ON ON LOW ON ON ON ON 1 1 1 ON ON ON ON ON ON ON ON ON NOTES: 1. LOW means outputs held static LOW as per latency requirement below 2. ON means active. 3. PWRDWN pulled LOW, impacts all outputs including REF and 48MHz outputs. 4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW. 5. CPUDIV2, IOAPIC, REF, 48MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when PWRDWN is LOW. POWER MANAGEMENT REQUIREMENTS LATENCY SG SIGNAL SG S SIGNAL STATE NO. OF RISING EDGES OF FREE RUNNING PCICLK CPUSTOP 0 (DISABLED) 1 1 (ENABLED) 1 0 (DISABLED) 1 1 (ENABLED) 1 1 (NORMAL OPERATION) 3ms 0 (POWER DOWN) 2 MAX PCISTOP PWRDWN NOTES: 1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the first valid clock that comes out of the device. 2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to VSS (VSS = 0V) SYMBOL PARAMETER VDD3 CONDITION LIMITS UNIT MIN MAX DC 3.3V core supply voltage –0.5 +4.6 V VDDQ3 DC 3.3V I/O supply voltage –0.5 +4.6 V VDDQ2 DC 2.5V I/O supply voltage –0.5 +3.6 V IIK DC input diode current VI < 0 –50 mA VI DC input voltage Note 2 IOK DC output diode current VO > VCC or VO < 0 VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VCC TSTG Storage temperature range PTOT Power dissipation per package plastic medium-shrink (SSOP) –0.5 –0.5 –65 For temperature range: –40 to +125°C above +55°C derate linearly with 11.3mW/K 5.5 V ±50 mA VCC + 0.5 V ±50 mA +150 °C 850 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1999 Mar 01 6 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN MAX VDD3V DC 3.3V core supply voltage 3.135 3.465 V VDD25V DC 2.5V I/O supply voltage 2.375 2.625 V CL Capacitive load on: CPUCLK PCICLK CPUDIV2 3V66 48MHz clock REF IOAPIC 10 10 10 10 10 10 10 20 30 20 30 20 20 20 VI DC input voltage range 0 VDD3V V VO DC output voltage range 0 VDD25V VDD3V V fREF Reference frequency, oscillator nominal value 14.31818 14.31818 MHz Tamb Operating ambient temperature range in free air 0 +70 °C 1 device load, possible 2 loads Must meet PCI 2.1 requirements 1 device load, possible 2 loads 1 device load, possible 2 loads 1 device load 1 device load 1 device load pF POWER MANAGEMENT CK133 CONDITION MAXIMUM 2.5V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDD25V = 2.625V ALL STATIC INPUTS = VDD3V OR VSS MAXIMUM 3.3V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDD25V= 3.465V ALL STATIC INPUTS = VDD3V OR VSS Power-down mode (PWRDWN = 0) 100µA 200µA Full active 100MHz SEL133/100# = 0 SEL1, 0 = 1 1 CPUSTOP, PCISTOP = 1 75mA 160mA Full active 133MHz SEL133/100# = 1 SEL1, 0 = 1 1 CPUSTOP, PCISTOP = 1 90mA 160mA 1999 Mar 01 7 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 DC CHARACTERISTICS LIMITS TEST CONDITIONS SYMBOL Tamb = 0°C to +70°C PARAMETER VDD (V) OTHER MIN TYP UNIT MAX VIH HIGH level input voltage 3.135 to 3.465 VDD25V = 2.5V ±5% 2.0 VDD + 0.3 V VIL LOW level input voltage 3.135 to 3.465 VDD3V = 3.3V ±5% VSS – 0.3 0.8 V VOH2 2.5V output HIGH voltage CPUCLK, IOAPIC, CPUDIV2 2.375 to 2.625 IOH = –1mA 2.0 – V VOL2 2.5V output LOW voltage CPUCLK, IOAPIC, CPUDIV2 2.375 to 2.625 IOL = 1mA – 0.4 V VOH3 3.3V output HIGH voltage REF, 48MHz 3.135 to 3.465 IOH = –1mA 2.0 – V VOL3 3.3V output LOW voltage REF, 48MHz 3.135 to 3.465 IOL = 1mA – 0.4 V VOH3 3.3V output HIGH voltage PCI, 3V66 3.135 to 3.465 IOH = –1mA 2.4 – V VOL3 3.3V output LOW voltage PCI, 3V66 3.135 to 3.465 IOL= 1mA – 0.55 V IOH CPUCLK output HIGH current 2.375 VOUT = 1.0V –27 – 2.625 VOUT = 2.375V – –27 IOH 48MHz, REF output HIGH current 3.135 VOUT = 1.0V –29 – 3.465 VOUT = 3.135V – –23 IOH PCI, 3V66 output HIGH current 3.135 VOUT = 1.0V –33 – 3.465 VOUT = 3.135V – –33 IOL CPUCLK output LOW current 2.375 VOUT = 1.2V 27 – 2.625 VOUT = 0.3V – 30 IOL 48MHz, REF output LOW current 3.135 VOUT = 1.95V 29 – 3.465 VOUT = 0.4V – 27 IOL PCI, 3V66 output LOW current 3.135 VOUT = 1.95V 30 – 3.465 VOUT = 0.4V – 38 ±II Input leakage current 3.465 – 5 µA ±IOZ 3-State output OFF-State current – 10 µA 5 pF Cin Input pin capacitance Cxtal Xtal pin capacitance, as seen by external crystal Cout Output pin capacitance Idd3 Operating O erating supply su ly current 3.465 Operating O erating supply su ly current Powerdown supply current IO = 0 18 3.465 Powerdown supply current Idd2 VOUT = Vdd or GND mA mA mA mA pF 6 pF 100MHz mode Outputs 160 mA 133MHz mode Outputs loaded1 160 mA 200 µA 100MHz mode Output loaded1 160 mA 133MHz mode Output loaded1 160 mA 100 µA All static inputs to VDD or GND NOTE: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section. 1999 Mar 01 mA loaded1 All static inputs to VDD or GND 2.625 mA 8 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 AC CHARACTERISTICS VDD3V = 3.3V ± 5%; VDDAPIC = VDD25V = 2.5V ± 5%; fcrystal = 14.31818 MHz CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF) LIMITS Tamb = 0°C to +70°C LIMITS Tamb = 0°C to +70°C 133MHz MODE 100MHz MODE SYMBOL PARAMETER MIN MAX MIN MAX THKP CPUCLK period 7.5 8.0 10.0 10.5 ns 2, 9 THKH CPUCLK HIGH time 1.87 n/a 3.0 n/a ns 5, 10 THKL CPUCLK LOW time 1.67 n/a 2.8 n/a ns 6, 10 THRISE CPUCLK rise time 0.4 1.6 0.4 1.6 ns 8 THFALL CPUCLK fall time 0.4 1.6 0.4 1.6 ns 8 TJITTER CPUCLK cycle-cycle jitter 250 ps DUTY CYCLE Output Duty Cycle THSKW CPUCLK pin-pin skew 250 45 55 45 175 UNIT NOTES 55 % 1 175 ps 2 CPUDIV2 CLOCK OUTPUTS, CPUDIV2 (0–1) (LUMP CAPACITANCE TEST LOAD = 20pF) LIMITS Tamb = 0°C to +70°C LIMITS Tamb = 0°C to +70°C 133MHz MODE 100MHz MODE SYMBOL PARAMETER MIN MAX MIN MAX THKP CPUDIV2 CLK period 15.0 16.0 20.0 21.0 ns 2, 9 THKH CPUDIV2 CLK HIGH time 5.25 n/a 7.5 n/a ns 5, 10 THKL CPUDIV2 CLK LOW time 5.05 n/a 7.3 n/a ns 6, 10 THRISE CPUDIV2 CLK rise time 0.4 1.6 0.4 1.6 ns 8 THFALL CPUDIV2 CLK fall time 0.4 1.6 0.4 1.6 ns 8 TJITTER CPUDIV2 CLK cycle-cycle jitter 250 ps DUTY CYCLE CPUDIV2 CLK Duty Cycle THSKW CPUDIV2 CLK pin-pin skew 250 45 55 45 175 UNIT NOTES 55 % 1 175 ps 2 UNIT NOTES PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30pF) LIMITS Tamb = 0°C to +70°C LIMITS Tamb = 0°C to +70°C 133MHz MODE 100MHz MODE SYMBOL PARAMETER MIN MAX MIN MAX THKP PCICLK period 30.0 n/a 30.0 n/a ns 2, 9 THKH PCICLK HIGH time 12.0 n/a 12.0 n/a ns 5, 10 THKL PCICLK LOW time 12.0 n/a 12.0 n/a ns 6, 10 THRISE PCICLK rise time 0.5 2.0 0.5 2.0 ns 8 THFALL PCICLK fall time 0.5 2.0 0.5 2.0 ns 8 TJITTER PCICLK cycle-cycle jitter 500 ps DUTY CYCLE PCICLK Duty Cycle THSKW PCICLK pin-pin skew 1999 Mar 01 500 45 55 45 500 9 55 % 1 500 ps 2 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF) LIMITS Tamb = 0°C to +70°C LIMITS Tamb = 0°C to +70°C 133MHz MODE 100MHz MODE SYMBOL PARAMETER MIN MAX MIN MAX THKP IOAPIC CLK period 60.0 64.0 60.0 THKH IOAPIC CLK HIGH time 25.5 n/a THKL IOAPIC CLK LOW time 25.3 n/a THRISE IOAPIC CLK rise time 0.4 THFALL IOAPIC CLK fall time 0.4 TJITTER IOAPIC CLK cycle-cycle jitter DUTY CYCLE IOAPIC CLK Duty Cycle THSKW IOAPIC CLK pin-pin skew UNIT NOTES 64.0 ns 2, 9 25.5 n/a ns 5, 10 25.3 n/a ns 6, 10 1.6 0.4 1.6 ns 8 1.6 0.4 1.6 ns 8 500 ps 500 45 55 45 250 55 % 1 250 ps 2 UNIT NOTES 3V66 CLOCK OUTPUT, 3V66 (0–3) (LUMP CAPACITANCE TEST LOAD = 30 pF) LIMITS Tamb = 0°C to +70°C LIMITS Tamb = 0°C to +70°C 133MHz MODE 100MHz MODE SYMBOL PARAMETER MIN MAX MIN MAX THKP 3V66 CLK period 15.0 16.0 15.0 16.0 ns 2, 9, 4 THKH 3V66 CLK HIGH time 5.25 n/a 5.25 n/a ns 5, 10 THKL 3V66 CLK LOW time 5.05 n/a 5.05 n/a ns 6, 10 THRISE 3V66 CLK rise time 0.4 1.6 0.4 1.6 ns 8 THFALL 3V66 CLK fall time 0.4 1.6 0.4 1.6 ns 8 TJITTER 3V66 CLK cycle-cycle jitter 500 ps DUTY CYCLE 3V66 CLK Duty Cycle THSKW 3V66 CLK pin-pin skew 500 45 55 45 250 55 % 1 250 ps 2 48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF) SYMBOL TEST CONDITIONS PARAMETER NOTES f Frequency, Actual Determined by PLL divider ratio (48.008 – 48)/48 LIMITS Tamb = 0°C to +70°C MIN UNIT MAX 48.008 MHz fD Deviation from 48MHz THRISE (tR) Output rise edge rate 1 +167 4 ns THFALL (tF) Output fall edge rate 1 4 ns DUTY CYCLE (tD) Duty Cycle 45 55 % MAX ps 133MHz TJITTER CLK cycle-cycle jitter MIN 100MHz MAX 500 THSTB (fST) Frequency stabilization from Power-up (cold start) NOTES: 1. See Figure 3 for measure points. 1999 Mar 01 10 ppm MIN 500 3 ms Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 AC CHARACTERISTICS (Continued) LIMITS Tamb = 0°C to +70°C TEST CONDITIONS SYMBOL PARAMETER Measurement loads (lumped) Measure points MIN TYP UNIT NOTES MAX THPOFFSET CPUCLK to 3V66 CLK, CPU leads CPU@30pF, 3V66@30pF [email protected], [email protected] 0.0 1.5 ns 1 THPOFFSET 3V66 CLK to PCICLK, 3V66 leads 3V66@30pF, PCI@30pF [email protected], [email protected] 1.5 3.5 ns 1 THPOFFSET CPUCLK to IOAPIC, CPU leads CPU@20pF, IOAPIC@20pF [email protected], [email protected] 1.5 4.0 ns 1 PCICLK to CPUCLK, CPU leads PCI@30pF CPU@30pF [email protected] [email protected] 5.8 ns CPUDIV2 to CPUCLK, CPUDIV2 leads CPUDIV2@20pF CPU@30pF CPUDIV2@ [email protected] 1.6 ns IOAPICCLK to CPUCLK, IOAPIC leads IOAPIC@20pF CPU@30pF IOAPIC@20pF [email protected] 3.7 ns 3V66 CLK to CPUCLK, 3V66 leads 3V66@30pF CPU@30pF [email protected] [email protected] 1.7 ns NOTES: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks. 3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133.MHz. The 3V66 CLK is internal VCO frequency divided by three at CPUCLK = 100MHz. 4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133MHz. The 3V66 CLK is internal VCO frequency divided by three at CPUCLK = 100MHz. 5. THKH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs as shown in Figure 4. 6. THKL is measured at 0.4V for all outputs as shown in Figure 4. 7. The time is specified from when VDDQ achieves its nominal operating level (typical condition VDDQ = 3.3V) until the frequency output is stable and operating within specification. 8. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V (1mA) JEDEC specification. 9. The average period over any 1 µs period of time must be greater than the minimum specified period. 10. Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure duty-cycle specification is met. 11. Output (see Figure 3 for measure points). PCK2010 SPREAD SPECTRUM FUNCTION TABLE SPREAD# SEL133/100# SEL1 SEL0 Intel CK133 Intel CK133 Philips PCK2010 Philips PCK2010 pin 34 pin 28 pin 33 pin 32 Function 48MHz PLL Function 48MHz PLL 0 (active) 0 (100MHz) 0 0 3-State to High Impedance Inactive 0 (active) 0 (100MHz) 0 1 (Reserved) (Reserved) 0 (active) 0 (100MHz) 1 0 0 (active) 0 (100MHz) 1 1 0 (active) 1 (133MHz) 0 0 100MHz, Down Spread – 0.5% 100MHz, Down Spread – 0.5% Test Mode 0 (active) 1 (133MHz) 0 1 (Reserved) 0 (active) 1 (133MHz) 1 0 0 (active) 1 (133MHz) 1 1 1 (inactive) 0 (100MHz) 0 0 1999 Mar 01 Inactive Active Active (Reserved) 133Mhz, Down Spread – 0.5% 133Mhz, Down Spread – 0.5% 3-State to High Impedance 11 Inactive Active Inactive 3-State to High Impedance 100MHz, Center Spread ±0.5% 100MHz, Down Spread – 0.5% 100MHz, Down Spread – 0.5% Test Mode 133MHz, Center Spread ±0.5% 133MHz, Down Spread – 0.5% 133MHz, Down Spread – 0.5% 3-State to High Impedance Inactive Active Inactive Active Active Active Inactive Active Inactive Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator 1 (inactive) 0 (100MHz) 0 1 (Reserved) (Reserved) 1 (inactive) 0 (100MHz) 1 0 1 (inactive) 0 (100MHz) 1 1 1 (inactive) 1 (133MHz) 0 0 100MHz, No Spread Spectrum 100MHz, No Spread Spectrum Test Mode 1 (inactive) 1 (133MHz) 0 1 (Reserved) 1 (inactive) 1 (133MHz) 1 0 1 (inactive) 1 (133MHz) 1 1 Inactive Active Active (Reserved) 133MHz, No Spread Spectrum 133MHz, No Spread Spectrum Inactive Active PCK2010 100MHz, No Center Spread ±0.5% 100MHz, No Spread Spectrum 100MHz, No Down Spread – 0.5% Test Mode 133MHz, No Center Spread ±0.5% 133MHz, No Spread Spectrum 133MHz, No Down Spread – 0.5% Active Inactive Active Active Active Inactive Active AC WAVEFORMS VM = 1.25V @ VDDQ2 and 1.5V @ VDDQ3 VX = VOL + 0.3V VY = VOH –0.3V VOL and VOH are the typical output voltage drop that occur with the output load. VDDQ2 CPUCLK @133MHz VDDQ2 CPUCLK @ 133MHz 1.25V 1.25V VSS VSS VDDQ3 3v66 @66MHz VDDQ2 IOAPIC @ 16.6MHz 1.5V 1.25V VSS VSS CPUCLK leads IOAPIC CPU leads 3V66 THPOFFSET THPOFFSET SW00354 SW00357 Figure 1. CPUCLK to 3V66 offset Figure 3. CPU to IOAPIC offset THKP DUTY CYCLE VDDQ3 3V66 @ 66MHz 1.5V THKH VSS 2.5V CLOCKING INTERFACE 2.0 1.25 0.4 VDDQ3 PCICLK @ 33MHz THKL TRISE 1.5V TFALL VSS TPKP TPKH THPOFFSET 3V66 leads PCICLK 3.3V CLOCKING INTERFACE (TTL) SW00356 2.4 1.5 0.4 TPKL Figure 2. 3V66 to PCI offset TRISE TFALL SW00242 Figure 4. 2.5V/3.3V clock waveforms 1999 Mar 01 12 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 VI COMPONENT MEASUREMENT POINTS SEL133/100, SEL1, SEL0 2.5VOLT MEASURE POINTS VOH = 2.0V VOL = 0.4V VDDQ2 GND VIH = 1.7V 1.25V VIL = 0.7V tPLZ SYSTEM MEASUREMENT POINTS COMPONENT MEASUREMENT POINTS OUTPUT LOW-to-OFF OFF-to-LOW VOH = 2.4V VM VX VOL 3.3VOLT MEASURE POINTS VSS tPZL VDD VSS VOL = 0.4V VM VDDQ3 VIH = 2.0V 1.5V VIL = 0.7V tPHZ tPZH VOH VY OUTPUT HIGH-to-OFF OFF-to-HIGH SYSTEM MEASUREMENT POINTS VSS SW00243 VM outputs enabled outputs disabled Figure 5. Component versus system measure points SW00454 Figure 6. 3-State enable and disable times 1999 Mar 01 outputs enabled 13 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 S1 VDD 2VDD Open VSS 500Ω VI VO PULSE GENERATOR D.U.T. RT CL TEST S1 tPLH/tPHL Open tPLZ/tPZL 2VDD tPHZ/tPZH VSS 500Ω VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT SW00238 Figure 7. Load circuitry for switching times PWRDWN CPUCLK (INTERNAL) PCICLK (INTERNAL) PWRDWN CPUCLK (EXTERNAL) PCICLK (EXTERNAL) Á Á Á Á OSC & VCO USB (48MHz) Figure 8. Power Management 1999 Mar 01 14 SW00244 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1999 Mar 01 15 PCK2010 SOT371-1 Philips Semiconductors Preliminary specification CK98 (100/133MHz) Spread Spectrum System Clock Generator PCK2010 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 16 Date of release: 05-96 9397-750-04955