INTERGRATED CIRCUITS DATA SHEET SAA7120H; SAA7121H Digital video encoder Product specification Supersedes data of 1997 Jan 06 2002 Oct 11 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Data manager Encoder Output interface/DACs Synchronization I2C-bus interface Input levels and formats Bit allocation map I2C-bus format Slave receiver Slave transmitter 8 CHARACTERISTICS 8.1 8.2 Explanation of RTCI data bits Teletext timing 9 APPLICATION INFORMATION 9.1 Analog output voltages 10 PACKAGE OUTLINE 11 SOLDERING 11.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 11.2 11.3 11.4 11.5 12 DATA SHEET STATUS 13 DEFINITIONS 14 DISCLAIMERS 15 PURCHASE OF PHILIPS I2C COMPONENTS 2002 Oct 11 2 Philips Semiconductors Product specification Digital video encoder 1 SAA7120H; SAA7121H FEATURES • Monolithic CMOS 3.3 V device • Digital PAL/NTSC encoder • System pixel frequency 13.5 MHz • Accepts MPEG decoded data on 8-bit wide input port; input data format CB-Y-CR (CCIR 656) • Controlled rise/fall times of synchronization and blanking output signals • Three Digital-to-Analog Converters (DACs) for Y, C and CVBS two times oversampled with 10-bit resolution • Macrovision(1) Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; this applies to SAA7120H only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information • Real-time control of subcarrier • Cross-colour reduction filter • Closed captioning encoding and World Standard Teletext (WST) and North-American Broadcast Text System (NABTS) teletext encoding including sequencer and filter • Line 23 Wide Screen Signalling (WSS) encoding • QFP44 package. • Fast I2C-bus control port (400 kHz) • Encoder can be master or slave 2 • Programmable horizontal and vertical input synchronization phase GENERAL DESCRIPTION The SAA7120H; SAA7121H encodes digital YUV video data to an NTSC or PAL CVBS or S-video signal. • Programmable horizontal sync output phase • Internal Colour Bar Generator (CBG) The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip DACs. • 2 × 2 bytes in lines 20 (NTSC) for copy guard management system can be loaded via I2C-bus • Down mode of DACs (1) Macrovision is a trademark of the Macrovision Corporation. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7120H SAA7121H 2002 Oct 11 QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm 3 VERSION SOT307-2 Philips Semiconductors Product specification Digital video encoder 4 SAA7120H; SAA7121H QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA analog supply voltage 3.1 3.3 3.5 V VDDD digital supply voltage 3.0 3.3 3.6 V IDDA analog supply current − 55 62 mA IDDD digital supply current − 32 45 mA Vi input signal voltage levels Vo(p-p) analog output signal voltages Y, C and CVBS without load (peak-to-peak value) − 1.35 − V RL load resistance 75 − 300 Ω LElf(i) low frequency integral linearity error − − ±3 LSB LElf(d) low frequency differential linearity error − − ±1 LSB Tamb ambient temperature 0 − 70 °C 5 TTL compatible BLOCK DIAGRAM VDDA1, handbook, full pagewidth RCV1 RCV2 RESET SDA SCL SA 40 42 41 21 DATA MANAGER VDDA2, VDDA3 36 I2C-bus control 30 OUTPUT INTERFACE ENCODER CB-CR VDDA4 25, 28, 31 Y C I2C-bus control TTX XTALI 43 37 34 35 4 clock and timing Y 9 to 16 LLC SYNC CLOCK SAA7120H SAA7121H I2C-bus control XCLK 8 7 I2C-BUS INTERFACE MP7 to MP0 TTXRQ XTALO I2C-bus control I2C-bus control D 27 A 24 32, 33 6, 17, 39 1, 20, 22, 23, 26, 29 19 2 3 MBH787 VSSD1, VDDD1, VSSD2, VDDD2, VSSD3 VDDD3 RES RTCI SP Fig.1 Block diagram. 2002 Oct 11 4 AP Y C VSSA1 VSSA2 44 5, 18, 38 CVBS Philips Semiconductors Product specification Digital video encoder 6 SAA7120H; SAA7121H PINNING SYMBOL PIN TYPE DESCRIPTION RES 1 − reserved SP 2 I test pin; connected to digital ground for normal operation AP 3 I test pin; connected to digital ground for normal operation LLC 4 I VSSD1 5 supply digital ground 1 VDDD1 6 supply digital supply voltage 1 RCV1 7 I/O raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal RCV2 8 I/O raster control 2 for video port; this pin provides an HS pulse of programmable length or receives an HS pulse MP7 9 I MP6 10 I MP5 11 I MP4 12 I MP3 13 I MP2 14 I MP1 15 I MP0 16 I VDDD2 17 supply digital supply voltage 2 VSSD2 18 supply digital ground 2 RTCI 19 I real-time control input; if the LLC clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality RES 20 − reserved SA 21 I the I2C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH RES 22 − reserved RES 23 − reserved C 24 O analog output of the chrominance signal VDDA1 25 supply RES 26 − reserved Y 27 O analog output of VBS signal VDDA2 28 supply RES 29 − reserved CVBS 30 O analog output of the CVBS signal VDDA3 31 supply analog supply voltage 3 for the CVBS DAC VSSA1 32 supply analog ground 1 for the DACs VSSA2 33 supply analog ground 2 for the oscillator and reference voltage XTALO 34 O crystal oscillator output XTALI 35 I crystal oscillator input; if the oscillator is not used, this pin should be connected to ground VDDA4 36 supply 2002 Oct 11 line-locked clock; this is the 27 MHz master clock for the encoder MPEG ports; inputs for “CCIR 656” style multiplexed CB-Y-CR data analog supply voltage 1 for the C DAC analog supply voltage 2 for the Y DAC analog supply voltage 4 for the oscillator and reference voltage 5 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H SYMBOL PIN TYPE DESCRIPTION XCLK 37 O VSSD3 38 supply digital ground 3 VDDD3 39 supply digital supply voltage 3 RESET 40 I Reset input, active LOW. After reset is applied, all digital I/Os are in input mode. The I2C-bus receiver waits for the START condition. SCL 41 I I2C-bus serial clock input SDA 42 I/O I2C-bus serial data input/output TTXRQ 43 O teletext request output, indicating when bit stream is valid TTX 44 I teletext bit stream input 34 XTALO 35 XTALI 36 VDDA4 37 XCLK 38 VSSD3 39 VDDD3 40 RESET 41 SCL 42 SDA 44 TTX handbook, full pagewidth 43 TTXRQ clock output of the crystal oscillator RES 1 33 VSSA2 SP 2 32 VSSA1 AP 3 31 VDDA3 30 CVBS LLC 4 VSSD1 5 29 RES SAA7120H SAA7121H VDDD1 6 28 VDDA2 RCV1 7 27 Y RCV2 8 26 RES Fig.2 Pin configuration. 2002 Oct 11 6 RES 22 SA 21 RES 20 RTCI 19 VSSD2 18 VDDD2 17 23 RES MP0 16 MP5 11 MP1 15 24 C MP2 14 MP6 10 MP3 13 25 VDDA1 MP4 12 MP7 9 MBH790 Philips Semiconductors Product specification Digital video encoder 7 SAA7120H; SAA7121H 7.1 FUNCTIONAL DESCRIPTION Real-time arbitration on the data stream to be encoded is performed in the data manager. The digital video encoder encodes digital luminance and colour difference signals into analog CVBS and simultaneously S-video signals. NTSC-M, PAL-B/G and sub-standards are supported. Both interlaced and non-interlaced operation is possible for all standards. A pre-defined colour look-up table located in this block can be read out in a pre-defined sequence (8 steps per active video line), achieving a colour bar test pattern generator without the need for an external data source. The colour bar function is under software control only. The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of “RS-170-A” and “CCIR 624”. 7.2 7.2.1 For ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. Encoder VIDEO PATH The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. The total filter transfer characteristics are illustrated in Figs 3 to 6. The DACs for Y, C and CVBS are realized with full 10-bit resolution. Luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level in accordance with standard composite synchronization schemes. Other manipulations used for the Macrovision anti-taping process such as additional insertion of AGC super-white pulses (programmable in height) are supported by the SAA7120H only. The 8-bit multiplexed CB-Y-CR formats are “CCIR 656” (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. It is also possible to connect a Philips digital video decoder (SAA7111 or SAA7151B) to this encoder. By connecting pin RTCI to pin RTCO of a decoder, information about the actual subcarrier, PAL-ID and (with SAA7111 and newer types) definite subcarrier phase can be inserted. In order to enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 5 and 6. The digital video encoder synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using 50 Hz field rate. Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 3 and 4. The IC also contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with Macrovision. A number of possibilities are provided for setting different video parameters, such as: • Black and blanking level control The amplitude, beginning and ending of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in a 10-bit resolution is provided on the subcarrier. • Colour subcarrier frequency • Variable burst amplitude, etc. During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the I2C-bus interface to abort any running bus transfer and sets register 3A to 03H, register 61 to 06H, registers 6BH and 6EH to 00H and bit TTX60 to 0. No other control registers are influenced by a reset. 2002 Oct 11 Data manager The numeric ratio between Y and C outputs is in accordance with the respective standards. 7 Philips Semiconductors Product specification Digital video encoder 7.2.2 SAA7120H; SAA7121H TELETEXT INSERTION AND ENCODING Outputs of the DACs can be set together in two groups, via software control, to a minimum output voltage for either purpose. Pin TTX receives a WST or NABTS teletext bitstream sampled at the LLC clock. At each rising edge of output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at the input pin. 7.4 The synchronization of the SAA7120H; SAA7121H is able to operate in two modes; slave mode and master mode. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to RCV1 can be influenced by programming the polarity and the on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it also can be used to set the horizontal phase. TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which are selectable independently for both fields. The internal insertion window for text is set to 360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.10. 7.2.3 If the horizontal phase is not to be influenced by RCV1, a horizontal pulse needs to be applied to pin RCV2. Timing and trigger behaviour can also be influenced for the signal at pin RCV2. CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. If there are missing pulses at RCV1 and/or RCV2, the time base of the IC runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (with the incorrect phase) must occur. The actual line number where data is to be encoded in, can be modified in a certain range. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. The data clock frequency is in accordance with the definition for NTSC-M standard 32 times horizontal line frequency. Alternatively, the device can be triggered by auxiliary codes in a “CCIR 656” data stream at the MP port. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the device can output: • A Vertical Sync (VS) signal with 3 or 2.5 lines duration It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. 7.2.4 • An odd/even signal which is LOW in odd fields • A Field Sequence (FSEQ) signal which is HIGH in the first of 4 or 8 fields respectively. ANTI-TAPING (SAA7120H ONLY) For more information contact your nearest Philips Semiconductors sales office. 7.3 On the RCV2 port, the IC can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. Output interface/DACs In the output interface, encoded Y and C signals are converted from digital-to-analog in a 10-bit resolution. Y and C signals are also combined to a 10-bit CVBS signal. The polarity of both RCV1 and RCV2 is selectable by software control. The length of a field and the start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Y and C DACs to make maximum use of conversion ranges. 2002 Oct 11 Synchronization 8 Philips Semiconductors Product specification Digital video encoder 7.5 SAA7120H; SAA7121H Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. I2C-bus interface The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. “CCIR 601” signal component levels Table 1 SIGNALS COLOUR Y CB CR White 235 128 128 Yellow 210 16 146 Cyan 170 166 16 The SAA7120H; SAA7121H expects digital Y, CB and CR data with levels (digital codes) in accordance with “CCIR 601”. Green 145 54 34 Magenta 106 202 222 Red 81 90 240 For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. Blue 41 240 110 Black 16 128 128 The I2C-bus slave address is defined as 88H with pin 21 (SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH. 7.6 Input levels and formats Table 2 8-bit multiplexed format (similar to “CCIR 601”) BITS TIME 0 Sample Luminance pixel number Colour pixel number 2002 Oct 11 CB0 1 2 Y0 CR0 0 1 0 3 4 Y1 CB2 5 6 Y2 CR2 2 Y3 3 2 9 7 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 3 Slave receiver (slave address 88H or 8CH) DATA BYTE(1) REGISTER FUNCTION SUBADDR D7 Null 00H to 25H D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Wide screen signal 26H WSS7 WSS6 WSS5 WSS4 WSS3 WSS2 WSS1 WSS0 Wide screen signal 27H WSSON 0 WSS13 WSS12 WSS11 WSS10 WSS9 WSS8 Real-time control, burst start 28H DECCOL DECFIS BS5 BS4 BS3 BS2 BS1 BS0 Burst end 29H 0 0 BE5 BE4 BE3 BE2 BE1 BE0 Copy guard odd 0 2AH CGO07 CGO06 CGO05 CGO04 CGO03 CGO02 CGO01 CGO00 Copy guard odd 1 2BH CGO17 CGO16 CGO15 CGO14 CGO13 CGO12 CGO11 CGO10 Copy guard even 0 2CH CGE07 CGE06 CGE05 CGE04 CGE03 CGE02 CGE01 CGE00 Copy guard even 1 2DH CGE17 CGE16 CGE15 CGE14 CGE13 CGE12 CGE11 CGE10 Copy guard enable 2EH CGEN1 CGEN0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Null 2FH to 39H 10 CBENB 0 0 SYMP 0 0 Y2C UV2C 5AH CHPS7 CHPS6 CHPS5 CHPS4 CHPS3 CHPS2 CHPS1 CHPS0 Gain U 5BH GAINU7 GAINU6 GAINU5 GAINU4 GAINU3 GAINU2 GAINU1 GAINU0 Gain V 5CH GAINV7 GAINV6 GAINV5 GAINV4 GAINV3 GAINV2 GAINV1 GAINV0 Gain U MSB, real-time control, black level 5DH GAINU8 DECOE BLCKL5 BLCKL4 BLCKL3 BLCKL2 BLCKL1 BLCKL0 Gain V MSB, real-time control, blanking level 5EH GAINV8 DECPH BLNNL5 BLNNL4 BLNNL3 BLNNL2 BLNNL1 BLNNL0 CCR, blanking level VBI 5FH CCRS1 CCRS0 BLNVB5 BLNVB4 BLNVB3 BLNVB2 BLNVB1 BLNVB0 Null 60H 0 0 0 0 0 0 0 0 Standard control 61H 0 DOWN INPI YGS 0 SCBW PAL FISE RTC enable, burst amplitude 62H RTCE BSTA6 BSTA5 BSTA4 BSTA3 BSTA2 BSTA1 BSTA0 Subcarrier 0 63H FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00 Subcarrier 1 64H FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 Subcarrier 2 65H FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 Subcarrier 3 66H FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24 Line 21 odd 0 67H L21O07 L21O06 L21O05 L21O04 L21O03 L21O02 L21O01 L21O00 Line 21 odd 1 68H L21O17 L21O16 L21O15 L21O14 L21O13 L21O12 L21O11 L21O10 Product specification 3AH Chrominance phase SAA7120H; SAA7121H Input port control Philips Semiconductors Bit allocation map Digital video encoder 2002 Oct 11 7.7 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D7 D6 D5 D4 D3 D2 D1 D0 11 Line 21 even 0 69H L21E07 L21E06 L21E05 L21E04 L21E03 L21E02 L21E01 L21E00 Line 21 even 1 6AH L21E17 L21E16 L21E15 L21E14 L21E13 L21E12 L21E11 L21E10 RCV port control 6BH SRCV11 SRCV10 TRCV2 ORCV1 PRCV1 CBLF ORCV2 PRCV2 Trigger control 6CH HTRIG7 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 HTRIG0 Trigger control 6DH HTRIG10 HTRIG9 HTRIG8 VTRIG4 VTRIG3 VTRIG2 VTRIG1 VTRIG0 Multi control 6EH SBLBN 0 PHRES1 PHRES0 0 0 FLC1 FLC0 Closed caption, teletext enable 6FH CCEN1 CCEN0 TTXEN SCCLN4 SCCLN3 SCCLN2 SCCLN1 SCCLN0 RCV2 output start 70H RCV2S7 RCV2S6 RCV2S5 RCV2S4 RCV2S3 RCV2S2 RCV2S1 RCV2S0 RCV2 output end 71H RCV2E7 RCV2E6 RCV2E5 RCV2E4 RCV2E3 RCV2E2 RCV2E1 RCV2E0 MSBs RCV2 output 72H 0 RCV2E10 RCV2E9 RCV2E8 0 RCV2S10 RCV2S9 RCV2S8 TTX request H start 73H TTXHS7 TTXHS6 TTXHS5 TTXHS4 TTXHS3 TTXHS2 TTXHS1 TTXHS0 TTX request H delay 74H TTXHD7 TTXHD6 TTXHD5 TTXHD4 TTXHD3 TTXHD2 TTXHD1 TTXHD0 Vsync shift 75H 0 0 0 0 0 VS_S2 VS_S1 VS_S0 TTX odd request vertical start 76H TTXOVS7 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVS3 TTXOVS2 TTXOVS1 TTXOVS0 TTX odd request vertical end 77H TTXOVE7 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVE3 TTXOVE2 TTXOVE1 TTXOVE0 TTX even request vertical start 78H TTXEVS7 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVS3 TTXEVS2 TTXEVS1 TTXEVS0 79H TTXEVE7 TTXEVE6 TTXEVE5 TTXEVE4 TTXEVE3 TTXEVE2 TTXEVE1 TTXEVE0 First active line 7AH FAL7 FAL6 FAL5 FAL4 FAL3 FAL2 FAL1 FAL0 Last active line 7BH LAL7 LAL6 LAL5 LAL4 LAL3 LAL2 LAL1 LAL0 MSB vertical 7CH TTX60 LAL8 0 FAL8 TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8 Null 7DH 0 0 0 0 0 0 0 0 Disable TTX line 7EH LINE12 LINE11 LINE10 LINE9 LINE8 LINE7 LINE6 LINE5 Disable TTX line 7FH LINE20 LINE19 LINE18 LINE17 LINE16 LINE15 LINE14 LINE13 Note 1. All bits labelled ‘0’ are reserved. They must be programmed with logic 0. Product specification SAA7120H; SAA7121H TTX even request vertical end Philips Semiconductors SUBADDR Digital video encoder 2002 Oct 11 DATA BYTE(1) REGISTER FUNCTION Philips Semiconductors Product specification Digital video encoder 7.8 I2C-bus format Table 4 S SAA7120H; SAA7121H I2C-bus address; see Table 5 SLAVE ADDRESS Table 5 ACK SUBADDRESS ACK DATA 0 ACK -------- DATA n ACK P Explanation of Table 4 PART DESCRIPTION S START condition SLAVE ADDRESS 1000 100X or 1000 110X; note 1 ACK acknowledge, generated by the slave SUBADDRESS; note 2 subaddress byte DATA data byte -------- continued data bytes and ACKs P STOP condition Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read; no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. 7.9 Slave receiver Table 6 Subaddresses 26H and 27H DATA BYTE LOGIC LEVEL − WSS DESCRIPTION wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved WSSON Table 7 0 wide screen signalling output is disabled; default after reset 1 wide screen signalling output is enabled Subaddresses 28H and 29H DATA BYTE BS LOGIC LEVEL − DESCRIPTION starting point of burst in clock cycles REMARKS PAL: BS = 33 (21H); default after reset NTSC: BS = 25 (19H) BE − ending point of burst in clock cycles DECCOL 0 disable colour detection bit of RTCI input 1 enable colour detection bit of RTCI input 0 field sequence as FISE in subaddress 61 1 field sequence as FISE bit in RTCI input PAL: BE = 29 (1DH); default after reset NTSC: BE = 29 (1DH) DECFIS 2002 Oct 11 12 bit RTCE must be set to logic 1 (see Fig.9) bit RTCE must be set to logic 1 (see Fig.9) Philips Semiconductors Product specification Digital video encoder Table 8 Subaddresses 2AH to 2DH DATA BYTE DESCRIPTION CGO0 REMARKS first byte of copy guard data, odd field LSBs of the respective bytes are encoded immediately after run-in and framing code, second byte of copy guard data, odd field the MSBs of the respective bytes have to first byte of copy guard data, even field carry the parity bit, in accordance with the second byte of copy guard data, even field definition of line 20 encoding format CGO1 CGE0 CGE1 Table 9 SAA7120H; SAA7121H Subaddress 2EH DATA BYTE DESCRIPTION CCEN1 CCEN0 0 0 copy guard encoding off 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields Table 10 Subaddress 3AH DATA BYTE UV2C Y2C SYMP CBENB LOGIC LEVEL DESCRIPTION 0 CB, CR data are twos complement 1 CB, CR data are straight binary; default after reset 0 Y data is twos complement 1 Y data is straight binary; default after reset 0 horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset 1 horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP port 0 data from input ports is encoded; default after reset 1 colour bar with fixed colours is encoded Table 11 Subaddress 5AH DATA BYTE CHPS 2002 Oct 11 DESCRIPTION VALUE phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees 13 RESULT 00H PAL-B/G and data from input ports 2AH PAL-B/G and data from look-up table 88H NTSC-M and data from input ports AAH NTSC-M and data from look-up table Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H Table 12 Subaddresses 5BH and 5DH DATA BYTE GAINU DESCRIPTION variable gain for CB signal; input representation in accordance with “CCIR 601” CONDITIONS REMARKS white-to-black = 92.5 IRE GAINU = −2.17 × nominal to +2.16 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 118 (76H) output subcarrier of U contribution = nominal white-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 125 (7DH) output subcarrier of U contribution = nominal Table 13 Subaddresses 5CH and 5EH DATA BYTE GAINV DESCRIPTION variable gain for CR signal; input representation in accordance with “CCIR 601” CONDITIONS REMARKS white-to-black = 92.5 IRE GAINV = −1.55 × nominal to +1.55 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 165 (A5H) output subcarrier of V contribution = nominal white-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 175 (AFH) output subcarrier of V contribution = nominal Table 14 Subaddress 5DH DATA BYTE BLCKL DECOE DESCRIPTION variable black level; input representation in accordance with “CCIR 601” real-time control CONDITIONS white-to-sync = 140 IRE; note 1 recommended value: BLCKL = 42 (2AH) BLCKL = 0; note 1 output black level = 34 IRE BLCKL = 63 (3FH); note 1 output black level = 54 IRE white-to-sync = 143 IRE; note 2 recommended value: BLCKL = 35 (23H) BLCKL = 0; note 2 output black level = 32 IRE BLCKL = 63 (3FH); note 2 output black level = 52 IRE logic 0 disable odd/even field control bit from RTCI logic 1 enable odd/even field control bit from RTCI (see Fig.9) Notes 1. Output black level/IRE = BLCKL × 2/6.29 + 34.0. 2. Output black level/IRE = BLCKL × 2/6.18 + 31.7. 2002 Oct 11 REMARKS 14 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H Table 15 Subaddress 5EH DATA BYTE BLNNL DECPH DESCRIPTION variable blanking level real-time control CONDITIONS REMARKS white-to-sync = 140 IRE; note 1 recommended value: BLNNL = 46 (2EH) BLNNL = 0; note 1 output blanking level = 25 IRE BLNNL = 63 (3FH); note 1 output blanking level = 45 IRE white-to-sync = 143 IRE; note 2 recommended value: BLNNL = 53 (35H) BLNNL = 0; note 2 output blanking level = 26 IRE BLNNL = 63 (3FH); note 2 output blanking level = 46 IRE logic 0 disable subcarrier phase reset bit from RTCI logic 1 enable subcarrier phase reset bit from RTCI (see Fig.9) Notes 1. Output black level/IRE = BLNNL × 2/6.29 + 25.4. 2. Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35H. Table 16 Subaddress 5FH DATA BYTE DESCRIPTION BLNVB variable blanking level during vertical blanking interval is typically identical to value of BLNNL CCRS select cross-colour reduction filter in luminance; see Table 17 Table 17 Logic levels and function of CCRS CCRS1 CCRS0 0 0 no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5 0 1 cross-colour reduction #1 active; for overall transfer characteristic see Fig.5 1 0 cross-colour reduction #2 active; for overall transfer characteristic see Fig.5 1 1 cross-colour reduction #3 active; for overall transfer characteristic see Fig.5 2002 Oct 11 DESCRIPTION 15 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H Table 18 Subaddress 61H DATA BYTE FISE PAL SCBW YGS INPI DOWN LOGIC LEVEL DESCRIPTION 0 864 total pixel clocks per line; default after reset 1 858 total pixel clocks per line 0 NTSC encoding (non-alternating V component) 1 PAL encoding (alternating V component); default after reset 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); default after reset 0 luminance gain for white − black 100 IRE; default after reset 1 luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black 0 PAL switch phase is nominal; default after reset 1 PAL switch phase is inverted compared to nominal if RTC is enabled; see Table 19 0 DACs for CVBS, Y and C in normal operational mode; default after reset 1 DACs for CVBS, Y and C forced to lowest output voltage Table 19 Subaddress 62H DATA BYTE RTCE LOGIC LEVEL DESCRIPTION 0 no real-time control of generated subcarrier frequency; default after reset 1 real-time control of generated subcarrier frequency through SAA7151B or SAA7111; for timing see Fig.9 Table 20 Subaddress 62H DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with “CCIR 601” CONDITIONS REMARKS white-to-black = 92.5 IRE; recommended value: burst = 40 IRE; NTSC encoding BSTA = 63 (3FH) BSTA = 0 to 2.02 × nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding recommended value: BSTA = 45 (2DH) BSTA = 0 to 2.82 × nominal white-to-black = 100 IRE; recommended value: burst = 43 IRE; NTSC encoding BSTA = 67 (43H) BSTA = 0 to 1.90 × nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 × nominal 2002 Oct 11 16 recommended value: BSTA = 47 (2FH); default after reset Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H Table 21 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE FSC0 to FSC3 DESCRIPTION fsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) CONDITIONS f sc 32 FSC = round ------ × 2 ; f llc REMARKS FSC3 = most significant byte; FSC0 = least significant byte note 1 Note 1. Examples: a) NTSC-M: fsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH). b) PAL-B/G: fsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH). Table 22 Subaddresses 67H to 6AH DATA BYTE DESCRIPTION L21O0 first byte of captioning data, odd field L21O1 second byte of captioning data, odd field L21E0 first byte of extended data, even field L21E1 second byte of extended data, even field REMARKS LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format Table 23 Subaddress 6BH DATA BYTE PRCV2 ORCV2 CBLF LOGIC LEVEL DESCRIPTION 0 polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default after reset 1 polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively 0 pin RCV2 is switched to input; default after reset 1 pin RCV2 is switched to output 0 if ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset 1 if ORCV2 = HIGH, pin RCV2 provides a ‘composite-blanking-not’ signal, for example a reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval, which is defined by FAL and LAL if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal PRCV1 ORCV1 TRCV2 SRCV1 2002 Oct 11 0 polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset 1 polarity of RCV1 as output is active LOW, falling edge is taken when input 0 pin RCV1 is switched to input; default after reset 1 pin RCV1 is switched to output 0 horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded frame sync of “CCIR 656” input (at bit SYMP = HIGH); default after reset 1 horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW) − defines signal type on pin RCV1; see Table 24 17 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H Table 24 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT AS INPUT 0 VS VS vertical sync each field; default after reset 1 FS FS frame sync (odd/even) 1 0 FSEQ FSEQ 1 1 − − SRCV11 SRCV10 0 0 FUNCTION field sequence, vertical sync every fourth field (PAL = 0) or eighth field (PAL = 1) not applicable Table 25 Subaddresses 6CH and 6DH DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals; reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 398H (398H) Table 26 Subaddress 6DH DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 to 31 (1FH) Table 27 Subaddress 6EH DATA BYTE LOGIC LEVEL SBLBN 0 DESCRIPTION vertical blanking is defined by programming of FAL and LAL; default after reset 1 vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz) PHRES − selects the phase reset mode of the colour subcarrier generator; see Table 28 FLC − field length control; see Table 29 Table 28 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 PHRES0 0 0 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset 0 1 reset every two lines 1 0 reset every eight fields 1 1 reset every four fields 2002 Oct 11 18 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H Table 29 Logic levels and function of FLC DATA BYTE DESCRIPTION FLC1 FLC0 0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset 0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz 1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz 1 1 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz Table 30 Subaddress 6FH DATA BYTE LOGIC LEVEL DESCRIPTION CCEN − enables individual line 21 encoding; see Table 31 TTXEN 0 disables teletext insertion; default after reset 1 enables teletext insertion − selects the actual line, where closed caption or extended data are encoded; line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems SCCLN Table 31 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 CCEN0 0 0 line 21 encoding off; default after reset 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields Table 32 Subaddresses 70H to 72H DATA BYTE RCV2S DESCRIPTION start of output signal on pin RCV2 values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2S = 11AH (0FDH) RCV2E end of output signal on pin RCV2 values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2E = 694H (687H) Table 33 Subaddresses 73H and 74H DATA BYTE TTXHS DESCRIPTION REMARKS start of signal on pin TTXRQ; see Fig.10 PAL: TTXHS = 42H NTSC: TTXHS = 54H TTXHD 2002 Oct 11 indicates the delay in clock cycles between rising edge of TTXRQ output and valid data at pin TTX 19 minimum value: TTXHD = 2 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H Table 34 Subaddress 75H DATA BYTE VS_S DESCRIPTION REMARKS vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is possible to shift Hsync (RCV2; CBLF = 0) against Vsync (RCV1; SRCV1 = 00) standard value: VS_S = 3 Table 35 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS DESCRIPTION REMARKS first line of occurrence of signal on pin TTXRQ in odd field line = (TTXOVS + 4) for M-systems PAL: TTXOVS = 05H; NTSC: TTXOVS = 06H line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal on pin TTXRQ in odd field line = (TTXOVE + 3) for M-systems PAL: TTXOVE = 16H; NTSC: TTXOVE = 10H line = TTXOVE for other systems Table 36 Subaddresses 78H, 79H and 7CH DATA BYTE TTXEVS DESCRIPTION REMARKS first line of occurrence of signal on pin TTXRQ in even field line = (TTXEVS + 4) for M-systems PAL: TTXEVS = 04H; NTSC: TTXEVS = 05H line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal on pin TTXRQ in even field line = (TTXEVE + 3) for M-systems PAL: TTXEVE = 16H; NTSC: TTXEVE = 10H line = TTXEVE for other systems Table 37 Subaddresses 7AH to 7CH DATA BYTE FAL DESCRIPTION first active line: measured in lines; FAL = 0 coincides with the first field synchronization pulse first active line = (FAL + 4) for M systems first active line = (FAL + 1) for other systems LAL last active line: measured in lines; LAL = 0 coincides with the first field synchronization pulse last active line = (LAL + 3) for M-systems last active line = LAL for other systems Table 38 Subaddress 7CH DATA BYTE TTX60 2002 Oct 11 LOGIC LEVEL DESCRIPTION 0 enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset 1 enables world standard teletext 60 Hz (FISE = 1) 20 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H Table 39 Subaddresses 7EH and 7FH DATA BYTE LINE DESCRIPTION individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate); this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up. 7.10 Slave transmitter Table 40 Slave transmitter (slave address 89H or 8DH) REGISTER FUNCTION Status byte DATA BYTE SUBADDRESS − D7 D6 D5 VER2 VER1 VER0 D4 D3 CCRDO CCRDE D2 D1 D0 FSEQ2 FSEQ1 O_E Table 41 No subaddress DATA BYTE VER CCRDO LOGIC LEVEL DESCRIPTION − version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 001 binary 1 closed caption bytes of the odd field have been encoded 0 the bit is reset after information has been written to the subaddresses 67H and 68H; it is set immediately after the data has been encoded 1 closed caption bytes of the even field have been encoded 0 the bit is reset after information has been written to the subaddresses 69H and 6AH; it is set immediately after the data has been encoded FSEQ − state of the internal field sequence counter, with bit O_E as LSB (repetition rate: NTSC = 4 fields, PAL = 8 fields) O_E 1 during even field 0 during odd field CCRDE 2002 Oct 11 21 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H MBE737 handbook, full 6 pagewidth Gv (dB) 0 −6 −12 −18 −24 (1) (2) −30 −36 −42 −48 −54 0 2 4 6 8 10 (1) SCBW = 1. (2) SCBW = 0. Fig.3 Chrominance transfer characteristic 1. MBE735 handbook, halfpage 2 Gv (dB) 0 (1) (2) −2 −4 −6 0 0.4 0.8 1.2 f (MHz) 1.6 (1) SCBW = 1. (2) SCBW = 0. Fig.4 Chrominance transfer characteristic 2. 2002 Oct 11 22 12 f (MHz) 14 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H MGD672 6 Gv full pagewidth handbook, (dB) (4) 0 (2) (3) −6 (1) −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 14 f (MHz) (1) CCRS1 = 0; CCRS0 = 1. (2) CCRS1 = 1; CCRS0 = 0. (3) CCRS1 = 1; CCRS0 = 1. (4) CCRS1 = 0; CCRS0 = 0. Fig.5 Luminance transfer characteristic 1. MBE736 handbook, halfpage 1 Gv (dB) (1) 0 −1 −2 −3 −4 −5 0 2 4 f (MHz) 6 (1) CCRS1 = 0; CCRS0 = 0. Fig.6 Luminance transfer characteristic 2. 2002 Oct 11 23 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H 8 CHARACTERISTICS VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Supply VDDA analog supply voltage 3.1 3.5 V VDDD digital supply voltage 3.0 3.6 V IDDA analog supply current note 1 − 62 mA IDDD digital supply current VDDD = 3.3 V; note 1 − 45 mA Inputs: LLC, RCV1, RCV2, MP7 to MP0, RTCI, SA, RESET and TTX VIL LOW-level input voltage −0.5 +0.8 V VIH HIGH-level input voltage 2.0 VDDD + 0.3 V ILI input leakage current Ci input capacitance − 1 µA clocks − 10 pF data − 8 pF I/Os at high-impedance − 8 pF Outputs: RCV1, RCV2 and TTXRQ VOL LOW-level output voltage IOL = 2 mA − 0.4 V VOH HIGH-level output voltage IOH = −2 mA 2.4 − V −0.5 +0.3VDDD V I2C-bus: SDA and SCL VIL LOW-level input voltage VIH HIGH-level input voltage 0.7VDDD VDDD + 0.3 V Ii input current Vi = LOW or HIGH −10 +10 µA VOL LOW-level output voltage (pin SDA) IOL = 3 mA − 0.4 V Io output current during acknowledge 3 − mA Clock timing: LLC TLLC cycle time note 2 34 41 ns δ duty factor tHIGH/TLLC note 3 40 60 % tr rise time note 2 − 5 ns tf fall time note 2 − 6 ns Input timing: RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX tSU;DAT input data set-up time 6 − ns tHD;DAT input data hold time 3 − ns 2002 Oct 11 24 Philips Semiconductors Product specification Digital video encoder SYMBOL SAA7120H; SAA7121H PARAMETER CONDITIONS MIN. MAX. UNIT Crystal oscillator fn nominal frequency (usually 27 MHz) 3rd harmonic − ∆f/fn permissible deviation of nominal frequency note 4 −50 × 10−6 +50 × 10−6 30 MHz CRYSTAL SPECIFICATION Tamb ambient temperature 0 70 °C CL load capacitance 8 − pF RS series resistance − 80 Ω C1 motional capacitance (typical) 1.5 − 20% 1.5 + 20% fF C0 parallel capacitance (typical) 3.5 − 20% 3.5 + 20% pF Data and reference signal output timing CL output load capacitance 7.5 40 pF th output hold time 4 − ns td output delay time − 25 ns 1.25 1.50 V C, Y and CVBS outputs Vo(p-p) output signal voltage (peak-to-peak value) note 5 Rint internal serial resistance 1 3 Ω RL output load resistance 75 300 Ω B output signal bandwidth of DACs 10 − MHz LElf(i) low frequency integral linearity error of DACs − ±3 LSB LElf(d) low frequency differential linearity error of DACs − ±1 LSB −3 dB Notes 1. At maximum supply voltage with highly active input signals. 2. The data is for both input and output direction. 3. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 4. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 5. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V. 2002 Oct 11 25 Philips Semiconductors Product specification Digital video encoder handbook, full pagewidth SAA7120H; SAA7121H TLLC tHIGH 2.6 V 1.5 V 0.6 V LLC clock output tHD; DAT tf tr TLLC tHIGH 2.4 V 1.5 V 0.8 V LLC clock input tSU; DAT tHD; DAT tf tr 2.0 V input data valid valid not valid 0.8 V td tHD; DAT 2.4 V output data valid valid not valid 0.6 V MBE742 Fig.7 Clock data timing. handbook, full pagewidth LLC MP(n) CB(0) CR(0) Y(0) Y(1) CB(2) RCV2 MGB699 The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to 262 for 50 Hz and to 234 for 60 Hz in this example in output mode (RCV2S). Fig.8 Functional timing. 2002 Oct 11 26 Philips Semiconductors Product specification Digital video encoder 8.1 SAA7120H; SAA7121H Explanation of RTCI data bits 6. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the SAA7120H; SAA7121H ignores its internally generated odd/even flag and takes the odd/even bit from RTCI input. 1. The HPLL increment is not evaluated by the SAA7120H; SAA7121H. 2. The SAA7120H; SAA7121H generates the subcarrier frequency from the FSCPLL increment if enabled (see item 7.). 7. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0), the subcarrier frequency is generated by the SAA7120H; SAA7121H. In the other case (colour detection bit = 1) the subcarrier frequency is evaluated out of FSCPLL increment. 3. The PAL bit indicates the line with inverted (R − Y) component of colour difference signal. 4. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line whenever the reset bit of RTCI input is set to logic 1. If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL increment, independent of the colour detection bit of RTCI input. 5. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7120H; SAA7121H takes this bit instead of the FISE bit in subaddress 61H. HIGH-to-LOW transition handbook, full pagewidth LOW 128 RTCI 13 time slot: 0 1 3 bits reserved 4 bits reserved count start HPLL increment (1) 0 14 22 19 64 valid sample (1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment. (2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit. (3) Sequence bit: PAL: 0 = (R − Y) line normal, 1 = (R − Y) line inverted; NTSC: 0 = no change. (4) Reset bit: only from SAA7111 and SAA7112 decoder. FISE bit: 0 = 50 Hz, 1 = 60 Hz. Odd/even bit: odd_even from external. Colour detection: 0 = no colour detected, 1 = colour detected. Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems. Fig.9 RTCI timing. 2002 Oct 11 (5) (7) (3) (6) 67 69 68 72 74 0 not used in SAA7120H/21H (5) (6) (7) (8) (4) FSCPLL increment (2) 27 invalid sample 8/LLC MBH789 (8) Philips Semiconductors Product specification Digital video encoder 8.2 SAA7120H; SAA7121H Time tTTXWin is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (WST) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is logic 0. Teletext timing Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and Y output signal, such that it appears at tTTX = 9.78 µs (PAL) or tTTX = 10.5 µs (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ, a new teletext bit must be provided by the source. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of outgoing horizontal synchronization pulse. handbook, full pagewidth CVBS/Y tTTX textbit #: 1 tTTXWin 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TTX tPD tFD TTXRQ MBH788 Fig.10 Teletext timing. 2002 Oct 11 28 24 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 10 µH 1 nF +3.3 V analog 0.1 µF AGND 10 pF 10 pF 0.1 µF 27.0 MHz X1 0.1 µF AGND DGND 0.1 µF 0.1 µF AGND 3rd harmonic XTALI XTALO 35 34 AGND VDDD1, VDDD2, VDDD3 6, 17, 39 use one capacitor for each VDDD VDDA4 VDDA1 VDDA2 VDDA3 36 25 28 31 2 Ω (1) DAC1 30 CVBS 4.7 Ω 29 75 Ω 2 Ω (1) DAC2 27 Y 10 Ω 75 Ω digital inputs and outputs SAA7120H SAA7121H 2 Ω (1) DAC3 24 C 10 Ω UCVBS 1.23 V (p-p)(2) AGND UY 1.00 V (p-p)(2) AGND UC 0.89 V (p-p)(2) AGND 5, 18, 38 32, 33 VSSD1, VSSD2, VSSD3 VSSA1, VSSA2 AGND Fig.11 Application circuit. MBH786 Product specification handbook, full pagewidth DGND SAA7120H; SAA7121H 75 Ω (1) Typical value. (2) For 100⁄100 colour bar. Digital video encoder APPLICATION INFORMATION +3.3 V digital Philips Semiconductors 9 2002 Oct 11 DGND Philips Semiconductors Product specification Digital video encoder 9.1 SAA7120H; SAA7121H Analog output voltages The analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion (typical value 1.35 V), the internal series resistor (typical value 2 Ω), the external series resistor and the external load impedance. The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated in Table 42 for a 100⁄100 colour bar signal. Values for the external series resistors result in a 75 Ω load. Table 42 Digital output signals conversion range CONVERSION RANGE (peak-to-peak) CVBS SYNC-TIP TO PEAK-CARRIER (digits) Y (VBS) SYNC-TIP TO WHITE (digits) 1016 881 2002 Oct 11 30 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H 10 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 2002 Oct 11 EUROPEAN PROJECTION 31 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H If wave soldering is used the following conditions must be observed for optimal results: 11 SOLDERING 11.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 11.2 – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. 11.3 11.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2002 Oct 11 Manual soldering 32 Philips Semiconductors Product specification Digital video encoder 11.5 SAA7120H; SAA7121H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Oct 11 33 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H 12 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 13 DEFINITIONS 14 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 Oct 11 34 Philips Semiconductors Product specification Digital video encoder SAA7120H; SAA7121H 15 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2002 Oct 11 35 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA74 © Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753505/02/pp36 Date of release: 2002 Oct 11 Document order number: 9397 750 09829