ATMEL U2790B

Features
• Supply Voltage 5V (Typically)
• Very Low Power Consumption: 150 mW (Typically) for –1 dBm Output Level
• Very Good Sideband Suppression by Means of Duty Cycle Regeneration of the LO
•
•
•
•
•
•
Input Signal
Phase Control Loop for Precise 90° Phase Shifting
Power-down Mode
Low LO Input Level: –10 dBm (Typically)
50-Ω Single-ended LO and RF Port
LO Frequency from 100 MHz to 1 GHz
SO16 Package
1000-MHz
Quadrature
Modulator
Benefits
• No External Components Required for Phase Shifting
• Adjustment Free, Hence Saves Manufacturing Time
• Only Three External Components Necessary, this Results in Cost and Board Space
Saving
U2790B
Electrostatic sensitive device.
Observe precautions for handling.
1. Description
The U2790B is a 1000-MHz quadrature modulator using Atmel®’s advanced UHF process. It features a frequency range from 100 MHz up to 1000 MHz, low current
consumption, and single-ended RF and LO ports. Adjustment-free application makes
the direct converter suitable for all digital radio systems up to 1000 MHz, e.g., GSM,
ADC, JDC.
Figure 1-1.
Block Diagram
SPU
BBAI
8
BBAI
12
15
Phadj
1
Power
up
7
LO i
PU
6
Duty cycle
regenerator
Frequency
doubler
0°
90°
90°/control
loop
VS
5,4
RFO
Σ
3
16
BBBi
9
BBBI
10
2,11,13,14
GND
4583D–CELL–07/06
2. Pin Configuration
Figure 2-1.
Table 2-1.
2
Pinning SO16
PU
1
16
Phadj
GND
2
15
Phadj
RFO
3
14
GND
VS
4
13
GND
VS
5
12
LOi
SPD
6
11
GND
BBAi
7
10
BBBi
BBAi
8
9
BBBi
Pin Description
Pin
Symbol
Function
1
PU
2, 11, 13, 14
GND
Ground
3
RFo
RF output
4, 5
VS
Supply voltage
6
SPU
Settling time power-up
7
BBAi
Baseband input A
8
BBAi
Baseband input A inverse
9
BBBi
Baseband input B
10
BBBi
Baseband input B inverse
12
LOi
LO input
15, 16
Phadj
Power-up input
Phase adjustment (not necessary for regular applications)
U2790B
4583D–CELL–07/06
U2790B
3. Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Supply voltage
VS
6
V
Input voltage
Vi
0 to VS
V
Junction temperature
Tj
125
°C
TStg
–55 to +125
°C
Symbol
Value
Unit
Storage temperature range
4. Operating Range
Parameters
Supply voltage range
Ambient temperature range
VS
4.5 to 5.5
V
Tamb
–40 to +85
°C
Symbol
Value
Unit
RthJA
110
K/W
5. Thermal Resistance
Parameters
Junction ambient SO16
6. Electrical Characteristics
Test conditions (unless otherwise specified): VS = 5V, Tamb = 25°C, referred to test circuit, system impedance ZO = 50Ω, fLO = 900 MHz,
PLO = –10 dBm, VBBi = 1 Vpp differential.
No.
Parameters
1.1
1.2
Test Conditions
Pin
Symbol
Min.
Supply voltage range
4, 5
VS
4.5
Supply current
4, 5
IS
24
7-8,
9-10
Typ.
Max.
Unit
Type*
5.5
V
A
30
37
mA
A
VBBi
1000
1500
mVpp
D
3.2
kΩ
D
250
MHz
D
2.5
2.65
V
A
0.1
<1
mV/°C
D
2
Baseband Inputs
2.1
Input-voltage range
(differential)
2.2
Input impedance
(single ended)
ZBBi
2.3
Input-frequency
range(5)
fBBi
0
2.4
Internal bias voltage
VBBb
2.35
2.5
Temperature
coefficient
TCBB
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. The required LO level is a function of the LO frequency.
2. In reference to an RF output level ≤ –1 dBm and I/Q input level of 400 mVpp differential.
3. Sideband suppression is tested without connection at pins 15 and 16. For higher requirements a potentiometer can be
connected at these pins.
4. For Tamb = –30°C to +85°C and VS = 4.5V to 5.5V.
5. By low impedance signal source.
3
4583D–CELL–07/06
6. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 5V, Tamb = 25°C, referred to test circuit, system impedance ZO = 50Ω, fLO = 900 MHz,
PLO = –10 dBm, VBBi = 1 Vpp differential.
No.
3
3.1
Parameters
Test Conditions
Pin
Symbol
Min.
12
fLOi
50
PLOi
–12
Typ.
Frequency range
(1)
–10
3.2
Input level
Input impedance
ZiLO
50
3.4
Voltage standing
wave ratio
VSWRLO
1.4
Duty cycle range
DCRLO
0.4
PRFo
–5
–1
4
RF Output
4.1
Output level
4.2
LO suppression(2)
fLO = 900 MHz
fLO = 150 MHz
LORFo
30
32
4.3
Sideband
suppression(2, 3)
fLO = 900 MHz
fLO = 150 MHz
SBSRFo
35
30
4.4
Phase error(4)
4.5
Amplitude error
3
1000
MHz
D
–5
dBm
D
Ω
D
VBBi = 2V, VBBi = 3V
VBBi = VBBi = 2.5V
2
D
0.6
D
B
35
35
dB
B
40
35
dB
B
Pe
<1
deg.
D
Ae
< ±0.25
dB
D
NFL
–132
–144
dBm/Hz
D
VSWRRF
1.6
Noise floor
4.7
VSWR
4.8
3rd-order baseband
harmonic
suppression
SBBH
4.9
RF harmonic
suppression
35
+2
2
D
45
dB
D
SRFH
35
dB
D
4, 5
IPU
10
µA
D
6 to 3
tsPU
10
µs
D
Power-up Mode
5.1
Supply current
VPU ≤ 0.5V
VPU = 1V
5.2
Settling time
CSPU = 100 pF
CLO = 100 pF
CRFo = 1 nF
6
Type*
dBm
4.6
5
Unit
LO Input
3.3
3.5
Max.
1
Switching Voltage
6.1
Power-on
1
VPUon
6.2
Power-up
1
VPUdown
4
1
V
D
V
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. The required LO level is a function of the LO frequency.
2. In reference to an RF output level ≤ –1 dBm and I/Q input level of 400 mVpp differential.
3. Sideband suppression is tested without connection at pins 15 and 16. For higher requirements a potentiometer can be
connected at these pins.
4. For Tamb = –30°C to +85°C and VS = 4.5V to 5.5V.
5. By low impedance signal source.
4
U2790B
4583D–CELL–07/06
U2790B
7. Diagrams
Figure 7-1.
Typical Single Sideband Output Spectrum at VS = 4.5V and VS = 5.5V,
fLO = 900 MHz, PLO = –10 dBm, VBBI = 1 VPP (differential) Tamb = 25°C
Figure 7-2.
Typical GMSK Output Spectrum
5
4583D–CELL–07/06
Figure 7-3.
Demo Board Layout
Figure 7-4.
OIP3 versus Tamb, LO = 150 MHz, Level –20 dBm
16
VBBI = 0.2 VPP
IP3 (dBm)
12
VBBi= 0.4 VPP
8
4
0
-40
-20
0
20
40
60
80
100
Temperature (°C)
6
U2790B
4583D–CELL–07/06
U2790B
Figure 7-5.
OIP3 versus Tamb, LO = 900 MHz, Level –10 dBm
12
10
IP3 (dBm)
VBBi = 0.4 VPP
8
6
VBBi = 1.0 VPP
4
2
0
-40
-20
0
20
40
60
80
100
Temperature (°C)
Figure 7-6.
Output Power versus Tamb
0.5
Output Power (dBm)
0
FLO = 150 MHz
-0,5
-1
-1.5
FLO = 900 MHz
-2
-2.5
-40
-20
0
20
40
60
80
100
Temperature (°C)
Figure 7-7.
Supply Current versus Tamb
Supply Current (mA)
40
30
20
10
0
-40
-20
0
20
40
60
80
100
Temperature (°C)
7
4583D–CELL–07/06
8
Figure 7-8.
Typical S11 Frequency Response of the RF Output
Figure 7-9.
Typical VSWR Frequency Response of the RF Output
U2790B
4583D–CELL–07/06
U2790B
Figure 7-10. Typical S11 Frequency Response of the LO Input
Figure 7-11. Typical VSWR Frequency Response of the LO input
10
VSWR
8
6
4
2
0
1000
100
LO Frequency (MHz)
9
4583D–CELL–07/06
Figure 7-12. Typical Supply Current versus Temperature at VS = 5V
Supply Current ( mA )
60
50
40
30
20
10
-40
-20
0
20
40
60
80
100
Temperature (°C)
Figure 7-13. Typical Output Power versus LO-Frequency at Tamb = 25°C,
VBBI = 230 mVPP (differential)
Output Power ( dBm )
0
-5
0
200
400
600
800
1000 1200 1400
LO Frequency ( MHz )
Figure 7-14. Typical required VBBi Input Signal (differential) versus LO Frequency for
PO = 0 dBm and PO = –2 dBm
VBBi (differential) (VPP)
2
1
0
0
200
400
600
800 1000 1200 1400
LO Frequency (MHz)
10
U2790B
4583D–CELL–07/06
U2790B
Figure 7-15. Typical useful LO Power Range versus LO Frequency at Tamb = 25° C
0
LO Power (dBm)
-10
-20
-30
-40
-50
0
200
400
600
800 1000
1200 1400
LO Frequency (MHz)
Figure 7-16. Application Circuit
PU
1n
CPU
A inv
SPU
Power
down
220n
A
220n BBAi
1
6
8
Power
down 5,4
7
BBAi
Baseband
100p
LO
processing
12
10k
VS
LOi
Phadj
B
220n
BBBi
Duty cycle
regenerator
Frequency
doubler
0°
90°
90°/ control
loop
VS
VS
100n
1n
Σ
3
15
OUT
RFO
16
9
10
BBBi
2,11,13,14
220n
Binv
GND
11
4583D–CELL–07/06
Figure 7-17. Demo Board Layout
12
U2790B
4583D–CELL–07/06
U2790B
8. Application Notes
8.1
Noise Floor and Settling Time
In order to reduce noise on the power-up control input and improve the wide-off noise floor of the
900-MHz RF output signal, capacitor CPU should be connected from pin 6 to ground in the
shortest possible way.
The settling time has to be considered for the system under design. For GSM applications, a
value of CPU = 1 nF defines a settling time, tsPU, equal or less than 3 ms. This capacitance does
not have any influence on the noise floor within the relevant GSM mask. For mobile applications
the mask requirements can be achieved very easily without CPU.
A significant improvement of the wide-off noise floor is obtainable with CPU greater than 100 nF.
Such values are recommended for applications where the settling time is not critical such as in
base stations. Coupling capacitors for LOi and RFO also have a certain impact on the settling
time. The values used for the measurements are CLOi = 100 pF and CRFo = 1 nF.
8.2
Baseband Coupling
The U2790B-FP (SO16) has an integrated biasing network which allows AC coupling of the
baseband signal at a low count of external components. The bias voltage is 2.5V ±0.15V.
Figure 7-17 shows the baseband input circuitry with a resistance of 3.2 kΩ for each asymmetric
input. The internal DC offset between A and A, and B and B is typically < ±1 mV with a maximum
of ±3 mV. DC coupling is also possible with an external DC voltage of 2.5 ±0.15V.
Figure 8-1.
Baseband Input Circuitry
Mixer input stage
3.2 kΩ
A
A
,
B
,
B
13
4583D–CELL–07/06
RF Output Circuitry LO Input Circuitry
VS
RFO
20 Ω
Figure 8-2.
3
LO Input Circuitry
LO
12
50 Ω
20 pF
14
U2790B
4583D–CELL–07/06
U2790B
9. Ordering Information
Extended Type Number
Package
Remarks
U2790B-NFPH
SO16
Tube, Pb-free
U2790B-NFPG3H
SO16
Taped and reeled, Pb-free
10. Package Information
Package SO16
Dimensions in mm
5.2
4.8
10.0
9.85
3.7
1.4
0.25
0.10
0.4
1.27
0.2
3.8
6.15
5.85
8.89
16
9
technical drawings
according to DIN
specifications
1
8
11. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4583D-CELL-07/06
• Page 3, Abs. Max.Ratings table: Storage temperature values changed
• Page 2, Pin Description table: symbol of Pins 8 and 10 changed
• Put datasheet in a new template
15
4583D–CELL–07/06
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4583D–CELL–07/06