PHILIPS TZA3044U

INTEGRATED CIRCUITS
DATA SHEET
TZA3044T; TZA3044U
1.25 Gbits/s Gigabit Ethernet
postamplifiers
Objective specification
File under Integrated Circuits, IC19
1998 Jul 07
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
FEATURES
APPLICATIONS
• Pin compatible with the NE/SA5224 and NE/SA5225 but
with extended power supply range and less external
component count
• Digital fibre optic receiver for Gigabit Ethernet
applications
• Wideband RF gain block.
• Wideband operation from 1.0 kHz to 1.25 GHz typical
• Applicable in 1.25 Gbits/s Gigabit Ethernet receivers
GENERAL DESCRIPTION
• Single supply voltage from 3.0 to 5.5 V
The TZA3044 is a high gain limiting amplifier that is
designed to process signals from fibre optic preamplifiers
like the TZA3043. It is pin compatible with the NE/SA5224
and NE/SA5225 but with extended power supply range,
and needs less external components. Capable of
operating at 1.25 Gbits/s, the chip has input signal level
detection with a user-programmable threshold. The data
and level-detection status outputs are differential outputs
for optimum noise margin and ease of use.
• PECL (Positive Emitter Coupled Logic) compatible data
outputs
• Programmable input signal level-detection to be
adjusted using a single external resistor
• On-chip DC offset compensation without external
capacitor
• Fully differential for excellent PSRR.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TZA3044T
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
TZA3044U
naked die
die in waffle pack carriers; die dimensions 1.58 × 1.58 mm
−
BLOCK DIAGRAM
TEST
handbook, full pagewidth
2
(2, 10, 15, 21, 26)
DC-OFFSET
COMPENSATION
DIN
DINQ
TZA3044
(24) 13
4 (7)
A1
5 (8)
A2
A3
(23) 12
(16) 8
25 kΩ
DOUT
DOUTQ
JAM
RECTIFIER
(18) 10
RSET
Vref
16 (30)
15 (29)
A4
1 kΩ
(1, 14)
1
SUB
(11, 12)
6
(13)
7
VCCA
CF
(19, 20, 22, 25)
11
DGND
The numbers in brackets refer to the pad numbers of the naked die version.
Fig.1 Block diagram.
1998 Jul 07
ST
STQ
BAND GAP
REFERENCE
(3, 4, 6, 9)
3
AGND
(17) 9
2
(27, 28)
14
VCCD
MGR240
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
SUB
1
substrate
substrate pin; must be at the same potential as AGND (pin 3)
TEST
2
test pin
for test purpose only; to be left open in the application
AGND
3
ground
analog ground; must be at the same potential as DGND (pin 11)
DIN
4
analog input
differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DINQ (pin 5)
DINQ
5
analog input
differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DIN (pin 4)
VCCA
6
supply
analog supply voltage; must be at the same potential as VCCD (pin 14)
CF
7
analog input
filter capacitor for input signal level detector; capacitor should be connected
between this pin and VCCA (pin 6)
JAM
8
PECL input
PECL-compatible input; controls the output buffers DOUT and DOUTQ
(pins 13 and 12). When a LOW signal is applied, the outputs will follow the input
signal. When a HIGH signal is applied, the DOUT and DOUTQ pins will latch into
LOW and HIGH states, respectively. When left unconnected, this pin is actively
pulled LOW (JAM OFF).
STQ
9
PECL output
PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is HIGH;
complimentary to ST (pin 10)
ST
10
PECL output
PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is LOW;
complimentary to STQ (pin 9)
DGND
11
ground
digital ground; must be at the same potential as AGND (pin 3)
DOUTQ
12
PECL output
PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a HIGH condition; complimentary to DOUT (pin 13)
DOUT
13
PECL output
PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a LOW condition; complimentary to DOUTQ (pin 12)
VCCD
14
supply
digital supply voltage; must be at the same potential as VCCA (pin 6)
Vref
15
analog output band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 kΩ
RSET
16
analog input
1998 Jul 07
input signal level detector programming; nominal DC voltage is VCCA − 1.5 V;
threshold level is set by connecting an external resistor between RSET and VCCA
or by forcing a current into RSET; default value for this resistor is 180 kΩ which
corresponds with approximately 4 mV (p-p) differential input signal
3
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
PAD CONFIGURATION
Pad centre locations
COORDINATES(1)
handbook, halfpage
SUB 1
SYMBOL
16 RSET
x
y
1
−235.7
+647.8
2
−392.8
+647.8
3
−532.8
+647.8
4
−647.8
+507.1
n.c.
5
−647.8
+350.0
AGND
6
−647.8
+210.0
DIN
7
−647.8
+70.0
DINQ
8
−647.8
−70.0
AGND
9
−647.8
−210.0
TEST
10
−647.8
−350.0
VCCA
11
−647.8
−507.1
VCCA
12
−532.8
−647.8
CF
13
−392.8
−647.8
SUB
14
−235.7
−647.8
TEST
15
−78.6
−647.8
JAM
16
+61.4
−647.8
STQ
17
+218.5
−647.8
ST
18
+375.6
−647.8
DGND
19
+532.7
−647.8
DGND
20
+647.8
−507.1
TEST
21
+647.8
−350.0
DGND
22
+647.8
−210.0
DOUTQ
23
+647.8
−70.0
DOUT
24
647.8
70.0
DGND
25
647.8
210.0
TEST
26
647.8
350.0
15 Vref
SUB
14 VCCD
TEST
13 DOUT
AGND
DINQ 5
12 DOUTQ
AGND
VCCA 6
11 DGND
TEST 2
AGND 3
DIN 4
TZA3044T
CF 7
10 ST
JAM 8
9
STQ
MGR241
Fig.2 Pin configuration.
PAD
VCCD
27
647.8
507.1
VCCD
28
532.7
647.8
Vref
29
392.7
647.8
RSET
30
235.6
647.8
n.c.
31
78.5
647.8
n.c.
32
−78.6
+647.8
Note
1. Coordinates represent the position of the centre of the
pad, in µm, with respect to the centre of the die.
1998 Jul 07
4
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
SUB
n.c.
n.c.
RSET
Vref
VCCD
3
2
1
32
31
30
29
28
AGND
4
27
VCCD
n.c.
5
26
TEST
AGND
6
25
DGND
DIN
7
24
DOUT
0
23
DOUTQ
y
22
DGND
21
TEST
20
DGND
11
12
13
14
15
16
17
18
19
DGND
VCCA
ST
10
STQ
TEST
TZA3044U
JAM
9
TEST
AGND
SUB
8
0
CF
DINQ
x
VCCA
1.58(1)
mm
TEST
handbook, full pagewidth
AGND
Bonding pad locations
1.58 mm(1)
MGR242
(1) Typical value.
Pad size: 90 × 90 µm.
Fig.3 Bonding pad locations: TZA3044U.
The outcome of this test is available at the PECL
outputs ST and STQ. This flag can also be used to prevent
the PECL outputs DOUT and DOUTQ from reacting to
noise in the absence of a valid input signal, by connecting
the output STQ to the input JAM. This insures that data will
only be transmitted when the input signal-to-noise ratio is
sufficient for low bit error rate system operation.
FUNCTIONAL DESCRIPTION
The TZA3044 accepts up to 1.25 Gbits/s Gigabit Ethernet
data streams, with amplitudes from 2 mV (p-p) up to
1 V (p-p) single-ended. The input signal will be amplified
and limited to differential PECL output levels (see Fig.1).
The input buffer A1 presents an impedance of
approximately 4.5 kΩ to the data stream on the inputs DIN
and DINQ. The input can be used both single-ended and
differential, but differential operation is preferred for better
performance.
PECL logic
The logic level symbol definitions for PECL are shown in
Fig.4.
Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3044, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.
Input biasing
The input pins DIN and DINQ are DC biased at
approximately 2.55 V by an internal reference generator
(see Fig.5). The TZA3044 can be DC coupled, but AC
coupling is preferred. In case of DC coupling, the driving
source must operate within the allowable input signal
range (2.0 V to VCCA + 0.5 V). Also a DC offset voltage of
An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
1998 Jul 07
5
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
Since the voltage on pin RSET is held constant at 1.5 V
below VCCA, the current flowing into this pin will be:
1.5
I RSET = ------------------------ [ A ]
(2)
R DETECT
more than a few millivolt should be avoided, since the
internal DC offset compensation circuit has a limited
correction range.
If AC coupling is used to remove any DC compatibility
requirement, the coupling capacitors must be large
enough to pass the lowest input frequency of interest.
For example, 1 nF coupling capacitors react with the
internal 4.5 kΩ input bias resistors to yield a lower −3 dB
frequency of 35 kHz. This then sets a limit on the
maximum number of consecutive pulses that can be
sensed accurately at the system data rate. Capacitor
tolerance and resistor variation must be included for an
accurate calculation.
Combining these two formulas results in a general formula
to calculate RDETECT for a given input signal
level-detection:
750
(3)
R DETECT = ------------------------------------------ [ Ω ]
( V DIN – V DINQ )
In this formula, VDIN and VDINQ are in V (p-p).
Example: Detection should occur if the differential voltage
of the input signals drops below 4 mV (p-p). In this case, a
reference current of 0.002 × 0.004 = 8 µA should flow into
pin RSET. This can be set using a current source or simply
by connecting a resistor of the appropriate value.
The resistor must be connected between VCCA and
pin RSET. In this example the resistor would be:
750
R DETECT = ----------------- = 187.5 kΩ
0.004
DC-offset compensation
A control loop connected between the inputs of buffer A3
and amplifier A1 (see Fig.1) will keep the input of buffer A3
at its toggle point in the absence of any input signal.
Because of the active offset compensation which is
integrated in the TZA3044, no external capacitor is
required. The loop time constant determines the lower
cut-off frequency of the amplifier chain, which is set at
approximately 850 Hz.
The hysteresis is fixed internally at 3 dB electrical. In the
example of above, a differential level below 4 mV (p-p) of
the input signal will drive pin ST to LOW, and an input
signal level above 5.7 mV (p-p) will drive pin ST to HIGH.
Input signal level-detection
The TZA3044 allows for user-programmable input signal
level-detection and can automatically disable the switching
of the PECL outputs if the input signal is below a set
threshold. This prevents the outputs from reacting to noise
in the absence of a valid input signal, and insures that data
will only be transmitted when the signal-to-noise ratio of
the input signal is sufficient for low bit-error-rate system
operation. Complementary PECL flags (ST and STQ)
indicate whether the input signal is above or below the
programmed threshold level.
Since a JAM function is provided which forces the data
outputs to a predetermined state (DOUT = LOW and
DOUTQ = HIGH), the pins STQ and JAM can be
connected to automatically disable the signal transmission
when the chip senses that the input signal is below the
programmed threshold.
Response time of the input signal level-detection circuit is
determined by the time constant of the input capacitors,
together with the filter time constant (1 µs internal plus the
additional capacitor at pin CF).
The input signal is amplified and rectified before being
compared to a programmable threshold reference. A filter
is included to prevent noise spikes from triggering the
level-detector. This filter has a nominal 1 µs time constant
and additional filtering can be achieved by using an
external capacitor between pin CF and VCCA (the internal
driving impedance nominally is 25 kΩ). The resultant
signal is then compared to a threshold current through
pin RSET (see Fig.6). This current can be set by
connecting an external resistor RDETECT between
pin RSET and VCCA, or by forcing a current into pin RSET.
PECL output circuits
The output circuit of ST and STQ is given in Fig.7
The output circuit of DOUT and DOUTQ is given in Fig.8.
Some PECL termination schemes are given in Fig.9.
The relationship between the threshold current and the
detected input voltage is approximately:
I RSET = 0.002 × ( V DIN – V DINQ ) [ A ]
(1)
1998 Jul 07
TZA3044T; TZA3044U
6
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
VCC
handbook, full pagewidth
VO(max)
VOQH
VOH
Vo(p-p)
VOQL
VOO
VOL
VO(min)
MGR243
Fig.4 Logic level symbol definitions for PECL.
VCC
handbook, full pagewidth
DINQ
DIN
4.5 kΩ
2.55 V
4.5 kΩ
330 µA
330 µA
MGR244
Fig.5 Data input circuit DIN and DINQ.
1998 Jul 07
7
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
handbook, halfpage
VCC
TZA3044T; TZA3044U
RSET
1.5 V
MGR245
Fig.6 Level-detect input circuit RSET.
VCC
handbook, halfpage
VLOW
VHIGH
ST, STQ
10 kΩ
MGR246
Fig.7 PECL output circuit ST and STQ.
VCC
handbook,
halfpage
105 Ω
105 Ω
DOUT
DOUTQ
0.5 mA
9 mA
0.5 mA
MGR247
Fig.8 PECL output circuit DOUT and DOUTQ.
1998 Jul 07
8
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
VCC − 2 V
handbook, full pagewidth
R1 = 50 Ω
VI
R1 = 50 Ω
VO
Zo = 50 Ω
VIQ
VOQ
MGR248
VCC = 3.3 V
handbook, full pagewidth
R1 = 127 Ω
VI
R1 = 127 Ω
VO
Zo = 50 Ω
VIQ
VOQ
R2 = 82.5 Ω
GND
R2 = 82.5 Ω
MGR249
VCC = 5.0 V
handbook, full pagewidth
R1 = 83.3 Ω
VI
R1 = 83.3 Ω
VO
Zo = 50 Ω
VIQ
VOQ
R2 = 125 Ω
GND
Fig.9 PECL output termination schemes.
1998 Jul 07
9
R2 = 125 Ω
MGR250
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−0.5
+6
pins 4 and 5 (7 and 8): DIN and DINQ
−0.5
VCC + 0.5 V
pin 7 (13): CF
−0.5
VCC + 0.5 V
pin 8 (16): JAM
−0.5
VCC + 0.5 V
pins 9, 10, 12 and 13 (17, 18, 23 and 24):
STQ, ST, DOUTQ and DOUT
VCC − 2
VCC + 0.5 V
pin 15 (29): Vref
−0.5
+3.2
pin 16 (30): RSET
−0.5
VCC + 0.5 V
pin 4 and 5 (7 and 8): DIN and DINQ
−1
+1
mA
pin 7 (13): CF
−1
+1
mA
pin 8 (16): JAM
−1
+1
mA
pins 9, 10, 12 and 13 (17, 18, 23 and 24):
STQ, ST, DOUTQ and DOUT
−25
+10
mA
pin 15 (29): Vref
−2
+2.5
mA
pin 16 (30): RSET
−2
+2
mA
Ptot
total power dissipation
−
tbf
mW
Tstg
storage temperature
−65
+150
°C
Tj
junction temperature
−
150
°C
Tamb
ambient temperature
−40
+85
°C
VCC
supply voltage
Vn
DC voltage
In
V
note 1
DC current
V
note 1
Note
1. The numbers in brackets refer to the pad numbers of the naked die version.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth(j-s)
thermal resistance from junction to solder point
tbf
K/W
Rth(j-a)
thermal resistance from junction to ambient
tbf
K/W
1998 Jul 07
10
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
CHARACTERISTICS
For typical values Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient
temperature range and supply voltage range; all voltages with respect to ground; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCC
supply voltage
ICCD
digital supply current
ICCA
analog supply current
Ptot
total power dissipation
Tj
junction temperature
Tamb
ambient temperature
note 1
note 1
3
3.3
5.5
V
−
18
27
mA
−
15
22
mA
−
110
270
mW
−40
−
+120
°C
−40
+25
+85
°C
Inputs: DIN and DINQ
Vi(se)(p-p)
input signal voltage
single-ended (peak-to-peak)
0.002
−
1.0
V
Vi(dif)(p-p)
input signal voltage
differential (peak-to-peak)
0.004
−
2.0
V
VI
absolute input signal voltage
2.1
2.55
VCCA + 0.5
V
VIO(eq)
equivalent input signal offset
voltage
−
−
50
µV
VIO(cor)
input offset voltage correction note 2
range
−5
−
+5
mV
Ri
input resistance
single-ended
2.9
4.5
7.6
kΩ
Ci
input capacitance
single-ended
−
−
2.5
pF
Vn(i)(rms)
equivalent input RMS noise
voltage
note 3
−
115
145
µV
Input signal level-detect: RSET
Iref
reference current
note 4
5
−
60
µA
Vref
reference voltage
referred to VCCA
−1.55
−1.5
−1.45
V
Vth(p-p)
programmability
(single-ended, peak-to-peak)
Vi = 200 kHz square
wave
2
−
12
mV
hys
hysteresis
electrically measured
2
3
4
dB
RF
filter resistance
14
25
41
kΩ
tF
filter time constant
CF = 0
0.5
1.0
2.0
µs
RL = 50 Ω to VCC − 2 V
VCC − 1840 −
PECL outputs: DOUT and DOUTQ
VCC − 1620 mV
VOL
LOW-level output voltage
VOH
HIGH-level output voltage
RL = 50 Ω to VCC − 2 V
VCC − 1100 −
VCC − 900
mV
tr
rise time
20% to 80%
−
150
250
ps
tf
fall time
80% to 20%
−
100
200
ps
tw(p-p)
pulse width distortion
−
−
30
ps
f-3dB(l)
low frequency −3 dB point
−
0.85
1.5
kHz
f-3dB(h)
high frequency −3 dB point
1000
1300
1600
MHz
1998 Jul 07
11
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
SYMBOL
PARAMETER
TZA3044T; TZA3044U
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PECL outputs: ST and STQ
VOL
LOW-level output voltage
RL = 50 Ω to VCC − 2 V
VCC − 1840 −
VCC − 1620 mV
VOH
HIGH-level output voltage
RL = 50 Ω to VCC − 2 V
VCC − 1100 −
VCC − 900
mV
tr
rise time
20% to 80%
−
−
600
ns
tf
fall time
80% to 20%
−
−
200
ns
−
−
VCC − 1490 mV
PECL input: JAM
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
II(JAM)
JAM input current
VCC − 1165 −
−
mV
note 5
−10
−
+10
µA
note 6
1.165
1.20
1.235
V
Reference voltage output: Vref
Vref
reference voltage
Notes
1. DOUT, DOUTQ, ST and STQ outputs are left unconnected.
2. If the input is DC coupled, the preceding amplifier’s output offset voltage should not exceed these limits, in order to
avoid malfunctioning of the DC offset compensation circuit.
3.
total output RMS noise
Input RMS noise = -----------------------------------------------------------low frequency gain
4. The reference currents can be set by a resistor between VCCA and pin RSET. The corresponding input signal
level-detect range is from 2 to 12 mV (p-p) single-ended. See section “Input signal level-detection” for detailed
information.
5. Internal pull-down resistor of 500 kΩ to DGND.
6. Internal series resistor of 1 kΩ.
1998 Jul 07
12
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
APPLICATION INFORMATION
VCC
handbook, full pagewidth
100 nF
RSET
VCCA
6
(11, 12)
10 nF
DIN
100 nF
180 kΩ
16
(30)
CF
Vref
7
(13)
15
(29)
4 (7)
VCCD
14
(27, 28)
(24) 13
DOUT
TZA3044
data in
10 nF
DINQ
data out
5 (8)
(23) 12
(3, 4, 6, 9) (1, 14)
3
1
AGND
SUB
(16)
8
JAM
(17)
9
DOUTQ
(18) (19, 20, 22, 25)
10
11
STQ
ST
DGND
level-detect
status
1 kΩ
50 Ω
50 Ω
MGR251
The numbers in brackets refer to the pad numbers of the naked die version.
Fig.10 Application diagram.
1998 Jul 07
13
VCC − 2 V
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(1)
22 nF
100 nF
VCC
DREF
6
(11, 12)
1
7
TZA3043T
IPhoto
3
14
2
GND
4 pF
6
4
RSET
DIN
16
(30)
CF
7
(13)
VCCD
Vref
15
(29)
14
(27, 28)
4 (7)
(24) 13
100 Ω
DOUT
TZA3044
10 nF
OUT
noise filter:
1-pole, 800 MHz
5
GND
10 nF
OUTQ
100 nF
180 kΩ
VCCA
8
(1)
DINQ
5 (8)
(23) 12
(3, 4, 6, 9) (1, 14)
3
1
AGND
GND
data out
SUB
(16)
8
JAM
(17)
9
STQ
DOUTQ
(18) (19, 20, 22, 25)
10
11
ST
DGND
level-detect
status
1 kΩ
50 Ω
Philips Semiconductors
680 nF
(1)
1.25 Gbits/s Gigabit Ethernet postamplifiers
width
1998 Jul 07
VCC
50 Ω
VCC − 2 V
MGR252
Objective specification
Fig.11 STM1 receiver using the TZA3043T and TZA3044.
TZA3044T; TZA3044U
(1) ferrite bead e.g. Murata BLM31A601S.
The numbers in brackets refer to the pad numbers of the naked die version.
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
PACKAGE OUTLINE
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.050
0.041
0.228
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.01
0.01
0.028
0.004
0.012
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07S
MS-012AC
1998 Jul 07
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
15
o
8
0o
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
SOLDERING
Wave soldering
Introduction
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1998 Jul 07
16
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jul 07
17
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© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
425102/200/01/pp20
Date of release: 1998 Jul 07
Document order number:
9397 750 03816