INTEGRATED CIRCUITS DATA SHEET TZA3034T; TZA3034U SDH/SONET STM1/OC3 postamplifiers Objective specification File under Integrated Circuits, IC19 1998 Jul 07 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U FEATURES APPLICATIONS • Pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range and less external component count • Digital fibre optic receiver in short, medium and long haul optical telecommunications transmission systems or in high speed data networks • Wideband operation from 1.0 kHz to 150 MHz typical • Wideband RF gain block. • Applicable in 155 Mbits/s SDH/SONET receivers • Single supply voltage from 3.0 to 5.5 V GENERAL DESCRIPTION • PECL (Positive Emitter Coupled Logic) compatible data outputs The TZA3034 is a high gain limiting amplifier that is designed to process signals from fibre optic preamplifiers like the TZA3033. It is pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range, and needs less external components. Capable of operating at 155 Mbits/s, the chip has input signal level detection with a user-programmable threshold. The data and level-detection status outputs are differential outputs for optimum noise margin and ease of use. • Programmable input signal level-detection which can be adjusted using a single external resistor • On-chip DC offset compensation without external capacitor • Fully differential for excellent PSRR. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TZA3034T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TZA3034U naked die die in waffle pack carriers; die dimensions 1.58 × 1.58 mm − BLOCK DIAGRAM TEST handbook, full pagewidth 2 (2, 10, 15, 21, 26) DC-OFFSET COMPENSATION DIN DINQ TZA3034 (24) 13 4 (7) A1 5 (8) A2 A3 (23) 12 (16) 8 25 kΩ DOUT DOUTQ JAM RECTIFIER (18) 10 RSET Vref 16 (30) 15 (29) A4 1 kΩ (1, 14) 1 SUB (11, 12) 6 (13) 7 VCCA CF (19, 20, 22, 25) 11 DGND The numbers in brackets refer to the pad numbers of the naked die version. Fig.1 Block diagram. 1998 Jul 07 ST STQ BAND GAP REFERENCE (3, 4, 6, 9) 3 AGND (17) 9 2 (27, 28) 14 VCCD MGR281 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U PINNING SYMBOL PIN TYPE DESCRIPTION SUB 1 substrate substrate pin; must be at the same potential as AGND (pin 3) TEST 2 test pin for test purpose only; to be left open in the application AGND 3 ground analog ground; must be at the same potential as DGND (pin 11) DIN 4 analog input differential input; DC bias level is set internally at approximately 2.55 V; complimentary to DINQ (pin 5) DINQ 5 analog input differential input; DC bias level is set internally at approximately 2.55 V; complimentary to DIN (pin 4) VCCA 6 supply analog supply voltage; must be at the same potential as VCCD (pin 14) CF 7 analog input filter capacitor for input signal level detector; capacitor should be connected between this pin and VCCA (pin 6) JAM 8 PECL input PECL-compatible input; controls the output buffers DOUT and DOUTQ (pins 13 and 12). When a LOW signal is applied, the outputs will follow the input signal3 When a HIGH signal is applied, the DOUT and DOUTQ pins will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled LOW (JAM OFF). STQ 9 PECL output PECL-compatible status output of the input signal level detector; when the input signal is below the user-programmed threshold level, this output is HIGH; complimentary to ST (pin 10) ST 10 PECL output PECL-compatible status output of the input signal level detector; when the input signal is below the user-programmed threshold level, this output is LOW; complimentary to STQ (pin 9) DGND 11 ground digital ground; must be at the same potential as AGND (pin 3) DOUTQ 12 PECL output PECL-compatible differential output; when JAM is HIGH, this pin will be forced into a HIGH condition; complimentary to DOUT (pin 13) DOUT 13 PECL output PECL-compatible differential output; when JAM is HIGH, this pin will be forced into a LOW condition; complimentary to DOUTQ (pin 12) VCCD 14 supply digital supply voltage; must be at the same potential as VCCA (pin 6) Vref 15 analog output band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 kΩ RSET 16 analog input 1998 Jul 07 input signal level detector programming; nominal DC voltage is VCCA − 1.5 V; threshold level is set by connecting an external resistor between RSET and VCCA or by forcing a current into RSET; default value for this resistor is 180 kΩ which corresponds with approximately 4 mV (p-p) differential input signal 3 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U PAD CONFIGURATION Pad centre locations COORDINATES(1) handbook, halfpage SUB 1 16 RSET SYMBOL PAD 15 Vref TEST 2 14 VCCD AGND 3 DIN 4 13 DOUT x y SUB 1 −235.7 +647.8 TEST 2 −392.8 +647.8 AGND 3 −532.8 +647.8 DINQ 5 12 DOUTQ AGND 4 −647.8 +507.1 VCCA 6 11 DGND n.c. 5 −647.8 +350.0 10 ST AGND 6 −647.8 +210.0 9 DIN 7 −647.8 +70.0 DINQ 8 −647.8 −70.0 AGND 9 −647.8 −210.0 TEST 10 −647.8 −350.0 VCCA 11 −647.8 −507.1 VCCA 12 −532.8 −647.8 CF 13 −392.8 −647.8 SUB 14 −235.7 −647.8 TEST 15 −78.6 −647.8 JAM 16 +61.4 −647.8 STQ 17 +218.5 −647.8 ST 18 +375.6 −647.8 DGND 19 +532.7 −647.8 DGND 20 +647.8 −507.1 TEST 21 +647.8 −350.0 DGND 22 +647.8 −210.0 DOUTQ 23 +647.8 −70.0 DOUT 24 647.8 70.0 DGND 25 647.8 210.0 TEST 26 647.8 350.0 TZA3034T CF 7 JAM 8 STQ MGR282 Fig.2 Pin configuration. VCCD 27 647.8 507.1 VCCD 28 532.7 647.8 Vref 29 392.7 647.8 RSET 30 235.6 647.8 n.c. 31 78.5 647.8 n.c. 32 −78.6 +647.8 Note 1. Coordinates represent the position of the centre of the pad, in µm, with respect to the centre of the die. 1998 Jul 07 4 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U SUB n.c. n.c. RSET Vref VCCD 3 2 1 32 31 30 29 28 AGND 4 27 VCCD n.c. 5 26 TEST AGND 6 25 DGND DIN 7 24 DOUT DINQ 8 0 23 DOUTQ AGND 9 y 22 DGND TEST 10 21 TEST VCCA 11 20 DGND x 0 16 17 18 19 ST DGND SUB 15 STQ 14 JAM 13 TEST 12 CF TZA3034U VCCA 1.58(1) mm TEST handbook, full pagewidth AGND Bonding pad locations 1.58 mm(1) MGR283 (1) Typical value. Pad size: 90 × 90 µm. Fig.3 Bonding pad locations: TZA3034U. The outcome of this test is available at the PECL outputs ST and STQ. This flag can also be used to prevent the PECL outputs DOUT and DOUTQ from reacting to noise in the absence of a valid input signal, by connecting the output STQ to the input JAM. This insures that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. FUNCTIONAL DESCRIPTION The TZA3034 accepts up to 155 Mbits/s SD/SONET data streams, with amplitudes from 2 mV (p-p) up to 1 V (p-p) single-ended. The input signal will be amplified and limited to differential PECL output levels (see Fig.1). The input buffer A1 presents an impedance of approximately 4.5 kΩ to the data stream on the inputs DIN and DINQ. The input can be used both single-ended and differential, but differential operation is preferred for better performance. PECL logic The logic level symbol definitions for PECL are shown in Fig.4. Because of the high gain of the postamplifier, a very small offset voltage would shift the decision level in such a way that the input sensitivity decreases drastically. Therefore a DC offset compensation circuit is implemented in the TZA3034, which keeps the input of buffer A3 at its toggle point in the absence of any input signal. Input biasing The input pins DIN and DINQ are DC biased at approximately 2.55 V by an internal reference generator (see Fig.5). The TZA3034 can be DC coupled, but AC coupling is preferred. In case of DC coupling, the driving source must operate within the allowable input signal range (2.0 V to VCCA + 0.5 V). Also a DC offset voltage of An input signal level detection is implemented to check if the input signal is above the user-programmed level. 1998 Jul 07 5 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers Since the voltage on pin RSET is held constant at 1.5 V below VCCA, the current flowing into this pin will be: 1.5 I RSET = ------------------------ [ A ] (2) R DETECT more than a few millivolt should be avoided, since the internal DC offset compensation circuit has a limited correction range. If AC coupling is used to remove any DC compatibility requirement, the coupling capacitors must be large enough to pass the lowest input frequency of interest. For example, 1 nF coupling capacitors react with the internal 4.5 kΩ input bias resistors to yield a lower −3 dB frequency of 35 kHz. This then sets a limit on the maximum number of consecutive pulses that can be sensed accurately at the system data rate. Capacitor tolerance and resistor variation must be included for an accurate calculation. Combining these two formulas results in a general formula to calculate RDETECT for a given input signal level-detection: 750 (3) R DETECT = ------------------------------------------ [ Ω ] ( V DIN – V DINQ ) In this formula, VDIN and VDINQ are in V (p-p). Example: Detection should occur if the differential voltage of the input signals drops below 4 mV (p-p). In this case, a reference current of 0.002 × 0.004 = 8 µA should flow into pin RSET. This can be set using a current source or simply by connecting a resistor of the appropriate value. The resistor must be connected between VCCA and pin RSET. In this example the resistor would be: 750 R DETECT = ----------------- = 187.5 kΩ 0.004 DC-offset compensation A control loop connected between the inputs of buffer A3 and amplifier A1 (see Fig.1) will keep the input of buffer A3 at its toggle point in the absence of any input signal. Because of the active offset compensation which is integrated in the TZA3034, no external capacitor is required. The loop time constant determines the lower cut-off frequency of the amplifier chain, which is set at approximately 850 Hz. The hysteresis is fixed internally at 3 dB electrical. In the example of above, a differential level below 4 mV (p-p) of the input signal will drive pin ST to LOW, and an input signal level above 5.7 mV (p-p) will drive pin ST to HIGH. Input signal level-detection The TZA3034 allows for user-programmable input signal level-detection and can automatically disable the switching of the PECL outputs if the input signal is below a set threshold. This prevents the outputs from reacting to noise in the absence of a valid input signal, and insures that data will only be transmitted when the signal-to-noise ratio of the input signal is sufficient for low bit-error-rate system operation. Complementary PECL flags (ST and STQ) indicate whether the input signal is above or below the programmed threshold level. Since a JAM function is provided which forces the data outputs to a predetermined state (DOUT = LOW and DOUTQ = HIGH), the pins STQ and JAM can be connected to automatically disable the signal transmission when the chip senses that the input signal is below the programmed threshold. Response time of the input signal level-detection circuit is determined by the time constant of the input capacitors, together with the filter time constant (1 µs internal plus the additional capacitor at pin CF). The input signal is amplified and rectified before being compared to a programmable threshold reference. A filter is included to prevent noise spikes from triggering the level-detector. This filter has a nominal 1 µs time constant and additional filtering can be achieved by using an external capacitor between pin CF and VCCA (the internal driving impedance nominally is 25 kΩ). The resultant signal is then compared to a threshold current through pin RSET (see Fig.6). This current can be set by connecting an external resistor RDETECT between pin RSET and VCCA, or by forcing a current into pin RSET. PECL output circuits The output circuit of ST and STQ is given in Fig.7. The output circuit of DOUT and DOUTQ is given in Fig.8. Some PECL termination schemes are given in Fig.9. The relationship between the threshold current and the detected input voltage is approximately: I RSET = 0.002 × ( V DIN – V DINQ ) [ A ] (1) 1998 Jul 07 TZA3034T; TZA3034U 6 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U VCC handbook, full pagewidth VO(max) VOQH VOH Vo(p-p) VOQL VOO VOL VO(min) MGR243 Fig.4 Logic level symbol definitions for PECL. VCC handbook, full pagewidth DINQ DIN 4.5 kΩ 2.55 V 4.5 kΩ 330 µA 330 µA MGR244 Fig.5 Data input circuit DIN and DINQ. 1998 Jul 07 7 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers handbook, halfpage VCC TZA3034T; TZA3034U RSET 1.5 V MGR245 Fig.6 Level-detect input circuit RSET. VCC handbook, halfpage VLOW VHIGH ST, STQ 10 kΩ MGR246 Fig.7 PECL output circuit ST and STQ. VCC handbook, halfpage 105 Ω 105 Ω DOUT DOUTQ 0.5 mA 9 mA 0.5 mA MGR247 Fig.8 PECL output circuit DOUT and DOUTQ. 1998 Jul 07 8 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U VCC − 2 V handbook, full pagewidth R1 = 50 Ω VI R1 = 50 Ω VO Zo = 50 Ω VIQ VOQ MGR248 VCC = 3.3 V handbook, full pagewidth R1 = 127 Ω VI R1 = 127 Ω VO Zo = 50 Ω VIQ VOQ R2 = 82.5 Ω GND R2 = 82.5 Ω MGR249 VCC = 5.0 V handbook, full pagewidth R1 = 83.3 Ω VI R1 = 83.3 Ω VO Zo = 50 Ω VIQ VOQ R2 = 125 Ω GND Fig.9 PECL output termination schemes. 1998 Jul 07 9 R2 = 125 Ω MGR250 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT −0.5 +6 pins 4 and 5 (7 and 8): DIN and DINQ −0.5 VCC + 0.5 V pin 7 (13): CF −0.5 VCC + 0.5 V pin 8 (16): JAM −0.5 VCC + 0.5 V pins 9, 10, 12 and 13 (17, 18, 23 and 24): STQ, ST, DOUTQ and DOUT VCC − 2 VCC + 0.5 V pin 15 (29): Vref −0.5 +3.2 pin 16 (30): RSET −0.5 VCC + 0.5 V pin 4 and 5 (7 and 8): DIN and DINQ −1 +1 mA pin 7 (13): CF −1 +1 mA pin 8 (16): JAM −1 +1 mA pins 9, 10, 12 and 13 (17, 18, 23 and 24): STQ, ST, DOUTQ and DOUT −25 +10 mA pin 15 (29): Vref −2 +2.5 mA pin 16 (30): RSET −2 +2 mA Ptot total power dissipation − tbf mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb ambient temperature −40 +85 °C VCC supply voltage Vn DC voltage In V note 1 DC current V note 1 Note 1. The numbers in brackets refer to the pad numbers of the naked die version. THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT Rth(j-s) thermal resistance from junction to solder point tbf K/W Rth(j-a) thermal resistance from junction to ambient tbf K/W 1998 Jul 07 10 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U CHARACTERISTICS For typical values Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range; all voltages with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCC supply voltage ICCD digital supply current ICCA analog supply current Ptot total power dissipation Tj junction temperature Tamb ambient temperature note 1 note 1 3 3.3 5.5 V − 18 27 mA − 15 22 mA − 110 270 mW −40 − +120 °C −40 +25 +85 °C Inputs: DIN and DINQ Vi(se)(p-p) input signal voltage single-ended (peak-to-peak) 0.002 − 1.0 V Vi(dif)(p-p) input signal voltage differential (peak-to-peak) 0.004 − 2.0 V VI absolute input signal voltage 2.1 2.55 VCCA + 0.5 V VIO(eq) equivalent input signal offset voltage − − 50 µV VIO(cor) input offset voltage correction note 2 range −5 − +5 mV Ri input resistance single-ended 2.9 4.5 7.6 kΩ Ci input capacitance single-ended − − 2.5 pF Vn(i)(rms) equivalent input RMS noise voltage note 3 − 45 60 µV Input signal level-detect: RSET Iref reference current note 4 5 − 60 µA Vref reference voltage referred to VCCA −1.55 −1.5 −1.45 V Vth(p-p) programmability (single-ended, peak-to-peak) Vi = 200 kHz square wave 2 − 12 mV hys hysteresis electrically measured 2 3 4 dB RF filter resistance 14 25 41 kΩ tF filter time constant CF = 0 0.5 1.0 2.0 µs RL = 50 Ω to VCC − 2 V VCC − 1840 − PECL outputs: DOUT and DOUTQ VCC − 1620 mV VOL LOW-level output voltage VOH HIGH-level output voltage RL = 50 Ω to VCC − 2 V VCC − 1100 − VCC − 900 mV tr rise time 20% to 80% − 1.5 2.2 ns tf fall time 80% to 20% − 1.5 2.2 ns tw(p-p) pulse width distortion − − 0.1 ns f-3dB(l) low frequency −3 dB point − 0.85 1.5 kHz f-3dB(h) high frequency −3 dB point 110 150 190 MHz 1998 Jul 07 11 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers SYMBOL PARAMETER TZA3034T; TZA3034U CONDITIONS MIN. TYP. MAX. UNIT PECL outputs: ST and STQ VOL LOW-level output voltage RL = 50 Ω to VCC − 2 V VCC − 1840 − VCC − 1620 mV VOH HIGH-level output voltage RL = 50 Ω to VCC − 2 V VCC − 1100 − VCC − 900 mV tr rise time 20% to 80% − − 600 ns tf fall time 80% to 20% − − 200 ns − − VCC − 1490 mV PECL input: JAM VIL LOW-level input voltage VIH HIGH-level input voltage II(JAM) JAM input current VCC − 1165 − − mV note 5 −10 − +10 µA note 6 1.165 1.20 1.235 V Reference voltage output: Vref Vref reference voltage Notes 1. DOUT, DOUTQ, ST and STQ outputs are left unconnected. 2. If the input is DC coupled, the preceding amplifier’s output offset voltage should not exceed these limits, in order to avoid malfunctioning of the DC offset compensation circuit. 3. total output RMS noise Input RMS noise = -----------------------------------------------------------low frequency gain 4. The reference currents can be set by a resistor between VCCA and pin RSET. The corresponding input signal level-detect range is from 2 to 12 mV (p-p) single-ended. See section “Input signal level-detection” for detailed information. 5. Internal pull-down resistor of 500 kΩ to DGND. 6. Internal series resistor of 1 kΩ. 1998 Jul 07 12 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U APPLICATION INFORMATION VCC handbook, full pagewidth 100 nF RSET VCCA 6 (11, 12) 10 nF DIN 100 nF 180 kΩ 16 (30) CF Vref 7 (13) 15 (29) 4 (7) VCCD 14 (27, 28) (24) 13 DOUT TZA3034 data in 10 nF DINQ data out 5 (8) (23) 12 (3, 4, 6, 9) (1, 14) 3 1 AGND SUB (16) 8 JAM (17) 9 DOUTQ (18) (19, 20, 22, 25) 10 11 STQ ST DGND level-detect status 1 kΩ 50 Ω 50 Ω MGR284 The numbers in brackets refer to the pad numbers of the naked die version. Fig.10 Application diagram. 1998 Jul 07 13 VCC − 2 V This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... (1) 22 nF 100 nF VCC DREF 6 (11, 12) 1 7 TZA3033T IPhoto 3 31 pF 6 14 2 4 GND RSET DIN 16 (30) CF 7 (13) Vref 15 (29) 4 (7) VCCD 14 (27, 28) (24) 13 100 Ω DOUT TZA3034 10 nF OUT noise filter: 1-pole, 100 MHz 5 GND 10 nF OUTQ 100 nF 180 kΩ VCCA 8 (1) DINQ 5 (8) (23) 12 (3, 4, 6, 9) (1, 14) 3 1 AGND GND data out SUB (16) 8 JAM (17) 9 STQ DOUTQ (18) (19, 20, 22, 25) 10 11 ST DGND 64.4 nH 29.2 pF 64.4 nH SDH/SONET STM1/OC3 postamplifiers 680 nF (1) Philips Semiconductors width 1998 Jul 07 VCC level-detect status 4.5 pF Fig.11 STM1 receiver using the TZA3033T and TZA3034. 50 Ω VCC − 2 V MGR285 Objective specification (1) ferrite bead e.g. Murata BLM31A601S. The numbers in brackets refer to the pad numbers of the naked die version. 50 Ω TZA3034T; TZA3034U optional noise filter: 3-pole, 120 MHz Bessel 1 kΩ Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U PACKAGE OUTLINE SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.244 0.050 0.041 0.228 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07S MS-012AC 1998 Jul 07 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 15 o 8 0o Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U SOLDERING Wave soldering Introduction Wave soldering techniques can be used for all SO packages if the following conditions are observed: There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SO packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1998 Jul 07 16 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 postamplifiers TZA3034T; TZA3034U DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jul 07 17 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 425102/200/01/pp20 Date of release: 1998 Jul 07 Document order number: 9397 750 03814