INTEGRATED CIRCUITS DATA SHEET TZA3030 SDH/SONET STM1/OC3 optical receiver Objective specification File under Integrated Circuits, IC19 1998 Aug 24 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 FEATURES APPLICATIONS • Low equivalent input noise, typically 1 pA/√Hz • Digital fibre optic receiver in short, medium and long haul optical telecommunications transmission systems or in high speed data networks • Wide dynamic range, typically 0.5 µA to 2 mA • On-chip low-pass filter. The bandwidth can be varied between 90 and 150 MHz using an external resistor. Default value is 120 MHz. • Wideband RF gain block. • Differential transimpedance of 1.8 MΩ GENERAL DESCRIPTION • On-chip Automatic Gain Control (AGC) The TZA3030 optical receiver is a low-noise transimpedance amplifier with AGC plus a limiting amplifier designed to be used in SDH/SONET fibre optic links. The TZA3030 amplifies the current generated by a photo detector (PIN diode or avalanche photodiode) and converts it to a differential output voltage. • Positive Emitter Coupled Logic (PECL) or Current-Mode Logic (CML) compatible data outputs • LOS (Loss Of Signal) detection • LOS threshold level can be adjusted using a single external resistor • On-chip DC offset compensation • Single supply voltage from 3.0 to 5.5 V • Bias voltage for PIN diode. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TZA3030HL LQFP32 TZA3030U − 1998 Aug 24 DESCRIPTION plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm naked die in waffle pack carriers; die dimensions 1.58 × 1.58 mm 2 VERSION SOT401-1 − Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 BLOCK DIAGRAM AGC VCCA handbook, full pagewidth VCCD 2 2 2, 5 31 17, 20 LOS DETECTION TTL PECL PEAK DETECTOR DREF 4 IPhoto 7 2 kΩ 29 LOSTH 28 LOSTTL 26 LOS 27 LOSQ 18 OUTCML 19 OUTQCML 15 OUTSEL 22 OUTPECL 23 OUTQPECL GAIN CONTROL 65 pF CML A1 1 nF A2 PECL PREAMPLIFIER LIMITING AMPLIFIER DC OFFSET COMPENSATION TESTING 12 1, 3, 6, 8 9, 30, 32 14 BIASING TZA3030 10 11 7 SUB AGND 5 RFTEST Vref BWC Fig.1 Block diagram. 1998 Aug 24 13, 16, 21 24, 25 3 DGND MBK857 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 PINNING SYMBOL PIN TYPE DESCRIPTION AGND 1 ground analog ground VCCA 2 supply analog supply voltage AGND 3 ground analog ground DREF 4 analog output bias voltage for PIN diode (VCCA); cathode should be connected to this pin VCCA 5 supply analog supply voltage AGND 6 ground analog ground IPhoto 7 analog input current input; connect the anode of PIN diode to this pin; DC bias level is 1048 mV AGND 8 ground analog ground AGND 9 ground analog ground BWC 10 analog input bandwidth control pin; default bandwidth is 120 MHz; a resistor should be connected between Vref (pin 11) and BWC (pin 10) to decrease bandwidth, or between BWC (pin 10) and AGND to increase bandwidth Vref 11 analog output band gap reference voltage; nominal value approximately 1.2 V SUB 12 substrate substrate pin; to be connected to AGND DGND 13 ground digital ground RFTEST 14 analog input test pin; not connected; not used in application OUTSEL 15 CMOS input output select pin; when OUTSEL is HIGH, CML data outputs are active and PECL data outputs are disabled; OUTSEL is pulled LOW if left unconnected, PECL data outputs will then be active and CML data outputs disabled DGND 16 ground digital ground VCCD 17 supply digital supply voltage OUTCML 18 CML output CML data output; OUTCML goes HIGH when current flows into IPhoto (pin 7) OUTQCML 19 CML output CML compliment of OUTCML (pin 18) VCCD 20 supply digital supply voltage DGND 21 ground digital ground OUTPECL 22 PECL output PECL data output; OUTPECL goes HIGH when current flows into IPhoto (pin 7) OUTQPECL 23 PECL output PECL compliment of OUTPECL (pin 22) DGND 24 ground digital ground DGND 25 ground digital ground LOS 26 PECL output PECL-compatible LOS detection pin; LOS output is HIGH when the input signal is below the user programmable threshold level LOSQ 27 PECL output PECL compliment of LOS (pin 26) LOSTTL 28 TTL output CMOS-compatible LOS detection pin; the LOSTTL output is HIGH when the input signal is below the user programmable threshold level LOSTH 29 analog I/O pin for setting input threshold level; nominal DC voltage is VCCA − 1.5 V; threshold level set by connecting an external resistor between LOSTH and VCCA or by forcing a current into LOSTH; default value for this resistor is 400 kΩ AGND 30 ground analog ground AGC 31 analog I/O AGC monitor voltage; the internal AGC circuit can be disabled by applying an external voltage to this pin AGND 32 ground analog ground 1998 Aug 24 4 Philips Semiconductors Objective specification 25 DGND 26 LOS TZA3030 27 LOSQ 28 LOSTTL 29 LOSTH 30 AGND 32 AGND handbook, full pagewidth 31 AGC SDH/SONET STM1/OC3 optical receiver AGND 1 24 DGND VCCA 2 23 OUTQPECL AGND 3 22 OUTPECL DREF 4 21 DGND TZA3030HL 18 OUTCML AGND 8 17 VCCD AGND Fig.2 Pin configuration. 1998 Aug 24 5 DGND 16 7 OUTSEL 15 IPhoto RFTEST 14 19 OUTQCML DGND 13 6 SUB 12 AGND Vref 11 20 VCCD BWC 10 5 9 VCCA MBK856 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 CHIP DIMENSIONS AND BONDING PAD LOCATIONS COORDINATES(1) COORDINATES(1) SYMBOL SYMBOL PAD x y PAD OUTQCML 19 x y 1398 543 AGND 1 102 1251 VCCA 2 102 1111 VCCD 20 1398 683 21 1398 823 AGND 3 102 971 DGND DREF 4 102 814 OUTPECL 22 1398 963 VCCA 5 102 674 OUTQPECL 23 1398 1103 AGND 6 102 534 DGND 24 1398 1243 IPhoto 7 102 395 DGND 25 1283 1400 AGND 8 102 254 LOS 26 1143 1400 AGND 9 243 105 LOSQ 27 986 1400 BWC 10 383 105 LOSTTL 28 829 1400 Vref 11 523 105 LOSTH 29 671 1400 SUB 12 663 105 AGND 30 514 1400 DGND 13 803 105 AGC 31 357 1400 RFTEST 14 943 105 AGND 32 217 1400 OUTSEL 15 1100 105 Note 1. All coordinates (µm) are measured with respect to the bottom left-hand corner of the die. 403 handbook, full pagewidth 31 30 29 28 27 26 25 AGND 1 24 DGND VCCA 2 23 OUTQPECL AGND 3 22 OUTPECL DREF 4 21 DGND VCCA 5 20 VCCD AGND 6 19 OUTQCML IPhoto 7 18 OUTCML 8 17 VCCD 14 15 16 DGND y 13 OUTSEL 12 RFTEST 11 DGND 10 SUB 0 9 Vref 0 TZA3030U BWC AGND x 32 AGND 1.58 mm DGND 1398 LOS 18 LOSQ OUTCML LOSTTL 263 LOSTH 105 1398 AGND 1257 17 AGC 16 VCCD AGND DGND 1.58 mm Fig.3 Bonding pad locations of TZA3030U. 1998 Aug 24 6 MBK858 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 FUNCTIONAL DESCRIPTION Limiting amplifier The TZA3030 contains five functional blocks: A limiting amplifier boosts the signal up to PECL levels. The output can be either CML or PECL compatible, selected by means of pin OUTSEL. When OUTSEL is HIGH, the CML data outputs are active and the PECL data outputs are disabled. If OUTSEL is left unconnected, it is pulled LOW and the PECL data outputs are active while the CML data outputs are disabled. • Preamplifier input stage • Low-pass filter • Limiting amplifier stage • Offset compensation loop • Loss of signal detection unit. The logic level symbol definitions for CML and PECL are shown in Fig.4. Preamplifier The preamplifier provides low-noise amplification of the current generated by a photodiode connected to pin IPhoto. The CML and PECL output circuits are given in Fig.5. A differential amplifier converts the output of the preamplifier to a differential voltage. An AGC loop increases the dynamic range of the receiver by reducing the feedback resistance of the preamplifier. The AGC loop hold capacitor is integrated on-chip, so an external capacitor is not needed for AGC. The AGC voltage can be monitored at pin AGC. This pin can be left unconnected for normal operation. It can also be used to force an external AGC voltage. If pin AGC is connected to VCCA, the internal AGC loop is disabled and the receiver gain is at a maximum. In this case, the maximum input current is approximately 10 µA. A control loop connected between the limiting amplifier output and the differential amplifier input cancels the DC offset. The loop bandwidth is fixed internally at 30 kHz. Offset compensation loop Loss Of Signal (LOS) detection The LOS section detects an input signal level below a fixed threshold. The threshold is determined by the current through pin LOSTH. If this current is increased, the threshold level will rise. An external resistor connected between pin LOSTH and VCCA can be used, or a current can be forced into pin LOSTH. The default value for the external resistor is 400 kΩ. In this case, the current through pin LOSTH will be approximately 3.75 µA since the voltage at pin LOSTH is regulated at 1.5 V below the supply voltage. This threshold corresponds to an input current of 208 nA. The ratio of LOSTH current to input current is thus approximately 18 : 1. When the input signal level falls below this threshold, the LOS (PECL compatible) and LOSTTL (TTL compatible) outputs go HIGH. The hysteresis is fixed internally at 3 dB. Response time is typically less than 20 µs. Low-pass filter A low-pass filter controls the bandwidth of the receiver, which can be varied between 90 and 150 MHz. The bandwidth is set to 120 MHz by default. It can be decreased by connecting a resistor between pin BWC and pin Vref or increased by connecting a resistor between pin BWC and AGND. 1998 Aug 24 7 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 VCC handbook, full pagewidth VO(max) VOQH VOH Vo(p-p) VOQL VOO VOL VO(min) MGR243 Fig.4 Logic level symbol definitions for CML and PECL. VCC handbook, full pagewidth VCC 100 Ω 105 Ω 100 Ω OUTCML 105 Ω OUTQCML OUTPECL OUTQPECL 0.5 mA 9 mA 6 mA 0.5 mA MGK886 a. CML. b. PECL. Fig.5 Output circuits. 1998 Aug 24 8 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MAX. UNIT −0.5 +6 V pin 7: IPhoto −0.5 +2 V pin 14: RFTEST −0.5 VCC supply voltage Vn DC voltage In MIN. VCC + 0.5 V pins 22, 23, 26 and 27: OUTPECL, OUTQPECL, LOS and LOSQ VCC − 2 VCC + 0.5 V pins 18 and 19: OUTCML and OUTQCML VCC − 2 VCC + 0.5 V pin 29: LOSTH −0.5 VCC + 0.5 V pin 10: BWC −0.5 +3.2 pin 31: AGC −0.5 VCC + 0.5 V pin 11: Vref −0.5 +3.2 V V pin 4: DREF −0.5 VCC + 0.5 V pin 15: OUTSEL −0.5 VCC + 0.5 V pin 28: LOSTTL −0.5 VCC + 0.5 V pin 7: IPhoto −2.5 +2.5 mA pin 14: RFTEST −2 +2 mA pins 22, 23, 26 and 27: OUTPECL, OUTQPECL, LOS and LOSQ −25 +10 mA pins 18 and 19: OUTCML and OUTQCML −15 +15 mA pin 29: LOSTH −2 +2 mA pin 10: BWC −1 +1 mA pin 31: AGC −0.2 +0.2 mA pin 11: Vref −2 +2.5 mA pin 4: DREF −2.5 +2.5 mA pin 15: OUTSEL −0.5 +0.5 mA pin 28: LOSTTL −16 +16 mA 600 mW DC current Ptot total power dissipation − Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb operating ambient temperature −40 +85 °C THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT Rth(j-s) thermal resistance from junction to solder point tbf K/W Rth(j-a) thermal resistance from junction to ambient tbf K/W 1998 Aug 24 9 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 CHARACTERISTICS For typical values Tamb = 25 °C and VCC = 5 V; minimum and maximum values are valid over the entire ambient temperature range and process spread. SYMBOL PARAMETER VCC supply voltage ICCD digital supply current CONDITIONS MIN. 3 TYP. 5 MAX. 5.5 UNIT V note 1 13 20 28 mA note 2 − 47 − mA note 3 11 17 24 mA ICCA analog supply current 24 36 51 mA Ptot total power dissipation − − 525 mW Tj junction temperature −40 − +110 °C Tamb operating ambient temperature −40 +25 +85 °C Rtr small-signal transresistance of the receiver PECL outputs − 2000 − kΩ CML outputs − 1000 − kΩ − 120 − MHz 20 30 40 kHz ∆f = 90 MHz − 16 − nA ∆f = 120 MHz − tbf − nA ∆f = 155 MHz − tbf − nA − 0.5 µA/V f = 10 MHz to 100 MHz − 10 µA/V f−3dB(h) high frequency −3 dB point f−3dB(l) low frequency −3 dB point In(tot) total integrated RMS noise current over bandwidth PSRR power supply rejection ratio measured differentially pin BWC left unconnected; note 4 referenced to input; Ci = 1.2 pF; note 5 measured differentially; note 6 f = 100 kHz to 10 MHz ∆Rtr/∆t − 1 − dB/ms tbf 1048 tbf mV VCC = 5 V −2000 +1 +2000 µA VCC = 3.3 V −1000 +1 +1000 µA mV AGC loop constant Input: IPhoto Vbias(IPhoto) input bias voltage Ii(IPhoto)(p-p) input current (peak-to-peak value) PECL outputs: OUTPECL and OUTQPECL VOH HIGH-level output voltage 50 Ω to VCC − 2 V VCC − 1100 − VCC − 900 VOL LOW-level output voltage 50 Ω to VCC − 2 V VCC − 1840 − VCC − 1620 mV VOO output offset voltage measured differentially −10 − +10 mV tr rise time 20% to 80% − tbf tbf ps tf fall time 80% to 20% − tbf tbf ps 1998 Aug 24 10 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver SYMBOL PARAMETER TZA3030 CONDITIONS MIN. TYP. MAX. UNIT PECL outputs: LOS and LOSQ VOH HIGH-level output voltage 50 Ω to VCC − 2 V VCC − 1100 − VCC − 900 VOL LOW-level output voltage 50 Ω to VCC − 2 V VCC − 1840 − VCC − 1620 mV VOO output offset voltage measured differentially −10 − +10 mV tr rise time 20% to 80% − − 600 ns tf fall time 80% to 20% − − 200 ns mV CML outputs: OUTCML and OUTQCML VO output voltage measured single-ended; 50 Ω to VCC VCC − 260 − VCC mV Vo(se)(p-p) output voltage single-ended (peak-to-peak value) 50 Ω to VCC 150 200 260 mV VOO output offset voltage measured differentially; 50 Ω to VCC −10 − +10 mV Ro output resistance measured single-ended 80 100 120 Ω tr rise time 20% to 80%; RL = 50 Ω; CL = 1 pF − tbf − ps tf fall time 80% to 20%; RL = 50 Ω; CL = 1 pF − tbf − ps 0.8 V CMOS input: OUTSEL VIL LOW-level input voltage − 0.4 VIH HIGH-level input voltage VCC − 1 VCC − 0.5 − V CMOS output: LOSTTL VOL LOW-level output voltage 0 − 0.2 V VOH HIGH-level output voltage VCC − 0.2 − VCC V Notes 1. OUTPECL, OUTQPECL, OUTCML, OUTQCML, LOS and LOSQ outputs are left unconnected. OUTPECL and OUTQPECL outputs are active. 2. OUTPECL and OUTQPECL outputs are terminated with 50 Ω to VT. VT is an external termination voltage for PECL outputs and is 2 V below the supply voltage. OUTCML, OUTQCML, LOS and LOSQ outputs are left unconnected. 3. OUTCML and OUTQCML outputs are terminated with 50 Ω to VCCD; CML outputs are active. OUTPECL, OUTQPECL, LOS and LOSQ outputs are left unconnected. 4. The bandwidth is set to 120 MHz by default. It can be varied between 90 and 150 MHz by adjusting the voltage at pin BWC. 5. All In(tot) measurements were made with an input capacitance of Ci = 1.2 pF. This was comprised of 0.7 pF for the photodiode itself, with 0.3 pF allowed for the PCB layout and 0.2 pF intrinsic to the package. 6. PSRR is defined as the ratio of the equivalent current change at the input (∆IIPhoto) to a change in supply voltage: ∆I IPhoto PSRR = ------------------∆V CC For example, a 4 mV disturbance on VCCat 10 MHz will typically generate the equivalent of 2 nA extra photodiode current. 1998 Aug 24 11 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 APPLICATION INFORMATION VCC handbook, full pagewidth 680 nF 10 µH 22 nF 2, 5 22 nF 400 kΩ 2 VCCA 10 µH 2 VCCD LOSTH 29 17, 20 27 1 nF DREF 26 28 4 23 TZA3030 IPhoto 22 7 19 12 1, 3, 6, 8 9, 30, 32 SUB 31 AGND 10 AGC 14 BWC 11 13, 16, 21 18 24, 25 15 RFTEST Vref OUTSEL 7 LOSQ LOS LOSTTL R1 R1 Zo = 50 Ω OUTQPECL OUTPECL Zo = 50 Ω OUTQCML R2 R2 OUTCML DGND MBK859 5 Fig.6 Application diagram: PECL data outputs active. VCC handbook, full pagewidth 680 nF 10 µH 22 nF 2, 5 22 nF 400 kΩ 2 VCCA 2 VCCD LOSTH 29 10 µH 17, 20 27 1 nF DREF 26 28 4 23 TZA3030 IPhoto 22 7 19 12 1, 3, 6, 8 9, 30, 32 SUB AGND 31 10 AGC BWC 14 11 RFTEST Vref 13, 16, 21 18 24, 25 15 OUTSEL 7 LOSQ LOS LOSTTL OUTQPECL OUTPECL R1 Zo = 50 Ω OUTQCML OUTCML Zo = 50 Ω DGND 5 MBK860 Fig.7 Application diagram: CML data outputs active. 1998 Aug 24 12 R1 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 PECL outputs: OUTPECL, OUTQPECL, LOS and LOSQ PECL outputs can be terminated in different ways depending on the power supply voltage (see Fig.8). VCC = 3.3 V handbook, full pagewidth R1 = 127 Ω VIQ VI R1 = 127 Ω VOQ VO R2 = 82.5 Ω R2 = 82.5 Ω GND VCC = 5 V R1 = 83.3 Ω VIQ VI VO R2 = 125 Ω GND Fig.8 PECL termination schemes. 1998 Aug 24 R1 = 83.3 Ω VOQ 13 R2 = 125 Ω MGK887 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver If the output impedance was 50 Ω rather than 100 Ω, an 8 mA tail current would be needed to generate the same voltage swing. This would increase power dissipation by 33%. CML outputs: OUTCML and OUTQCML The output impedance of the CML output driver is 100 Ω (see Fig.9) which doesn’t match the characteristic impedance of the strip line. While this means that the reflections of some incident edges will arrive at the driver output on the PCB, this value was selected to reduce power dissipation inside the IC. The parallel combination of 100 Ω and 50 Ω (33 Ω) will generate a signal swing of 200 mV (peak-to-peak value, single-sided) with a tail current of 6 mA. generator inside TZA3030 handbook, full pagewidth TZA3030 If necessary, the output impedance of the generator can be matched to the line impedance by connecting an external 100 Ω resistor in parallel with the output as shown in Fig.10. The magnitude of the output voltage swing will not change due to adaptive regulation. However, power dissipation will increase by 33%. interconnect PCB receiver inside TZA3004 VCC 100 Ω VCC 100 Ω Zo = 50 Ω VO VI Zo = 50 Ω 50 Ω 50 Ω VIQ VOQ MBK861 Fig.9 CML interface circuit without matched impedance; low power dissipation. generator inside TZA3030 handbook, full pagewidth interconnect PCB receiver inside TZA3004 VCC 100 Ω VCC 100 Ω 100 Ω VO 100 Ω Zo = 50 Ω VI Zo = 50 Ω 50 Ω 50 Ω VIQ VOQ MBK862 Fig.10 CML interface circuit with matched impedance; high power dissipation. 1998 Aug 24 14 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 PACKAGE OUTLINE SOT401-1 LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm c y X A 17 24 ZE 16 25 e A A2 E HE (A 3) A1 w M pin 1 index θ bp 32 Lp 9 L 1 8 detail X ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 5.1 4.9 0.5 7.15 6.85 7.15 6.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 97-08-04 SOT401-1 1998 Aug 24 EUROPEAN PROJECTION 15 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver If wave soldering cannot be avoided, for LQFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all LQFP packages with a pitch (e) equal or less than 0.5 mm. 1998 Aug 24 TZA3030 16 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver TZA3030 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Aug 24 17 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver NOTES 1998 Aug 24 18 TZA3030 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 optical receiver NOTES 1998 Aug 24 19 TZA3030 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 425102/200/01/pp20 Date of release: 1998 Aug 24 Document order number: 9397 750 04069