CY23S02
Spread Aware™, Frequency Multiplier,
and Zero Delay Buffer
Spread Aware™, Frequency Multiplier, and Zero Delay Buffer
Features
Configuration Options
■
Spread Aware™ – designed to work with SSFTG reference
signals
FBIN
FS0
FS1
OUT1
■
90 ps typical jitter OUT2
OUT1
0
0
2 X REF
REF
■
200 ps typical jitter OUT1
OUT1
1
0
4 X REF
2 X REF
■
65 ps typical output-to-output skew
OUT1
0
1
REF
REF/2
OUT1
1
1
8 X REF
4 X REF
OUT2
0
0
4 X REF
2 X REF
OUT2
1
0
8 X REF
4 X REF
OUT2
0
1
2 X REF
REF
OUT2
1
1
16 X REF
8 X REF
■
90 ps typical propagation delay
■
Voltage range: 3.3 V ± 5%, or 5 V ± 10%
■
Output frequency range: 20 MHz - 133 MHz
■
Two outputs
■
Configuration options allow various multiplication of the
reference frequency, refer to Configuration Options to
determine the specific option which meets your multiplication
needs
■
OUT2
Functional Description
For a complete list of related documentation, click here.
Available in 8-pin SOIC package
Block Diagram
External feedback connection to
OUT1 or OUT2, not both
FBIN
FS0
FS1
IN
Reference
Input
÷Q
Phase
Detector
Charge
Pump
Loop
Filter
Output
Buffer
OUT1
Output
Buffer
OUT2
VCO
÷2
Cypress Semiconductor Corporation
Document Number: 38-07155 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 18, 2016
CY23S02
Pin Configuration
FBIN
1
8
OUT2
IN
2
7
VDD
GND
3
6
OUT1
FS0
4
5
FS1
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
IN
2
I
Reference Input: The output signals will be synchronized to this signal.
FBIN
1
I
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback is
equal in length to the traces between the outputs and the signal destinations, then the signals
received at the destinations will be synchronized to the REF signal input (IN).
OUT1
6
O
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table ).
OUT2
8
O
Output 2: The frequency of the signal provided by this pin is one-half of the frequency of
OUT1. See Table .
VDD
7
P
Power Connections: Connect to 3.3 V or 5 V. This pin should be bypassed with a 0.1-F
decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance.
GND
3
P
Ground Connection: Connect all grounds to the common system ground plane.
FS0:1
4, 5
I
Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per
Table .
Overview
Spread Aware
The CY23S02 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing
maximum flexibility when implementing the Zero Delay feature.
This is explained further in the sections of this data sheet titled
“How to Implement Zero Delay,” and “Inserting Other Devices in
Feedback Path.”
Many systems being designed now utilize a technology called
spread spectrum frequency timing generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through, the
result is a significant amount of tracking skew which may cause
problems in systems requiring synchronization.
The CY23S02 is a pin-compatible upgrade of the Cypress
W42C70-01. The CY23S02 addresses some application
dependent problems experienced by users of the older device.
Most importantly, it addresses the tracking skew problem
induced by a reference that has Spread Spectrum Timing
enabled on it.
Document Number: 38-07155 Rev. *H
For more details on Spread Spectrum timing technology, please
see the Cypress application note titled, “EMI Suppression
Techniques with Spread Spectrum Frequency Timing Generator
(SSFTG) ICs.”
Page 2 of 10
CY23S02
Figure 1. Schematic/Suggested Layout
CA
G
10 µF
Ferrite
Bead
V+
Power Supply Connection
C8
G
0.01 µF
FBIN
1
IN
GND
FS0
8
7
2
3
G
4
How to Implement Zero Delay
Typically, zero delay buffers (ZDBs) are used because a
designer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this, layout
must compensate for trace length between the ZDB and the
target devices. The method of compensation is described below.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB causes the feedback signal to be in phase
with the reference signal. When laying out the board, match the
trace lengths between the output being used for feed back and
the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede the
input signal, this may also be affected by either making the trace
to the FBIN pin a little shorter or a little longer than the traces to
the devices being clocked.
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is the
ability to synchronize signals up to the signal coming from some
other device. This implementation can be applied to any device
(ASIC, multiple output clock buffer/driver, and so on) that is put
into the feedback path.
Referring to Figure 2, if the traces between the ASIC/Buffer and
the destination of the clock signal(s) (A) are equal in length to the
trace between the buffer and the FBIN pin, the signals at the
Document Number: 38-07155 Rev. *H
6
FS1
5
destination(s) device is driven HIGH at the same time the
Reference clock provided to the ZDB goes HIGH. Synchronizing
the other outputs of the ZDB to the outputs from the ASIC/Buffer
is more complex however, as any propagation delay in the
ASIC/Buffer must be accounted for.
Figure 2. Six Output Buffer in the Feedback Path
Reference
Signal
Feedback
Input
Zero
Delay
Buffer
ASIC/
Buffer
A
Phase Alignment
In cases where OUT1 (i.e., the higher frequency output) is
connected to FBIN input pin the output OUT2 rising edges may
be either 0° or 180° phase aligned to the IN input waveform (as
set randomly when the input and/or power is supplied). If OUT2
is desired to be rising-edge aligned to the IN input’s rising edge,
then connect the OUT2 (i.e., the lowest frequency output) to the
FBIN pin. This setup provides a consistent input-output phase
relationship.
Page 3 of 10
CY23S02
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only.
Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not
implied. Maximum conditions for extended periods may affect reliability.
Rating
Unit
VDD, VIN
Parameter
Voltage on any pin with respect to GND
Description
–0.5 to +7.0
V
TSTG
Storage temperature
–65 to +150
°C
TA
Operating temperature
0 to +70
°C
TB
Ambient temperature under bias
–55 to +125
°C
PD
Power dissipation
0.5
W
DC Electrical Characteristics
TA = 0 °C to 70 °C or –40 °C to 85 °C, VDD = 3.3 V ± 5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
–
–
17
35
mA
–
0.8
V
IDD
Supply current
VIL
Input low voltage
VIH
Input high voltage
VOL
Output low voltage
IOL = 8 mA
VOH
Output high voltage
IOH = 8 mA
2.4
–
–
V
IIL
Input low current
VIN = 0 V
–40
–
5
A
IIH
Input high current
VIN = VDD
–
–
5
A
Min.
Typ.
Max.
Unit
–
31
50
mA
Unloaded, 133 MHz
2.0
–
–
V
–
–
0.4
V
DC Electrical Characteristics
TA = 0 °C to 70 °C or –40 °C to 85 °C, VDD = 5 V ± 10%
Parameter
Description
Test Condition
IDD
Supply Current
VIL
Input Low Voltage
–
–
0.8
V
VIH
Input High Voltage
2.0
–
–
V
Unloaded, 133 MHz
VOL
Output Low Voltage
IOL = 8 mA
–
–
0.4
V
VOH
Output High Voltage
IOH = 8 mA
2.4
–
–
V
IIL
Input Low Current
VIN = 0 V
–80
–
5
A
IIH
Input High Current
VIN = VDD
–
–
5
A
Thermal Resistance
Parameter [1]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
8-pin SOIC
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
132
°C/W
43
°C/W
Note
1. These parameters are guaranteed by design and are not tested.
Document Number: 38-07155 Rev. *H
Page 4 of 10
CY23S02
AC Electrical Characteristics
TA = 0 °C to +70 °C or –40 °C to 85 °C, VDD = 3.3 V ± 5%
Parameter
Description
Test Condition
[2]
Min.
Typ.
Max.
Unit
OUT2 = REF
10
–
133
MHz
fIN
Input frequency
fOUT
Output frequency
OUT1
20
–
133
MHz
tR
Output rise time
0.8 V to 2.0 V, 15-pF load
–
–
3.5
ns
tF
Output fall time
2.0 V to 0.8 V, 15-pF load
–
–
2.5
ns
–
–
10
ns
–
–
10
ns
–
–
300
ps
Note 6
40
50
60
%
Power supply stable
–
–
1.0
ms
OUT1
–
200
300
ps
OUT2
–
90
300
ps
–
65
250
ps
–350
90
350
ps
Min.
Typ.
Max.
Unit
OUT2 = REF
10
—
133
MHz
tICLKR
Input clock rise time
[3]
[3]
tICLKF
Input clock fall time
tPD
FBIN to IN (Reference Input) Skew [4, 5]
[6]
tDC
Duty cycle
tLOCK
PLL lock time
tJC
Jitter, Cycle-to-Cycle
tSKEW
Output-output Skew
tPD
Propagation delay
[7]
AC Electrical Characteristics
TA = 0 °C to +70 °C or –40 °C to 85 °C, VDD = 5 V ± 10%
Parameter
Description
Test Condition
[2]
fIN
Input frequency
fOUT
Output frequency
OUT1
20
—
133
MHz
tR
Output rise time
0.8 V to 2.0 V, 15-pF load
—
—
3.5
ns
tF
Output fall time
2.0 V to 0.8 V, 15-pF load
—
—
2.5
ns
—
—
10
ns
—
—
10
ns
tICLKR
tICLKF
Input clock rise time
Input clock fall time
[3]
[3]
tPD
FBIN to IN (Reference Input) Skew
tD
Duty cycle [8, 9]
tLOCK
PLL lock time
tJC
Jitter, Cycle-to-Cycle
tSKEW
Output-output skew
tPD
Propagation delay
[7]
[4, 5]
—
—
300
ps
40
50
60
%
Power supply stable
—
—
1.0
ms
OUT1
—
200
300
ps
OUT2
—
90
300
ps
—
65
250
ps
–350
90
350
ps
Notes
2. Input frequency is limited by output frequency range and input to output frequency multiplication factor (that is determined by circuit configuration).
3. Longer input rise and fall time will degrade skew and jitter performance.
4. All AC specifications are measured with a 50 transmission line, load terminated with 50 to 1.4 V.
5. Skew is measured at 1.4 V on rising edges.
6. Duty cycle is measured at 1.4 V.
7. Jitter is measured on 133-MHz signal at 1.4 V, low frequency jitter = 350 ps.
8. Duty cycle is measured at 1.4 V, 120 MHz.
9. Duty cycle at 133 MHz is 35/65 worst case.
Document Number: 38-07155 Rev. *H
Page 5 of 10
CY23S02
Ordering Information
Ordering Code
Package Type
Temperature Grade
Pb-free
CY23S02SXI-1
8-pin SOIC (150 mil)
Industrial, –40 °C to 85 °C
CY23S02SXI-1T
8-pin SOIC (150 mil) - Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 23S02 S
X
X - X
T
T = Tape and Reel
X=1
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free
S = SOIC
Base Device Part Number
Company ID: CY = Cypress
Document Number: 38-07155 Rev. *H
Page 6 of 10
CY23S02
Package Diagram
Figure 3. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *H
Document Number: 38-07155 Rev. *H
Page 7 of 10
CY23S02
Acronyms
Document Conventions
Acronym
Description
Units of Measure
ASIC
application-specific integrated circuit
EMI
electromagnetic interference
°C
degree Celsius
PLL
phase-locked loop
µA
microampere
SOIC
small outline integrated circuit
mA
milliampere
SSFTG
Spread Spectrum Frequency Timing Generator
ms
millisecond
VCO
voltage controlled oscillator
MHz
megahertz
ZDB
zero delay buffer
ns
nanosecond
pF
picofarad
ps
picosecond
V
volt
W
watt
Document Number: 38-07155 Rev. *H
Symbol
Unit of Measure
Page 8 of 10
CY23S02
Document History Page
Document Title: CY23S02, Spread Aware™, Frequency Multiplier, and Zero Delay Buffer
Document Number: 38-07155
Rev.
ECN No.
Issue Date
Orig. of
Change
**
110265
12/18/01
SZV
Change from Spec number: 38-00795 to 38-07155
OBS
292037
See ECN
RGL
To Obsolete the DS
*B
348376
See ECN
RGL
Minor Change: Re-activate the Spec (Only commercial are obsoleted, all
industrial parts area still active).
*C
378857
See ECN
RGL
Updated Overview:
Added Phase Alignment.
Add typical char data.
*D
2894970
03/23/2010
KVM
Updated Ordering Information (Removed inactive parts).
Updated Package Diagram.
*E
3339549
08/08/2011
PURU
Added Ordering Code Definitions under Ordering Information.
Updated Package Diagram.
Added Acronyms and Units of Measure.
*F
4499739
09/11/2014
TAVA
Updated Package Diagram:
spec 51-85066 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*G
4580603
11/26/2014
TAVA
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*H
5276080
05/18/2016
PSR
Added Thermal Resistance.
Updated Package Diagram:
spec 51-85066 – Changed revision from *F to *H.
Updated to new template.
Document Number: 38-07155 Rev. *H
Description of Change
Page 9 of 10
CY23S02
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Products
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Memory
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Wireless/RF
cypress.com/memory
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2005-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
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product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 38-07155 Rev. *H
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Revised May 18, 2016
Page 10 of 10