Freescale Semiconductor Data Sheet Consumer Low Power Wireless Transmitter Controller Features Low power (5 W) solution for Wireless Power Consortium (WPC) compliant transmitter design Conforms to the latest version low power WPC specifications Supports wide DC input voltage range starting from 4.2 V, typically 5 V, 12 V and 19 V Integrated digital demodulation on chip Supports all types of receiver modulation strategies (AC capacitor, AC resistor and DC resistor) Supports Foreign Object Detection (FOD) Super low standby power by Freescale Touch technology Supports any low power consumer power transmitter solutions using frequency and duty cycle control, or rail voltage control or phase shift control LED & buzzer for system status indication Over-voltage/current/temperature protection Supports CAN/IIC/SCI/SPI interfaces Software based solution to provide maximum design freedom and product differentiation FreeMASTER GUI tool to enable configuration, calibration and debugging Applications Low Power Wireless Power Transmitter Any lower power consumer power transmitter solution with frequency & duty cycle control, or rail voltage control, or phase-shift control (WPC A/B types or customer properties) Document Number: WCT1101DS Rev. 1.0, 02/2014 Overview Description The WCT1101 is a wireless power transmitter controller that integrates all required functions for WPC “Qi” compliant wireless power transmitter design. It’s an intelligent device to work with Freescale touch sensing technology or use periodically analog PING (configurable by user) to detect a mobile device for charging while gaining super low standby power. Once the mobile device is detected, the WCT1101 controls the power transfer by adjusting the operation frequency and duty cycle, or rail voltage, or phase shift of power stage according to message packets sent by mobile device. To maximize the design freedom and product differentiation, WCT1101 supports any low power consumer power transmitter design (WPC A/B types or customization) using frequency and duty cycle control, or rail voltage control or phase shift control by software based solution. Besides, easy-to-use FreeMASTER GUI tool with configuration, calibration and debugging functions provides user-friendly design experience and speed time-to-market. The WCT1101 includes digital demodulation module to reduce external components, over-voltage/current/ temperature protection, FOD method to protect from overheating by misplaced metallic foreign objects and general CAN/IIC/SCI/SPI interfaces for external communication purpose. It also handles any abnormal condition and operational status, and provides comprehensive indicator outputs for robust system design. Wireless Charging System Functional Diagram © Freescale Semiconductor, Inc., 2014. All rights reserved. _______________________________________________________________________ Contents 1 Absolute Maximum Ratings .................................................................................................................... 4 1.1 Electrical Operating Ratings .................................................................................................................................... 4 1.2 Thermal Handling Ratings ....................................................................................................................................... 5 1.3 ESD Handling Ratings .............................................................................................................................................. 5 1.4 Moisture Handling Ratings ...................................................................................................................................... 5 2 Electrical Characteristics ......................................................................................................................... 5 2.1 General Characteristics ........................................................................................................................................... 5 2.2 Device Characteristics ............................................................................................................................................. 8 2.3 Thermal Operating Characteristics ........................................................................................................................ 17 3 Typical Performance Characteristics ............................................................................................... 18 3.1 System Efficiency .................................................................................................................................................. 18 3.2 Standby Power ...................................................................................................................................................... 18 3.3 Digital Demodulation ............................................................................................................................................ 18 3.4 Foreign Object Detection ...................................................................................................................................... 18 3.5 Dynamic Input Power Limit ................................................................................................................................... 19 4 Device Information ................................................................................................................................. 19 4.1 Functional Block Diagram ...................................................................................................................................... 19 4.2 Product Features Overview ................................................................................................................................... 20 4.3 Pinout Diagram ..................................................................................................................................................... 21 4.4 Pin Function Description ....................................................................................................................................... 22 Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 2 Freescale Semiconductor 4.5 Ordering Information ............................................................................................................................................ 31 4.6 Package Outline Drawing ...................................................................................................................................... 31 5 Software Library ...................................................................................................................................... 31 5.1 Memory Map ........................................................................................................................................................ 32 5.2 Software Library and API Description .................................................................................................................... 32 6 Design Considerations ........................................................................................................................... 32 6.1 Electrical Design Considerations............................................................................................................................ 32 6.2 PCB Layout Considerations.................................................................................................................................... 33 6.3 Thermal Design Considerations ............................................................................................................................. 34 7 References and Links ............................................................................................................................. 34 7.1 References ............................................................................................................................................................ 34 7.2 Useful Links ........................................................................................................................................................... 34 Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 3 1 Absolute Maximum Ratings 1.1 Electrical Operating Ratings Table 1. Absolute Maximum Electrical Ratings (VSS = 0 V, VSSA = 0 V) Characteristic Symbol Notes 1 Min. Max. Unit Supply Voltage Range VDD –0.3 4.0 V Analog Supply Voltage Range VDDA –0.3 4.0 V ADC High Voltage Reference VREFHx –0.3 4.0 V Voltage difference VDD to VDDA ΔVDD –0.3 0.3 V Voltage difference VSS to VSSA ΔVss –0.3 0.3 V VIN Pin Group 1 –0.3 5.5 V VIN_RESET Pin Group 2 –0.3 4.0 V Oscillator Input Voltage Range VOSC Pin Group 4 –0.4 4.0 V Analog Input Voltage Range VINA Pin Group 3 –0.3 4.0 V VIC – –5.0 mA VOC – ±20.0 mA IIcont –25 25 mA Digital Input Voltage Range Input Voltage Range Input clamp current, per pin (VIN < VSS – 0.3 V) Output clamp current, per pin 2, 3 4 Contiguous pin DC injection current—regional limit sum of 16 contiguous pins Output Voltage Range (normal push-pull mode) Output Voltage Range (open drain mode) Output Voltage Range DAC Output Voltage Range Ambient Temperature Storage Temperature Range 1. 2. 3. 4. VOUT Pin Group 1,2 –0.3 4.0 V VOUTOD Pin Group 1 –0.3 5.5 V VOUTOD_RESET Pin Group 2 –0.3 4.0 V VOUT_DAC Pin Group 5 –0.3 4.0 V TA –40 85 °C TSTG –55 150 °C Default Mode: Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL Pin Group 5: DAC analog output Continuous clamp current. All 5 volt tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (= VSS –0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required. I/O is configured as push-pull mode. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 4 Freescale Semiconductor 1.2 Thermal Handling Ratings Table 2. Thermal Handling Ratings Symbol 1. 2. Description TSTG Storage temperature TSDR Solder temperature, lead-free Min. Max. Unit Notes –55 150 °C 1 – 260 °C 2 Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD Handling Ratings Table 3. ESD Handling Ratings Characteristic 1. 1 Min. Max. Unit ESD for Human Body Model (HBM) -2000 +2000 V ESD for Machine Model (MM) -200 +200 V ESD for Charge Device Model (CDM) -500 +500 V Latch-up current at TA= 85°C (ILAT) -100 +100 mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 1.4 Moisture Handling Ratings Table 4. Moisture Handling Ratings Symbol Description MSL 1. Moisture sensitivity level Min. Max. Unit Notes – 3 – 1 Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 2 Electrical Characteristics 2.1 General Characteristics Table 5. General Electrical Characteristics Recommended Operating Conditions (VREFLx = 0 V, VSSA = 0 V, VSS = 0 V) Characteristic 2 Supply Voltage Symbol VDD ,VDDA Notes Min. Typ. Max. Unit 2.7 3.3 3.6 V Test Conditions - Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 5 ADC (Cyclic) Reference VREFHA Voltage High VREFHB 3.0 VDDA V - Voltage difference VDD to VDDA ΔVDD -0.1 0 0.1 V - Voltage difference VSS to VSSA ΔVss -0.1 0 0.1 V - 5.5 V - VDD V - 0.35×VDD V - Input Voltage High (digital inputs) Voltage High Input Voltage Low (digital inputs) VIH 1 (Pin Group 1) 0.7×VDD VIH_RESET 1 (Pin Group 2) 0.7×VDD VIL 1 (Pin Group 1,2) VIHOSC 1 (Pin Group 4) 2.0 VDD + 0.3 V - VILOSC 1 (Pin Group 4) -0.3 0.8 V - IOH 1 (Pin Group 1) - -2 - Oscillator Input Voltage High XTAL driven by an external clock source Oscillator Input Voltage Low Output Source Current High (at VOH min.) 3,4 • Programmed for low drive strength • Programmed for high mA 1 (Pin Group 1) - -9 1 (Pin Group 1,2) - 2 drive strength Output Source Current Low (at VOL max.) 3,4 • Programmed for low IOL drive strength • Programmed for high mA 1 (Pin Group 1,2) - 9 drive strength Output Voltage High VOH 1 (Pin Group 1) VDD - 0.5 - - V IOH = IOHmax Output Voltage Low VOL 1 (Pin Group 1,2) - - 0.5 V IOL = IOLmax VIN = 2.4 V to 5.5 V 1 (Pin Group 1) Digital Input Current High IIH pull-up enabled or disabled - 0 +/-2.5 µA 0 +/-2 µA VIN = VDDA - 0 +/-2 µA VIN = VDDA 1 (Pin Group 2) Comparator Input Current VIN = 2.4 V to VDD IIHC 1 (Pin Group 3) Oscillator Input Current High IIHOSC 1 (Pin Group 4) Internal Pull-Up Resistance RPull-Up 20 - 50 kΩ - RPull-Down 20 - 50 kΩ - High Internal Pull-Down Resistance Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 6 Freescale Semiconductor Comparator Input Current IILC 1 (Pin Group 3) - 0 +/-2 µA VIN = 0V Oscillator Input Current Low IILOSC 1 (Pin Group 4) - 0 +/-2 µA VIN = 0V DAC Output Voltage Range VDAC 1 (Pin Group 5) V RLD = 3 kΩ, CLD = 400 pF IOZ 1 (Pin Group 1,2) - 0 +/-1 µA - VHYS 1 (Pin Group 1,2) 0.06×VDD - - V - CIN - 10 - pF - COUT - 10 - pF - Low VSSA + 0.04 - VDDA 0.04 1 Output Current High Impedance State Schmitt Trigger Input Hysteresis Input capacitance Output capacitance GPIO pin interrupt pulse Bus TINT_Pulse 6 1.5 - - TPort_H_DIS 7 5.5 - 15.1 ns Port rise and fall time (high drive strength). Slew enabled. TPort_H_EN 7 1.5 - 6.8 ns 2.7 ≤ VDD ≤ 3.6 V Port rise and fall time (low drive strength). Slew disabled. TPort_L_DIS 8 8.2 - 17.8 ns 2.7 ≤ VDD ≤ 3.6 V Port rise and fall time (low drive strength). Slew enabled. TPort_L_EN 8 3.2 - 9.2 ns 2.7 ≤ VDD ≤ 3.6 V fSYSCLK 0 - 100 MHz - fBUS - - 50 MHz - width 5 clock Port rise and fall time (high drive strength). Slew disabled. Device (system and core) clock frequency Bus clock 1. 2. 3. 4. 5. 6. 7. 8. - 2.7 ≤ VDD ≤ 3.6 V Default Mode o Pin Group 1: GPIO, TDI, TDO, TMS, TCK o Pin Group 2: o Pin Group 3: ADC and Comparator Analog Inputs o Pin Group 4: XTAL, EXTAL o Pin Group 5: DAC analog output ADC (Cyclic) specifications are not guaranteed when VDDA is below 3.0 V. Total chip source or sink current cannot exceed 75 mA. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive injection currents of 16 contiguous pins—is 25 mA. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming GPIOn_IPOLR and GPIOn_IENR. The greater synchronous and asynchronous timing must be met. 75 pF load. 15 pF load. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 7 2.2 Device Characteristics Table 6. General Device Characteristics Power mode Transition Behavior Symbol Description Min. Max. Unit 199 225 µs Notes After a POR event, the amount of delay TPOR from when VDD reaches 2.7 V to when the first instruction executes (over the operating temperature range). TS2R STOP mode to RUN mode 6.79 7.27 µs 1 TLPS2LPR LPS mode to LPRUN mode 240.9 551 µs 2 VLPS mode to VLPRUN mode 1424 1459 µs 4 WAIT mode to RUN mode 0.57 0.62 µs 3 LPWAIT mode to LPRUN mode 237.2 554 µs 2 VLPWAIT mode to VLPRUN mode 1413 1500 µs 4 TVLPS2VLPR TW2R TLPW2LPR TVLPW2VLPR Power Consumption Operating Behaviors Typical at 3.3 V, 25 °C Mode Conditions Max. Frequency Notes IDD IDDA 38.1 mA 9.9 mA 100 MHz core clock, 50 MHz peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered on, continuous MAC instructions with fetches from program Flash, all peripheral modules enabled, TMRs and SCIs using 1× RUN1 peripheral clock, NanoEdge within 100 MHz eFlexPWM using 2× peripheral clock, ADC/DAC (only one 12-bit DAC and all 6-bit DACs) powered on and clocked, comparator powered on, all ports configured as inputs with input low and no DC loads Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 8 Freescale Semiconductor 50 MHz core and peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered on, continuous MAC instructions with fetches from program Flash, all peripheral modules enabled, TMRs and SCIs using 1× RUN2 peripheral clock, NanoEdge within 50 MHz 27.6 mA 9.9 mA WAIT 50 MHz core and peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered on, core in WAIT state, all peripheral modules enabled, TMRs and SCIs using 1× clock, NanoEdge within eFlexPWM using 2× clock, ADC/DAC (one 12-bit DAC, all 6-bit DACs)/comparator powered off, all ports configured as inputs with input low and no DC loads 50 MHz 24.0 mA - STOP 4 MHz core and peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered off, core in STOP state, all peripheral module and core clocks are off, ADC/DAC/Comparator powered off, all ports configured as inputs with input low and no DC loads 4 MHz 6.3 mA - LPRUN 200 kHz core and peripheral clock from relaxation oscillator's low speed clock, relaxation oscillator in standby mode, regulators are in standby, PLL disabled, repeat NOP instructions, all peripheral modules enabled, except NanoEdge within eFlexPWM and cyclic ADCs, one 12-bit DAC and all 6-bit DACs enabled, simple loop with running from platform instruction buffer, all ports configured as inputs with input low and no DC loads 2 MHz 2.8 mA 3.1 mA LPWAIT 200 kHz core and peripheral clock from relaxation oscillator's low speed clock, relaxation oscillator in standby mode, regulators are in standby, PLL disabled, all peripheral modules enabled, except NanoEdge within eFlexPWM and cyclic ADCs, one 12-bit DAC and all 6-bit DACs enabled, core in WAIT mode, all ports configured as inputs with input low and no DC loads 2 MHz 2.7 mA 3.1 mA eFlexPWM using 2× peripheral clock, ADC/DAC (only one 12-bit DAC and all 6-bit DACs) powered on and clocked, comparator powered on, all ports configured as inputs with input low and no DC loads Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 9 LPSTOP 200 kHz core and peripheral clock from relaxation oscillator's low speed clock, relaxation oscillator in standby mode, regulators are in standby, PLL disabled, only PITs and COP enabled, other peripheral modules disabled and clocks gated off, core in STOP mode, all ports configured as inputs with input low and no DC loads 2 MHz 1.2 mA - VLPRUN 32 kHz core and peripheral clock from a 64 kHz external clock source, oscillator in power down, all relaxation oscillators disabled, large regulator is in standby, small regulator is disabled, PLL disabled, repeat NOP instructions, all peripheral modules, except COP and EWM, disabled and clocks gated off, simple loop running from platform instruction buffer, all ports configured as inputs with input low and no DC loads 200 kHz 0.7 mA - VLPWAIT 32 kHz core and peripheral clock from a 64 kHz external clock source, oscillator in power down, all relaxation oscillators disabled, large regulator is in standby, small regulator is disabled, PLL disabled, all peripheral modules, except COP, disabled and clocks gated off, core in WAIT mode, all ports configured as inputs with input low and no DC loads 200 kHz 0.7 mA - VLPSTOP 32 kHz core and peripheral clock from a 64 kHz external clock source, oscillator in power down, all relaxation oscillators disabled, large regulator is in standby, small regulator is disabled, PLL disabled, all peripheral modules, except COP, disabled and clocks gated off, core in STOP mode, all ports configured as inputs with input low and no DC loads 200 kHz 0.7 mA - Min. Max. Unit Notes 16 - ns 5 - ns 6 570.9 ns Min. Typ. Max. Unit - 2.0 - V Reset and Interrupt Timing Symbol tRA tRDA tIF Characteristic Minimum Assertion Duration desertion to First Address Fetch Delay from Interrupt Assertion to Fetch of first instruction (exiting STOP mode) 865 × TOSC + 8 × TSYSCLK 361.3 PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters Symbol VPOR_A Characteristic POR Assert Voltage 7 Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 10 Freescale Semiconductor VPOR_R POR Release Voltage VLVI_2p7 VLVI_2p2 8 - 2.7 - V LVI_2p7 Threshold Voltage - 2.73 - V LVI_2p2 Threshold Voltage - 2.23 - V Description Min. Max. Unit Notes fOP TCK frequency of operation DC fSYSCLK/8 MHz tPW TCK clock pulse width 50 - ns tDS TMS, TDI data set-up time 5 - ns tDH TMS, TDI data hold time 5 - ns tDV TCK low to TDO data valid - 30 ns tTS TCK low to TDO tri-state - 30 ns Min. Typ. Max. Unit - 1.22 - V Short Circuit Current - 600 - mA TRSC Short Circuit Tolerance (VCAP shorted to ground) - - 30 Mins VREF Reference Voltage (after trim) - 1.21 - V Min. Typ. Max. Unit - - 50 MHz JTAG Timing Symbol Regulator 1.2 V Parameters Symbol VCAP ISS Characteristic Output Voltage 9 10 External Clock Timing Symbol Characteristic fOSC Frequency of operation (external clock driver) tPW Clock pulse width trise 11 8 External clock input rise time 12 13 ns - - 1 ns - - 1 ns tfall External clock input fall time Vih Input high voltage overdrive by an external clock 0.85×VDD - - V Vil Input low voltage overdrive by an external clock - - 0.3×VDD V Min. Typ. Max. Unit 8 8 16 MHz 200 - 400 MHz 35.5 - 73.2 µs 40 50 60 % Phase-Locked Loop (PLL) Timing Symbol fRef_PLL fOP_PLL Characteristic PLL input reference frequency PLL output frequency 14 15 16 tLock_PLL PLL lock time tDC_PLL Allowed Duty Cycle of input reference Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 11 External Crystal or Resonator Specifications Symbol fXOSC Characteristic Min. Typ. Max. Unit 4 8 16 MHz Min. Typ. Max. Unit 7.84 8 8.16 MHz 7.76 8 8.24 MHz - 405 - kHz - +/-1.5 +/-1.5 +/-2 +/-3 % % 194 200 206 kHz 200 kHz Output Frequency Variation over 18 25 °C RUN Mode Due to temperature • 0 °C to 85 °C • -40 °C to 85 °C - +/-1.5 +/-1.5 +/-2 +/-3 % % Stabilization Time 19 • 8 MHz output 20 • 200 kHz output - 0.12 10 - µs µs 48 50 52 % Min. Typ. Max. Unit - 7.5 18 µs - 13 113 ms - 52 452 ms - - 60 µs Frequency of operation Relaxation Oscillator Electrical Specifications Symbol Characteristic 17 fROSC_8M fROSC_8M_Delta fROSC_200k 17 fROSC_200k_Delta 17 tStab tDC_ROSC 8 MHz Output Frequency RUN Mode • 0 °C to 85 °C • -40 °C to 85 °C Standby Mode (IRC trimmed @ 8 MHz) • -40 °C to 85 °C 8 MHz Frequency Variation over 25 °C RUN Mode Due to temperature • 0 °C to 85 °C • -40 °C to 85 °C 200 kHz Output Frequency RUN Mode • -40 °C to 85 °C 18 Output Duty Cycle Flash Specifications Symbol thvpgm4 thversscr Description Longword Program high-voltage time Sector Erase high-voltage time 21 21 thversall Erase All high-voltage time trd1sec1k Read 1s Section execution time (flash 22 sector) tpgmchk Program Check execution time 22 - - 45 µs trdrsrc Read Resource execution time 22 - - 30 µs tpgm4 Program Longword execution time - 65 145 µs - 14 114 ms tersscr Erase Flash Sector execution time 23 Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 12 Freescale Semiconductor trd1all trdonce tpgmonce Read 1s All Blocks execution time Read Once execution time 22 Program Once execution time 23 - - 0.9 ms - - 25 µs - 65 - µs - 70 575 ms 30 µs tersall Erase All Blocks execution time tvfykey Verify Backdoor Access Key execution 22 time - - Data retention after up to 10 K cycles 5 50 tflashret10k tflashret1k nflashcyc Data retention after up to 1 K cycles Cycling endurance 25 20 10 K 24 100 - years 24 - years 24 - cycles 50 K 12-bit Cyclic ADC Electrical Specifications Symbol VDDA VREFHX fADCCLK Characteristic Supply voltage 26 VREFH supply voltage 27 ADC conversion clock Min. Typ. Max. Unit 3.0 3.3 3.6 V VDDA V VDDA - 0.6 28 0.1 - 10 MHz -( VREFH - VREFL) VREFL - VREFH VREFL VREFH V V VREFL VSSA - VREFH VDDA V V Conversion time - 8 - tADCCLK tADCPU ADC power-up time (from adc_pdn) - 13 - tADCCLK IADCRUN ADC RUN current (per ADC block) - 1.8 - mA IADPWRDWN ADC power down current (adc_pdn enabled) - 0.1 - µA VREFH current (in external mode) - 190 225 µA - +/- 1.5 +/- 2.2 LSB 32 - +/- 0.5 +/- 0.8 LSB 32 29 RADC VADCIN tADC IVREFH Conversion range • Fully differential • Single-ended/unipolar Input voltage range (per input) • External Reference • Internal Reference 31 30 INLADC Integral non-linearity DNLADC Differential non-linearity VOFFSET Offset • Fully differential • Single ended/Unipolar - +/- 8 +/- 12 - mV mV EGAIN Gain Error - 0.996 to 1.004 0.99 to 1.101 - ENOB Effective number of bits - 10.6 - bits 34 - - +/-3 mA - 4.8 - pF Min. Typ. Max. Unit 31 33 IINJ CADCI Input injection current Input sampling capacitance 12-bit DAC Electrical Specifications Symbol Characteristic Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 13 35 tSETTLE Settling time under RLD = 3 kΩ, CLD = 400 - 1 - µs - - 11 µs - +/- 3 +/- 4 LSB 36 - +/- 0.8 +/- 0.9 LSB 36 pF tDACPU DAC power-up time (from PWRDWN release to valid DACOUT) 37 INLDAC Integral non-linearity DNLDAC Differential non-linearity MONDAC Monotonicity (> 6 sigma monotonicity, < 3.4 ppm non-monotonicity) VOFFSET Offset error 37 37 37 (5% to 95% of full range) - - +/- 25 +/- 43 mV - +/- 0.5 +/- 1.5 % EGAIN Gain error VOUT Output voltage range VSSA + 0.04 - VDDA - 0.04 V SNR Signal-to-noise ratio - 85 - dB Effective number of bits - 11 - bits Min. Typ. Max. Unit 2.7 - 3.6 V - 300 - µA - 36 - µA Vss - VDD V - - 20 mV - 5 13 mV - 25 48 mV - 55 105 mV - 80 148 mV ENOB (5% to 95% of full range) Guaranteed Comparator and 6-bit DAC Electrical Specifications Symbol VDD IDDHS IDDLS Description Supply voltage Supply current, High-speed mode(EN=1, PMODE=1) Supply current, Low-speed mode(EN=1, PMODE=0) VAIN Analog input voltage VAIO Analog input offset voltage VH Analog comparator hysteresis • CR0[HYSTCTR]=00 • CR0[HYSTCTR]=01 • CR0[HYSTCTR]=10 • CR0[HYSTCTR]=11 38 VCMPOh Output high VDD - 0.5 - - V VCMPOl Output low - - 0.5 V - 25 50 ns - 60 200 ns - 40 - µs - 7 - µA VDDA - VDD V tDHS tDLS tDInit Propagation delay, high-speed mode(EN=1, PMODE=1) 39 Propagation delay, low-speed mode(EN=1, PMODE=0) 39 Analog comparator initialization delay IDAC6b 6-bit DAC current adder (enabled) RDAC6b 6-bit DAC reference inputs 40 Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 14 Freescale Semiconductor INLDAC6b 6-bit DAC integral non-linearity -0.5 - 0.5 LSB 41 DNLDAC6b 6-bit DAC differential non-linearity -0.3 - 0.3 LSB 41 Min. Typ. Max. Unit - 100 - MHz - 312 - ps 1 - - ns - 25 - µs Min. Max. Unit Notes Timer input period 2Ttimer + 6 - ns 45 PINHL Timer input high/low period 1Ttimer + 3 - ns 45 POUT Timer output period 2Ttimer - 2 - ns 45 Timer output high/low period 1Ttimer - 2 - ns 45 eFlexPWM Timing Parameters Symbol fPWM Characteristic PWM clock frequency 42,43 SPWMNEP NanoEdge Placement (NEP) step size tDFLT Delay for fault input activating to PWM output deactivated tPWMPU 44 Power-up time Quad Timer Timing Symbol PIN POUTHL Characteristic QSPI Timing Min. Symbol tC Max. Characteristic Cycle time Unit Master Slave Master Slave 60 60 - - ns tELD Enable lead time - 20 - - ns tELG Enable lag time - 20 - - ns tCH Clock (SCLK) high time 28 28 - - ns tCL Clock (SCLK) low time 28 28 - - ns tDS Data set-up time required for inputs 20 1 - - ns tDH Data hold time required for inputs 1 3 - - ns tA Access time (time to data active from high-impedance state) 5 - ns tD Disable time (hold time to high-impedance state) 5 - ns tDV Data valid for outputs - - tDI Data invalid 0 0 - - ns tR Rise time - - 1 1 ns tF Fall time - - 1 1 ns ns QSCI Timing Symbol Characteristic BRSCI Baud rate PW RXD RXD pulse width Min. Max. Unit Notes - (fMAX_SCI /16) Mbit/s 46 0.965/BRSCI 1.04/BRSCI ns Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 15 PW TXD TXD pulse width 0.965/BRSCI 1.04/BRSCI ns Min. Max. Unit Baud rate - 1 Mbit/s TWAKEUP CAN Wakeup dominant pulse filtered - 1.5 µs TWAKEUP CAN Wakeup dominant pulse pass 5 - µs CAN Timing Symbol BRCAN Characteristic Notes IIC Timing Min. Symbol Max. Min. Max. SCL clock frequency 0 100 0 400 kHz tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 - 0.6 - µs tSCL_LOW LOW period of the SCL clock 4.7 - 1.3 - µs tSCL_HIGH HIGH period of the SCL clock 4 - 0.6 - µs - 0.6 - µs 49 0.9 tSU_STA Set-up time for a repeated START condition 4.7 tHD_DAT Data hold time for IIC bus devices 0 tSU_DAT 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Data set-up time 47 250 50 3.45 48 - 0 100 51 47 Notes µs - ns 48 tr Rise time of SDA and SCL signals - 1000 20 + 0.1Cb 300 ns 52 tf Fall time of SDA and SCL signals - 300 20 + 0.1Cb 300 ns 51 tSU_STOP Set-up time for STOP condition 4 - 0.6 - µs tBUS_Free Bus free time between STOP and START condition 4.7 - 1.3 - µs Pulse width of spikes that must be suppressed by the input filter N/A N/A 0 50 ns tSP 2. 3. 4. 5. Unit Min. fSCL 1. Max. Characteristic CPU clock = 4 MHz and System running from 8 MHz IRC Applicable to all wakeup times: Wakeup times (in 1,2,3,4) are measured from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from respective stop/wait mode. CPU clock = 200 kHz and 8 MHz IRC on standby. Exit via interrupt on Port C GPIO. Clock configuration: CPU and system clocks= 100 MHz; Bus Clock = 50 MHz. Exit via an interrupt on PortC GPIO. Using 64 KHz external clock; CPU Clock = 32 KHz. Exit via an interrupt on PortC GPIO. If the pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion must be greater than 21 ns. TOSC means oscillator clock cycle; TSYSCLK means system clock cycle. During 3.3 V VDD power supply ramp down. During 3.3 V VDD power supply ramp up (gated by LVI_2p7). Value is after trim. Guaranteed by design. The chip may not function if the high or low pulse width is smaller than 6.25 ns. External clock input rise time is measured from 10% to 90%. External clock input fall time is measured from 90% to 10%. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8 MHz input. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must be set to 400 MHz. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 16 Freescale Semiconductor 16. 17. 18. 19. 20. 21. 22. 23. 24. This is the time required after the PLL is enabled to ensure reliable operation. Frequency after application of 8 MHz trimmed. Frequency after application of 200 kHz trimmed. Standby to run mode transition. Power down to run mode transition. Maximum time based on expectations at cycling end-of-life. Assumes 25 MHz flash clock frequency. Maximum times for erase parameters based on expectations at cycling end-of-life. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 25. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 26. The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed. 27. When the input is at the VREFL level, the resulting output will be all zeros (hex 000), plus any error contribution due to offset and gain error. When the input is at the VREFH level the output will be all ones (hex FFF), minus any error contribution due to offset and gain error. 28. ADC clock duty cycle is 45% ~ 55%. 29. Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively. 30. In unipolar mode, positive input must be ensured to be always greater than negative input. 31. INLADC/DNLADC is measured from VADCIN = VREFL to VADCIN = VREFH using Histogram method at x1 gain setting. 32. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain setting. 33. Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk). 34. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the ADC. 35. Settling time is swing range from VSSA to VDDA. 36. LSB = 0.806 mV. 37. No guaranteed specification within 5% of VDDA or VSSA. 38. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD-0.7 V. 39. Signal swing is 100 mV. 40. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 41. 1 LSB = Vreference/64. 42. Reference IPbus clock of 100 MHz in NanoEdge Placement mode. 43. Temperature and voltage variations do not affect NanoEdge Placement step size. 44. Powerdown to NanoEdge mode transition. 45. Ttimer = Timer input clock cycle. For 100 MHz operation, Ttimer = 10 ns. 46. fMAX_SCI is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock or 2x bus clock for the device. 47. The master mode IIC deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 48. The maximum tHD_DAT must be met only if the device does not stretch the LOW period (tSCL_LOW) of the SCL signal. 49. Input signal Slew = 10 ns and Output Load = 50 pF 50. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 51. A Fast mode IIC bus device can be used in a Standard mode IIC bus system, but the requirement tSU_DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU_DAT = 1000 + 250 = 1250 ns (according to the Standard mode IIC bus specification) before the SCL line is released. 52. Cb = total capacitance of the one bus line in pF. 2.3 Thermal Operating Characteristics Table 7. General Thermal Characteristics Symbol Description Min. Max. Unit TJ Die junction temperature -40 125 °C TA Ambient temperature -40 85 °C Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 17 3 Typical Performance Characteristics 3.1 System Efficiency The typical maximum system efficiency (receiver output power vs. transmitter input power) on Freescale WCT1101 based transmitter solutions can usually reach 70 plus percentage. Of course, the detailed number depends on the specific solution type. For example, Freescale A11 reference solution has more than 75% system efficiency with bq51013AEVM-764 receiver module. Note: Power components are the main factor to determine the system efficiency, such as drivers and MOSFETs. 3.2 Standby Power The purpose of the standby mode of operation is to reduce the power consumption of a wireless power transfer system when power transfer is not required. There are two ways to enter standby mode. The first is when the transmitter doesn’t detect the presence of a valid receiver. The second is when the receiver sends only an End Power Transfer Packet. In standby mode, the transmitter only monitors if a receiver is placed on the active charging area of the transmitter or removed there from. It is recommended that the transmitter’s power consumption in standby mode meets the relative regional regulations especially for “No-load power consumption”. In Freescale A11 reference design solution: Transmitter power consumption in standby mode with Analog PING technology: < 12 mA (60 mW with 5 V DC input) Transmitter power consumption in standby mode with Touch Sensor technology: < 5 mA (25 mW with 5 V DC input) 3.3 Digital Demodulation To optimize system BOM cost, WCT1101 solution employs digital demodulation algorithm to communicate with receiver. This method can achieve high performance, low cost, and very simple coil signal sensing circuit with less component number. 3.4 Foreign Object Detection WCT1101 solution employs flexible, intelligent and easy-to-use FOD algorithm to ensure accurate foreign metal objects detection. With Freescale FreeMASTER GUI tool, FOD algorithm can be easily calibrated to get accurate power loss information especially for very sensitive foreign objects. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 18 Freescale Semiconductor 3.5 Dynamic Input Power Limit When the transmitter is powered by a limited power supply, such as USB power, WCT1101 can limit the transmitter output power and provide necessary margin relative to the input power supply capability. By monitoring the input voltage and input current of the transmitter, when it drops to a specified level and still positive Control Error Packet (CEP) is received, WCT1101 will stop increasing power output and control transmitter operation in input power limit status. Users can know the system is in DIPL control mode by LED indication, LED1 and LED2 will be in fast blinking mode when input power is limited. WCT1101 will exit DIPL control mode and return to normal PID control mode if a negative Control Error Packet (CEP) is received to reduce output power. The input voltage level for DIPL control can be configured in the WCT1101 example project. 4 Device Information 4.1 Functional Block Diagram This functional block diagram just shows the functional block pin assignment information of MWCT1101CLH. For the detailed pin multiplexing information, please see Section 4.4 of “Pin Function Description”. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 19 Figure 3. MWCT1101CLH Function Block Diagram 4.2 Product Features Overview The following table highlights the main on-chip resource features of MWCT1101 device. Table 8. Product Features Overview Part Maximum Core/Bus Clock (MHz) Maximum Fully Run Current Consumption (mA) WCT1101 100/50 38.1 (VDD) + 9.9 (VDDA) On-Chip Program Flash Memory Size (KB) 64 On-Chip SRAM Memory Size (KB) 8 Memory Resource Protection Yes Inter-Peripheral Crossbar Switches with AOI Yes On-Chip Relaxation Oscillator 1 (8 MHz) + 1 (200 kHz) Windowed Computer Operating Properly 1 External Watchdog Monitor 1 Cyclic Redundancy Check 1 Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 20 Freescale Semiconductor Periodic Interrupt Timer 2 Quad Timer 1x4 12-bit Cyclic ADC Channels 2x8 High-Resolution 8 Standard 4 PWM Channels 12-bit DAC 2 Analog Comparator /w 6-bit REF DAC 4 DMA Channels 4 Queued Serial Communications Interface 2 Queued Serial Peripheral Interface 2 Inter-Integrated Circuit 1 Controller Area Network (MSCAN) 1 GPIO 54 Package 64 LQFP 4.3 Pinout Diagram Figure 4. MWCT1101CLH Pinout Diagram Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 21 4.4 Pin Function Description By default, each pin is configured for its primary function (listed first). Any alternative functionality, shown in parentheses, can be programmed through GPIO module peripheral enable registers and SIM module GPIO peripheral select registers. Table 9. Pin Signal Descriptions Signal Name Pin No. Multiplexing Signals Function Description Test Clock Input — This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-up resistor. A Schmitt-trigger input is used for noise immunity. TCK 1 GPIOD2 Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TCK. — This input is a direct hardware reset on the processor. When is asserted low, the device is initialized and placed in the reset state. A Schmitt-trigger input is used for noise immunity. The internal reset signal is de-asserted synchronous with the internal clocks after a fixed number of internal clocks. 2 GPIOD4 Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. If functionality is disabled in this mode and the chip can be reset only via POR, COP reset, or software reset. After reset, the default state is . Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOC0 3 EXTAL/CLKIN0 EXTAL — External Crystal Oscillator Input. This input connects the internal crystal oscillator input to an external crystal or ceramic resonator. CLKIN0 — This pin serves as an external clock input 0. After reset, the default state is GPIOC0. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOC1 4 XTAL XTAL — External Crystal Oscillator Output. This output connects the internal crystal oscillator output to an external crystal or ceramic resonator. After reset, the default state is GPIOC1. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. TXD0 — The SCI0 transmit data output or transmit/receive in single wire operation. GPIOC2 5 TXD0/XB_OUT 11/XB_IN2/CLK O0 XB_OUT11 — Crossbar module output 11. XB_IN2 — Crossbar module input 2. CLKO0 — This is a buffered clock output 0; the clock source is selected by clock out select (CLKOSEL) bits in the clock output select register (CLKOUT) of the SIM. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 22 Freescale Semiconductor After reset, the default state is GPIOC2. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. RXD0 — The SCI0 receive data input. GPIOF8 6 RXD0/XB_OUT 10/CMPD_O/P WM_2X XB_OUT10 — Crossbar module output 10. CMPD_O — Analog comparator D output. PWM_2X — NanoEdge eFlexPWM sub-module 2 output X or input capture X. After reset, the default state is GPIOF8. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. TA0 — Quad timer module A channel 0 input/output. GPIOC3 7 TA0/CMPA_O/ RXD0/CLKIN1 CMPA_O — Analog comparator A output. RXD0 — The SCI0 receive data input. CLKIN1 — This pin serves as an external clock input 1. After reset, the default state is GPIOC3. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. TA1 — Quad timer module A channel 1 input/output. GPIOC4 8 TA1/CMPB_O/X B_IN6/ CMPB_O — Analog comparator B output. XB_IN6 — Crossbar module input 6. — External watchdog monitor output. After reset, the default state is GPIOC4. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA7 9 ANA7&CMPD_I N3 ANA7&CMPD_IN3 — Analog input to channel 7 of ADCA and input 3 of analog comparator D. When used as an analog input, the signal goes to the ANA7 and CMPD_IN3. After reset, the default state is GPIOA7. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA6 GPIOA5 10 11 ANA6&CMPD_I N2 ANA5&CMPD_I N1 ANA6&CMPD_IN2 — Analog input to channel 6 of ADCA and input 2 of analog comparator D. When used as an analog input, the signal goes to the ANA6 and CMPD_IN2. After reset, the default state is GPIOA6. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA5&CMPD_IN1 — Analog input to channel 5 of ADCA and input 1 of analog comparator D. When used as an analog input, the signal goes to the Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 23 ANA5 and CMPD_IN1. After reset, the default state is GPIOA5. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA4 12 ANA4&CMPD_I N0 ANA4&CMPD_IN0 — Analog input to channel 4 of ADCA and input 0 of analog comparator D. When used as an analog input, the signal goes to the ANA4 and CMPD_IN0. After reset, the default state is GPIOA4. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA0 13 ANA0&CMPA_I N3/CMPC_O ANA0&CMPA_IN3 — Analog input to channel 0 of ADCA and input 3 of analog comparator A. When used as an analog input, the signal goes to the ANA0 and CMPA_IN3. CMPC_O — Analog comparator C output. After reset, the default state is GPIOA0. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA1 14 ANA1&CMPA_I N0 ANA1 and CMPA_IN0 — Analog input to channel 1 of ADCA and input 0 of analog comparator A. When used as an analog input, the signal goes to the ANA1 and CMPA_IN0. After reset, the default state is GPIOA1. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA2 15 ANA2&VREFH A&CMPA_IN1 ANA2&VREFHA&CMPA_IN1 — Analog input to channel 2 of ADCA and analog references high of ADCA and input 1 of analog comparator A. When used as an analog input, the signal goes to ANA2 and VREFHA and CMPA_IN1. ADC control register configures this input as ANA2 or VREFHA. After reset, the default state is GPIOA2. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOA3 16 ANA3&VREFLA &CMPA_IN2 ANA3&VREFLA&CMPA_IN2 — Analog input to channel 3 of ADCA and analog references low of ADCA and input 2 of analog comparator A. When used as an analog input, the signal goes to ANA3 and VREFLA and CMPA_IN2. ADC control register configures this input as ANA3 or VREFLA. After reset, the default state is GPIOA3. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOB7 GPIOC5 17 18 ANB7&CMPB_I N2 DACA_O/XB_IN 7 ANB7&CMPB_IN2 — Analog input to channel 7 of ADCB and input 2 of analog comparator B. When used as an analog input, the signal goes to the ANB7 and CMPB_IN2. After reset, the default state is GPIOB7. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. DACA_O — 12-bit Digital-to-Analog Converter A output. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 24 Freescale Semiconductor XB_IN7 — Crossbar module input 7. After reset, the default state is GPIOC5. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOB6 19 ANB6&CMPB_I N1 ANB6&CMPB_IN1 — Analog input to channel 6 of ADCB and input 1 of analog comparator B. When used as an analog input, the signal goes to the ANB6 and CMPB_IN1. After reset, the default state is GPIOB6. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOB5 20 ANB5&CMPC_I N2 ANB5&CMPC_IN2 — Analog input to channel 5 of ADCB and input 2 of analog comparator C. When used as an analog input, the signal goes to the ANB5 and CMPC_IN2. After reset, the default state is GPIOB5. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOB4 21 ANB4&CMPC_I N1 VDDA 22 - VSSA 23 - GPIOB0 24 ANB0&CMPB_I N3 ANB4&CMPC_IN1 — Analog input to channel 4 of ADCB and input 1 of analog comparator C. When used as an analog input, the signal goes to the ANB4 and CMPC_IN1. After reset, the default state is GPIOB4. Analog Power — This pin supplies 3.3 V power to the analog modules. It must be connected to a clean analog power supply. Analog Ground — This pin supplies an analog ground to the analog modules. It must be connected to a clean power supply. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB0&CMPB_IN3 — Analog input to channel 0 of ADCB and input 3 of analog comparator B. When used as an analog input, the signal goes to ANB0 and CMPB_IN3. After reset, the default state is GPIOB0. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOB1 25 ANB1&CMPB_I N0/DACB_O ANB1&CMPB_IN0 — Analog input to channel 1 of ADCB and input 0 of analog comparator B. When used as an analog input, the signal goes to ANB1 and CMPB_IN0. DACB_O — 12-bit Digital-to-Analog Converter B output. VCAP1 26 - GPIOB2 27 ANB2&VREFH B&CMPC_IN3 After reset, the default state is GPIOB1. Connect a 2.2 μF or greater bypass capacitor between this pin and VSS to stabilize the core voltage regulator output required for proper device operation. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB2&VREFHB&CMPC_IN3 — Analog input to channel 2 of ADCB and analog references high of ADCB and input 3 of analog comparator C. When used as an analog input, the signal goes to ANB2 and VREFHB and CMPC_IN3. ADC control register configures this input as ANB2 or VREFHB. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 25 After reset, the default state is GPIOB2. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOB3 28 ANB3&VREFLB &CMPC_IN0 VDD1 VSS1 29 30 - ANB3&VREFLB&CMPC_IN0 — Analog input to channel 3 of ADCB and analog references low of ADCB and input 0 of analog comparator C. When used as an analog input, the signal goes to ANB3 and VREFLB and CMPC_IN0. ADC control register configures this input as ANB3 or VREFLB. After reset, the default state is GPIOB3. I/O Power — Supplies 3.3 V power to on-chip digital module. I/O Ground — Provides ground on-chip digital module. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. TA2 — Quad timer module A channel 2 input/output. GPIOC6 31 TA2/XB_IN3/C MP_REF/ XB_IN3 — Crossbar module input 3. CMP_REF — Input 5 of analog comparator A and B and C and D. — is used in slave mode to indicate to the SPI0 module that the current transfer is to be received. After reset, the default state is GPIOC6. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. — is used in slave mode to indicate to the SPI0 module that the current transfer is to be received. GPIOC7 32 /TXD0/XB_I N8 TXD0 — SCI0 transmit data output or transmit/receive in single wire operation. XB_IN8 — Crossbar module input 8. After reset, the default state is GPIOC7. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOC8 33 MISO0 /RXD0/XB_IN9/ XB_OUT6 MISO0 — Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO0 line of a slave device is placed in the high-impedance state if the slave device is not selected. RXD0 — SCI0 receive data input. XB_IN9 — Crossbar module input 9. XB_OUT6 — Crossbar module output 6. After reset, the default state is GPIOC8. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOC9 34 SCLK0/XB_IN4/ TXD0/XB_OUT 8 SCLK0 — The SPI0 serial clock. In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 26 Freescale Semiconductor XB_IN4 — Crossbar module input 4. TXD0 — SCI0 transmit data output or transmit/receive in single wire operation. XB_OUT8 — Crossbar module output 8. After reset, the default state is GPIOC9. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. MOSI0 — Master out/slave in. In master mode, this pin serves as the data output. In slave mode, this pin serves as the data input. GPIOC10 35 MOSI0 /XB_IN5/MISO0 /XB_OUT9 XB_IN5 — Crossbar module input 5. MISO0 — Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO0 line of a slave device is placed in the high-impedance state if the slave device is not selected. XB_OUT9 — Crossbar module output 9. After reset, the default state is GPIOC10. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. XB_IN6 — Crossbar module input 6. GPIOF0 36 XB_IN6/SCLK1 SCLK1 — The SPI1 serial clock. In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. After reset, the default state is GPIOF0. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. CANTX — CAN transmit data output. GPIOC11 37 CAN_TX/SCL0/ TXD1 SCL0 — IIC0 serial clock. TXD1 — SCI1 transmit data output or transmit/receive in single wire operation. After reset, the default state is GPIOC11. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. CANRX — CAN receive data input. GPIOC12 38 CAN_RX/SDA0/ RXD1 SDA0 — IIC0 serial data line. RXD1 — SCI1 receive data input. After reset, the default state is GPIOC12. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOF2 39 SCL0/XB_OUT 6/MISO1 SCL0 — IIC0 serial clock. XB_OUT6 — Crossbar module output 6. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 27 MISO1 — Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO1 line of a slave device is placed in the high-impedance state if the slave device is not selected. After reset, the default state is GPIOF2. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. SDA0 — IIC0 serial data line. GPIOF3 40 SDA0/XB_OUT 7/ MOSI1 XB_OUT7 — Crossbar module output 7. MOSI1 — Master out/slave in. In master mode, this pin serves as the data output. In slave mode, this pin serves as the data input. After reset, the default state is GPIOF3. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. TXD1 — The SCI1 transmit data output or transmit/receive in single wire operation. GPIOF4 41 TXD1/XB_OUT 8/PWM_0X/PW M_FAULT6 XB_OUT8 — Crossbar module output 8. PWM_0X — NanoEdge eFlexPWM sub-module 0 output X or input capture X. PWM_FAULT6 — NanoEdge eFlexPWM fault input 6. After reset, the default state is GPIOF4. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. RXD1 — The SCI1 receive data input. GPIOF5 42 RXD1/XB_OUT 9/PWM_1X/PW M_FAULT7 XB_OUT9 — Crossbar module output 9. PWM_1X — NanoEdge eFlexPWM sub-module 1 output X or input capture X. PWM_FAULT7 — NanoEdge eFlexPWM fault input 7. VSS2 VDD2 43 44 - GPIOE0 45 PWM_0B After reset, the default state is GPIOF5. I/O Ground — Provides ground to on-chip digital module. I/O Power — Supplies 3.3 V power to on-chip digital module. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_0B — NanoEdge eFlexPWM sub-module 0 output B or input capture B. After reset, the default state is GPIOE0. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOE1 46 PWM_0A PWM_0A — NanoEdge eFlexPWM sub-module 0 output A or input capture A. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 28 Freescale Semiconductor After reset, the default state is GPIOE1. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOE2 47 PWM_1B PWM_1B — NanoEdge eFlexPWM sub-module 1 output B or input capture B. After reset, the default state is GPIOE2. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOE3 48 PWM_1A PWM_1A — NanoEdge eFlexPWM sub-module 1 output A or input capture A. After reset, the default state is GPIOE3. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. TA3 — Quad timer module A channel 3 input/output. GPIOC13 49 TA3/XB_IN6/ XB_IN6 — Crossbar module input 6. — External watchdog monitor output. After reset, the default state is GPIOC13. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOF1 50 CLKO1/XB_IN7/ CMPD_O CLKO1 — This is a buffered clock output 1; the clock source is selected by clock out select (CLKOSEL) bits in the clock output select register (CLKOUT) of the SIM. XB_IN7 — Crossbar module input 7. CMPD_O — Analog comparator D output. After reset, the default state is GPIOF1. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOE4 51 PWM_2B/XB_I N2 PWM_2B — NanoEdge eFlexPWM sub-module 2 output B or input capture B. XB_IN2 — Crossbar module input 2. After reset, the default state is GPIOE4. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOE5 52 PWM_2A/XB_I N3 PWM_2A — NanoEdge eFlexPWM sub-module 2 output A or input capture A. XB_IN3 — Crossbar module input 3. GPIOE6 53 PWM_3B/XB_I N4 After reset, the default state is GPIOE5. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_3B — NanoEdge eFlexPWM sub-module 3 output B or input capture B. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 29 XB_IN4 — Crossbar module input 4. After reset, the default state is GPIOE6. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOE7 54 PWM_3A/XB_I N5 PWM_3A — NanoEdge eFlexPWM sub-module 3 output A or input capture A. XB_IN5 — Crossbar module input 5. After reset, the default state is GPIOE7. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOC14 55 SDA0/XB_OUT 4/PWM_FAULT 4 SDA0 — IIC0 serial data line. XB_OUT4 — Crossbar module output 4. PWM_FAULT4 — NanoEdge eFlexPWM fault input 4. After reset, the default state is GPIOC14. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. GPIOC15 56 SCL0/XB_OUT 5/PWM_FAULT 5 SCL0 — IIC0 serial clock. XB_OUT5 — Crossbar module output 5. PWM_FAULT5 — NanoEdge eFlexPWM fault input 5. After reset, the default state is GPIOC15. Connect a 2.2 μF or greater bypass capacitor between this pin and VSS to stabilize the core voltage regulator output required for proper device operation. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. VCAP2 57 - GPIOF6 58 PWM_3X/XB_I N2 PWM_3X — NanoEdge eFlexPWM sub-module 3 output X or input capture X. XB_IN2 — Crossbar module input 2. After reset, the default state is GPIOF6. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. CMPC_O— Analog comparator C output. GPIOF7 59 CMPC_O/ B_IN3 /X — is used in slave mode to indicate to the SPI1 module that the current transfer is to be received. XB_IN3 — Crossbar module input 3. VDD3 VSS3 60 61 - TDO 62 GPIOD1 After reset, the default state is GPIOF7. I/O Power — Supplies 3.3 V power to on-chip digital module. I/O Ground — Provides ground to on-chip digital module. Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 30 Freescale Semiconductor shift-DR controller states, and changes on the falling edge of TCK. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDO. Test Mode Select Input — This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. TMS 63 GPIOD3 Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TMS. NOTE: Always tie the TMS pin to VDD through a 2.2 kΩ resistor if need to keep on-board debug capability. Otherwise, directly tie to VDD. Test Data Input — This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. TDI 64 GPIOD0 Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDI. 4.5 Ordering Information Table 1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office to determine availability and to order this device. Table 10 MWCT1101CLH Ordering Information Device Supply Voltage Package Type Pin Count Ambient Temp. Order Number MWCT1101CLH 3.0 to 3.6V LQFP 64 -40 to +85℃ MWCT1101CLH 4.6 Package Outline Drawing To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number of 98ASS23234W. 5 Software Library WCT1101 can not only run the core wireless charging function, but also allow user to add user application functions. Freescale provides two Wireless Charging Transmitter (WCT) software libraries (WCT1000 TX library and WCT1200 TX library) for different solutions design on WCT1101. In these libraries, low level drivers of HAL (Hardware Abstract Layer), callback functions for library access are open to user. For the software API and library details, see WCT1000 TX Library User Guide.pdf (WCT1000LIBUG). Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 31 5.1 Memory Map WCT1101 has large on-chip Flash memory and RAM for user design. Besides for wireless charging transmitter library code, the user can develop private functions and link it to library through predefined APIs. Table 11. WCT1101 Memory Footprint Part Memory Total Size Library Size FreeMASTER Size EEPROM Size Free Size Flash 64 Kbytes 19 Kbytes 1.5 Kbytes 1 Kbytes 42.5 Kbytes RAM 8 Kbytes 5.8 Kbytes 0.1 Kbytes 0 Kbytes 2.1 Kbytes WCT1101 5.2 Software Library and API Description For more and detailed information about WCT software library and API definition, see WCT1000 TX Library User Guide.pdf (WCT1000LIBUG). 6 Design Considerations 6.1 Electrical Design Considerations Use the following list of considerations to assure correct operation of the device and system: The minimum bypass requirement is to place 0.01 - 0.1μF capacitors positioned as near as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerances. Bypass the VDD and VSS with approximately 10μF, plus the number of 0.1μF ceramic capacitors. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. Take special care to minimize noise levels on the VDDA, and VSSA pins. Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If an analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite bead in serial with VDDA trace. If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the range of 4.7 kΩ – 10 kΩ; and the capacitor value should be in the range of 0.1μF – 4.7μF. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 32 Freescale Semiconductor Add a 2.2 kΩ external pull-up on the TMS pin of the JTAG port to keep device in a restate during normal operation if JTAG converter is not present. During reset and after reset but before I/O initialization, all I/O pins are at input mode with internal weak pull-up. To eliminate PCB trace impedance effect, each ADC input should have a no less than 33pF/10 Ω RC filter. To assure chip reliable operation, please reserve enough margin for chip electrical design. The figure 6 shows the relationship between electrical ratings and electrical operating characteristics for correct chip operation. ctr Ele Fatal range g tin l ra ica ) in. (m ctr Ele Degraded operating range Expected permanent failure - No permanent failure - Possible decreased life g atin per lo a c i ch ) in. (m cs isti r e ct ara Normal operating range - No permanent failure - Correct operation - Possible incorrect operation ctr Ele g atin per lo a c i ch ) ax. (m cs isti r e ct ara ctr Ele g tin l ra ica Degraded operating range - No permanent failure - Possible decreased life ) ax. (m Fatal range Expected permanent failure - Possible incorrect operation Operating (power on) in ndl Ha g atin gr ) in. (m in ndl Ha g atin gr ) ax. (m Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure Handling (power off) Figure 6. Relationship between Ratings and Operating Characteristics 6.2 PCB Layout Considerations Provide a low-impedance path from the board power supply to each VDD pin on the device and from the board ground to each VSS pin. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS pins are as short as possible. PCB trace lengths should be minimal for high-frequency signals. Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces. The decoupling capacitors of 0.1μF must be placed on the VDD pins as close as possible, and place those ceramic capacitors on the same PCB layer with WCT1101 device. VIA is not recommend between the VDD pins and decoupling capacitors. Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 Freescale Semiconductor 33 The WCT1101 bottom EP pad should be soldered to the ground plane, which will make the system more stable, and VIA matrix method can be used to connect this pad to the ground plane. As the Wireless Charging system functions as a switching-mode power supply, the power components layout is very important for the whole system power transfer efficiency and EMI performance. The power routing loop should be small and short as can as possible, especially for the resonant network, the traces of this circuit should be short and wide, and the current loop should be optimized smaller for the MOSFETs, resonant capacitor and primary coil. Another important thing is that the control circuit and power circuit should be separated. 6.3 Thermal Design Considerations WCT1101 power consumption is not so critical, so there is not additional part needed for power dissipation. However, the power inverter needs the additional PCB Cu copper to dissipate the heat, so good thermal package MOSFET is recommended to select, such as DFN package, and for the resonant capacitor, COG material, and 1206 or 1210 package are recommended to meet the thermal requirement. And the worst thermal case is on the inverter, so the user should make some special actions to dissipate the heat for good transmitter system thermal performance. 7 References and Links 7.1 References WCT1000 A11 Reference Design System User Guide (WCT1000SYSUG) WCT1000 TX Library User Guide (WCT1000LIBUG) WCT Runtime Debug User Guide (WCT1XXXRTDUG) WCT1000 A11 Reference Design Calibration User Guide (WCT1000CALUG) WPC Low Power Wireless Transfer System Description Part 1: Interface Definition Version 1.1 7.2 Useful Links freescale.com freescale.com\wirelesscharging www.wirelesspowerconsortium.com Consumer Low Power Wireless Transmitter Controller, Rev. 1.0 34 Freescale Semiconductor How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ©2014 Freescale Semiconductor, Inc. Document Number: WCT1101DS Rev. 1.0 02/2014