Freescale Semiconductor Data Sheet WCT1111DS Features • • • • • • • • • • • • • • Compliant with the latest version Wireless Power Consortium (WPC) specifications transmitter design Supports charging medium power receiver and low power receiver compliant with WPC specifications Supports wide DC input voltage ranging from 4.2 V, typically 12 V and 19 V Integrated digital demodulation on chip Supports two-way communication, transmitter to receiver by FSK and receiver to transmitter by ASK Supports all types of receiver modulation strategies (AC capacitor, AC resistor and DC resistor) Supports medium power Foreign Object Detection (FOD) framework Super low standby power by Freescale Touch technology Supports medium power consumer power transmitter solutions by using frequency control, duty cycle control, phase shift control, and topology switch LED for system status indication Over-voltage/current/temperature protection Supports CAN/IIC/SCI/SPI interfaces Software-based solution to provide maximum design freedom and product differentiation FreeMASTER GUI tool to enable configuration, calibration and debugging Applications • Medium Power Wireless Power Transmitter Medium power consumer power transmitter solution with frequency & duty cycle control, phase-shift control, or topology switch (WPC MP-Ax types, MP-Bx types or customer properties) Document Number: WCT1111DS Rev. 1.1, 09/2015 Overview Description The WCT1111 is a wireless power transmitter controller that integrates all required functions for WPC “Qi” compliant wireless power transmitter design. It’s an intelligent device to work with Freescale touch sensing technology or use periodically analog PING (configurable by user) to detect a mobile device for charging while gaining super low standby power. Once the mobile device is detected, the WCT1111 controls the power transfer by adjusting the operation frequency and duty cycle, or switching topology, or adjusting the phase shift of the power stage according to message packets sent by the mobile device. To maximize the design freedom and product differentiation, the WCT1111 supports medium power consumer power transmitter design (WPC MP-Ax types, MP-Bx types or customization) using frequency and duty cycle control, or phase shift control or topology switch by software based solution, which can support wireless charging with both medium power receiver and low power receiver. In addition, easy-to-use FreeMASTER GUI tool has configuration, calibration and debugging functions to provide a user-friendly design experience and reduced time-to-market. The WCT1111 includes digital demodulation module to reduce external components, FSK modulation to support two-way communication, over-voltage/current/temperature protection, FOD method to protect from overheating by misplaced metallic foreign objects and general CAN/IIC/SCI/SPI interfaces for external communications. It also handles any abnormal condition and operational status, and provides comprehensive indicator outputs for robust system design. Wireless Charging System Functional Diagram © 2015 Freescale Semiconductor, Inc. All rights reserved. _______________________________________________________________________ Contents 1 Absolute Maximum Ratings .................................................................................................................... 4 1.1 Electrical Operating Ratings .................................................................................................................................... 4 1.2 Thermal Handling Ratings ....................................................................................................................................... 5 1.3 ESD Handling Ratings .............................................................................................................................................. 5 1.4 Moisture Handling Ratings ...................................................................................................................................... 5 2 Electrical Characteristics ......................................................................................................................... 6 2.1 General Characteristics ........................................................................................................................................... 6 2.2 Device Characteristics ............................................................................................................................................. 8 2.3 Thermal Operating Characteristics ........................................................................................................................ 18 3 Typical Performance Characteristics ............................................................................................... 19 3.1 System Efficiency .................................................................................................................................................. 19 3.2 Standby Power ...................................................................................................................................................... 19 3.3 Digital Demodulation ............................................................................................................................................ 19 3.4 Foreign Object Detection ...................................................................................................................................... 19 4 Device Information ................................................................................................................................. 20 4.1 Functional Block Diagram ...................................................................................................................................... 20 4.2 Product Features Overview ................................................................................................................................... 20 4.3 Pinout Diagram ..................................................................................................................................................... 22 4.4 Pin Function Description ....................................................................................................................................... 22 4.5 Ordering Information ............................................................................................................................................ 32 4.6 Package Outline Drawing ...................................................................................................................................... 32 WCT1111DS, Rev. 1.1, 09/2015 2 Freescale Semiconductor 5 Software Library ...................................................................................................................................... 33 5.1 Memory Map ........................................................................................................................................................ 33 5.2 Software Library and API Description .................................................................................................................... 33 6 Design Considerations ........................................................................................................................... 34 6.1 Electrical Design Considerations............................................................................................................................ 34 6.2 PCB Layout Considerations.................................................................................................................................... 35 6.3 Thermal Design Considerations ............................................................................................................................. 36 7 Links ............................................................................................................................................................. 37 WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 3 1 Absolute Maximum Ratings 1.1 Electrical Operating Ratings Table 1. Absolute Maximum Electrical Ratings (VSS = 0 V, VSSA = 0 V) Characteristic Symbol Notes 1 Min. Max. Unit Supply Voltage Range VDD –0.3 4.0 V Analog Supply Voltage Range VDDA –0.3 4.0 V ADC High Voltage Reference VREFHx –0.3 4.0 V Voltage difference VDD to VDDA ΔVDD –0.3 0.3 V Voltage difference VSS to VSSA ΔVss –0.3 0.3 V Digital Input Voltage Range VIN Pin Group 1 –0.3 5.5 V RESET Input Voltage Range VIN_RESET Pin Group 2 –0.3 4.0 V Oscillator Input Voltage Range VOSC Pin Group 4 –0.4 4.0 V Analog Input Voltage Range VINA Pin Group 3 –0.3 4.0 V VIC – –5.0 mA VOC – ±20.0 mA IIcont –25 25 mA Input clamp current, per pin (VIN < VSS – 0.3 V) Output clamp current, per pin 2, 3 4 Contiguous pin DC injection current—regional limit sum of 16 contiguous pins Output Voltage Range (normal push-pull mode) VOUT Pin Group 1,2 –0.3 4.0 V Output Voltage Range (open drain mode) VOUTOD Pin Group 1 –0.3 5.5 V RESET Output Voltage Range VOUTOD_RESET Pin Group 2 –0.3 4.0 V DAC Output Voltage Range VOUT_DAC Pin Group 5 –0.3 4.0 V Ambient Temperature TA –40 85 °C Storage Temperature Range TSTG –55 150 °C 1. 2. 3. 4. Default Mode: • Pin Group 1: GPIO, TDI, TDO, TMS, TCK • Pin Group 2: RESET • Pin Group 3: ADC and Comparator Analog Inputs • Pin Group 4: XTAL, EXTAL • Pin Group 5: DAC analog output Continuous clamp current. All 5 volt tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (= VSS –0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed, then a current limiting resistor is required. I/O is configured as push-pull mode. WCT1111DS, Rev. 1.1, 09/2015 4 Freescale Semiconductor 1.2 Thermal Handling Ratings Table 2. Thermal Handling Ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free – 260 °C 2 1. 2. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD Handling Ratings Table 3. ESD Handling Ratings Characteristic 1 Min. Max. Unit ESD for Human Body Model (HBM) -2000 +2000 V ESD for Machine Model (MM) -200 +200 V ESD for Charge Device Model (CDM) -500 +500 V Latch-up current at TA= 85°C (ILAT) -100 +100 mA 1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 1.4 Moisture Handling Ratings Table 4. Moisture Handling Ratings Symbol MSL 1. Description Moisture sensitivity level Min. – Max. 3 Unit – Notes 1 Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 5 2 Electrical Characteristics 2.1 General Characteristics Table 5. General Electrical Characteristics Recommended Operating Conditions (VREFLx = 0 V, VSSA = 0 V, VSS = 0 V) Characteristic 2 Symbol Notes Min. Typ. Max. Unit Test Conditions 3.6 V - VDDA V - 0 0.1 V - 0 0.1 V - 5.5 V - VDD V - 0.35×VDD V - 2.0 VDD + 0.3 V - -0.3 0.8 V - Supply Voltage VDD ,VDDA 2.7 ADC (Cyclic) Reference VREFHA 3.0 Voltage High VREFHB Voltage difference VDD to VDDA ΔVDD -0.1 Voltage difference VSS to VSSA ΔVss -0.1 Input Voltage High (digital VIH 1 (Pin Group 1) 0.7×VDD VIH_RESET 1 (Pin Group 2) 0.7×VDD VIL 1 (Pin Group 1,2) VIHOSC 1 (Pin Group 4) Oscillator Input Voltage Low VILOSC 1 (Pin Group 4) Output Source Current High IOH 3.3 inputs) RESET Voltage High Input Voltage Low (digital - inputs) Oscillator Input Voltage High XTAL driven by an external clock source (at VOH min.) 3,4 • Programmed for low 1 (Pin Group 1) - -2 1 (Pin Group 1) - -9 1 (Pin Group 1,2) - 2 1 (Pin Group 1,2) - 9 mA drive strength • Programmed for high drive strength Output Source Current Low (at VOL max.) IOL 3,4 • Programmed for low mA - drive strength • Programmed for high drive strength Output Voltage High VOH 1 (Pin Group 1) VDD - 0.5 - - V IOH = IOHmax Output Voltage Low VOL 1 (Pin Group 1,2) - - 0.5 V IOL = IOLmax WCT1111DS, Rev. 1.1, 09/2015 6 Freescale Semiconductor Digital Input Current High IIH 1 (Pin Group 1) - 0 +/-2.5 µA pull-up enabled or disabled VIN = 2.4 V to 5.5 V VIN = 2.4 V to VDD 1 (Pin Group 2) 0 +/-2 µA VIN = VDDA - 0 +/-2 µA VIN = VDDA RPull-Up 20 - 50 kΩ - Internal Pull-Down Resistance RPull-Down 20 - 50 kΩ - Comparator Input Current IILC 1 (Pin Group 3) - 0 +/-2 µA VIN = 0V Oscillator Input Current Low IILOSC 1 (Pin Group 4) - 0 +/-2 µA VIN = 0V DAC Output Voltage Range VDAC 1 (Pin Group 5) VSSA + - VDDA - V RLD = 3 kΩ, CLD = 400 pF Comparator Input Current IIHC 1 (Pin Group 3) Oscillator Input Current High IIHOSC 1 (Pin Group 4) Internal Pull-Up Resistance High Low 0.04 1 Output Current High 0.04 IOZ 1 (Pin Group 1,2) - 0 +/-1 µA - VHYS 1 (Pin Group 1,2) 0.06×VDD - - V - Impedance State Schmitt Trigger Input Hysteresis Input capacitance CIN - 10 - pF - Output capacitance COUT - 10 - pF - GPIO pin interrupt pulse TINT_Pulse 1.5 - - Bus - width 6 5 Port rise and fall time (high clock TPort_H_DIS 7 5.5 - 15.1 ns drive strength). Slew 2.7 ≤ VDD ≤ 3.6 V disabled. Port rise and fall time (high drive strength). Slew enabled. TPort_H_EN 7 1.5 - 6.8 ns 2.7 ≤ VDD ≤ 3.6 V Port rise and fall time (low drive strength). Slew disabled. TPort_L_DIS 8 8.2 - 17.8 ns 2.7 ≤ VDD ≤ 3.6 V Port rise and fall time (low drive strength). Slew enabled. TPort_L_EN 8 3.2 - 9.2 ns 2.7 ≤ VDD ≤ 3.6 V Device (system and core) clock frequency fSYSCLK 0 - 100 MHz - Bus clock fBUS - - 50 MHz - 1. Default Mode o Pin Group 1: GPIO, TDI, TDO, TMS, TCK o Pin Group 2: RESET o Pin Group 3: ADC and Comparator Analog Inputs WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 7 2. 3. 4. 5. 6. 7. 8. o Pin Group 4: XTAL, EXTAL o Pin Group 5: DAC analog output ADC (Cyclic) specifications are not guaranteed when VDDA is below 3.0 V. Total chip source or sink current cannot exceed 75 mA. Contiguous pin DC injection current of regional limit—including sum of negative injection currents or sum of positive injection currents of 16 contiguous pins—is 25 mA. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming GPIOn_IPOLR and GPIOn_IENR. The greater synchronous and asynchronous timing must be met. 75 pF load. 15 pF load. 2.2 Device Characteristics Table 6. General Device Characteristics Power mode Transition Behavior Symbol TPOR Description Min. After a POR event, the amount of delay Max. Unit 199 225 µs Notes from when VDD reaches 2.7 V to when the first instruction executes (over the operating temperature range). TS2R STOP mode to RUN mode 6.79 7.27 µs 1 TLPS2LPR LPS mode to LPRUN mode 240.9 551 µs 2 TVLPS2VLPR VLPS mode to VLPRUN mode 1424 1459 µs 4 TW2R WAIT mode to RUN mode 0.57 0.62 µs 3 TLPW2LPR LPWAIT mode to LPRUN mode 237.2 554 µs 2 TVLPW2VLPR VLPWAIT mode to VLPRUN mode 1413 1500 µs 4 Power Consumption Operating Behaviors Typical at 3.3 V, 25 °C Mode Conditions Max. Frequency Notes IDD IDDA WCT1111DS, Rev. 1.1, 09/2015 8 Freescale Semiconductor RUN1 100 MHz core clock, 50 MHz peripheral 100 MHz 38.1 mA 9.9 mA 50 MHz 27.6 mA 9.9 mA clock, regulators are in full regulation, relaxation oscillator on, PLL powered on, continuous MAC instructions with fetches from program Flash, all peripheral modules enabled, TMRs and SCIs using 1× peripheral clock, NanoEdge within eFlexPWM using 2× peripheral clock, ADC/DAC (only one 12-bit DAC and all 6-bit DACs) powered on and clocked, comparator powered on, all ports configured as inputs with input low and no DC loads RUN2 50 MHz core and peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered on, continuous MAC instructions with fetches from program Flash, all peripheral modules enabled, TMRs and SCIs using 1× peripheral clock, NanoEdge within eFlexPWM using 2× peripheral clock, ADC/DAC (only one 12-bit DAC and all 6-bit DACs) powered on and clocked, comparator powered on, all ports configured as inputs with input low and no DC loads WAIT 50 MHz core and peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered on, core in WAIT state, all peripheral modules enabled, TMRs and SCIs using 1× clock, NanoEdge within eFlexPWM using 2× clock, ADC/DAC (one 12-bit DAC, all 6-bit DACs)/comparator powered off, all ports configured as inputs with input low and no DC loads 50 MHz 24.0 mA - STOP 4 MHz core and peripheral clock, regulators are in full regulation, relaxation oscillator on, PLL powered off, core in STOP state, all peripheral module and core clocks are off, ADC/DAC/Comparator powered off, all ports configured as inputs with input low and no DC loads 4 MHz 6.3 mA - WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 9 LPRUN 200 kHz core and peripheral clock from relaxation oscillator's low-speed clock, relaxation oscillator in standby mode, regulators are in standby, PLL disabled, repeat NOP instructions, all peripheral modules enabled, except NanoEdge within eFlexPWM and cyclic ADCs, one 12-bit DAC and all 6-bit DACs enabled, simple loop with running from platform instruction buffer, all ports configured as inputs with input low and no DC loads 2 MHz 2.8 mA 3.1 mA LPWAIT 200 kHz core and peripheral clock from relaxation oscillator's low-speed clock, relaxation oscillator in standby mode, regulators are in standby, PLL disabled, all peripheral modules enabled, except NanoEdge within eFlexPWM and cyclic ADCs, one 12-bit DAC and all 6-bit DACs enabled, core in WAIT mode, all ports configured as inputs with input low and no DC loads 2 MHz 2.7 mA 3.1 mA LPSTOP 200 kHz core and peripheral clock from relaxation oscillator's low-speed clock, relaxation oscillator in standby mode, regulators are in standby, PLL disabled, only PITs and COP enabled, other peripheral modules disabled and clocks gated off, core in STOP mode, all ports configured as inputs with input low and no DC loads 2 MHz 1.2 mA - VLPRUN 32 kHz core and peripheral clock from a 64 kHz external clock source, oscillator in power down, all relaxation oscillators disabled, large regulator is in standby, small regulator is disabled, PLL disabled, repeat NOP instructions, all peripheral modules, except COP and EWM, disabled and clocks gated off, simple loop running from platform instruction buffer, all ports configured as inputs with input low and no DC loads 200 kHz 0.7 mA - VLPWAIT 32 kHz core and peripheral clock from a 64 kHz external clock source, oscillator in power down, all relaxation oscillators disabled, large regulator is in standby, small regulator is disabled, PLL disabled, all peripheral modules, except COP, disabled and clocks gated off, core in WAIT mode, all ports configured as inputs with input low and no DC loads 200 kHz 0.7 mA - WCT1111DS, Rev. 1.1, 09/2015 10 Freescale Semiconductor VLPSTOP 32 kHz core and peripheral clock from a 64 kHz external clock source, oscillator in power down, all relaxation oscillators disabled, large regulator is in standby, small regulator is disabled, PLL disabled, all peripheral modules, except COP, disabled and clocks gated off, core in STOP mode, all ports configured as inputs with input low and no DC loads 200 kHz 0.7 mA - Reset and Interrupt Timing Symbol tRA tRDA tIF Characteristic Minimum RESET Assertion Duration RESET desertion to First Address Fetch Delay from Interrupt Assertion to Fetch of Min. Max. Unit Notes 16 - ns 5 865 × TOSC + 8 × - ns 6 570.9 ns TSYSCLK 361.3 first instruction (exiting STOP mode) PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters Symbol Characteristic 7 VPOR_A POR Assert Voltage VPOR_R POR Release Voltage VLVI_2p7 VLVI_2p2 Min. Typ. Max. Unit - 2.0 - V - 2.7 - V LVI_2p7 Threshold Voltage - 2.73 - V LVI_2p2 Threshold Voltage - 2.23 - V 8 JTAG Timing Symbol Description Min. Max. Unit fOP TCK frequency of operation DC fSYSCLK/8 MHz tPW TCK clock pulse width 50 - ns tDS TMS, TDI data set-up time 5 - ns tDH TMS, TDI data hold time 5 - ns tDV TCK low to TDO data valid - 30 ns tTS TCK low to TDO tri-state - 30 ns Notes Regulator 1.2 V Parameters Symbol VCAP Characteristic Output Voltage 9 10 Min. Typ. Max. Unit - 1.22 - V ISS Short Circuit Current - 600 - mA TRSC Short Circuit Tolerance (VCAP shorted to ground) - - 30 Mins WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 11 VREF Reference Voltage (after trim) - 1.21 - V External Clock Timing Symbol Characteristic Min. fOSC Frequency of operation (external clock driver) tPW Clock pulse width 11 - Max. 50 External clock input rise time 13 Unit MHz 8 12 trise - Typ. ns - - 1 ns tfall External clock input fall time - - 1 ns Vih Input high voltage overdrive by an external clock 0.85×VDD - - V Vil Input low voltage overdrive by an external clock - - 0.3×VDD V Phase-Locked Loop (PLL) Timing Symbol Characteristic Min. 14 fRef_PLL PLL input reference frequency 15 fOP_PLL PLL output frequency 16 tLock_PLL PLL lock time tDC_PLL Allowed Duty Cycle of input reference Typ. Max. Unit 8 8 16 MHz 200 - 400 MHz 35.5 - 73.2 µs 40 50 60 % External Crystal or Resonator Specifications Symbol fXOSC Characteristic Min. Frequency of operation 4 Typ. 8 Max. 16 Unit MHz Relaxation Oscillator Electrical Specifications Symbol Min. Typ. Max. Unit 17 fROSC_8M 8 MHz Output Frequency RUN Mode • 0 °C to 85 °C • -40 °C to 85 °C Standby Mode (IRC trimmed @ 8 MHz) • -40 °C to 85 °C fROSC_8M_Delta fROSC_200k Characteristic 17 8 MHz Frequency Variation over 25 °C RUN Mode Due to temperature • 0 °C to 85 °C • -40 °C to 85 °C 7.84 8 8.16 MHz 7.76 8 8.24 MHz - 405 - kHz - +/-1.5 +/-1.5 +/-2 +/-3 % % 194 200 206 kHz 18 200 kHz Output Frequency RUN Mode • -40 °C to 85 °C WCT1111DS, Rev. 1.1, 09/2015 12 Freescale Semiconductor fROSC_200k_Delta 17 tStab tDC_ROSC 200 kHz Output Frequency Variation over 18 25 °C RUN Mode Due to temperature • 0 °C to 85 °C • -40 °C to 85 °C - Stabilization Time 19 • 8 MHz output 20 • 200 kHz output Output Duty Cycle +/-1.5 +/-1.5 +/-2 +/-3 % % - 0.12 10 - µs µs 48 50 52 % Flash Specifications Symbol thvpgm4 Description Min. Longword Program high-voltage time 21 Typ. Max. Unit - 7.5 18 µs - 13 113 ms - 52 452 ms - - 60 µs thversscr Sector Erase high-voltage time thversall Erase All high-voltage time trd1sec1k Read 1s Section execution time (flash 22 sector) tpgmchk Program Check execution time 22 - - 45 µs trdrsrc Read Resource execution time 22 - - 30 µs tpgm4 Program Longword execution time - 65 145 µs - 14 114 ms - - 0.9 ms - - 25 µs - 65 - µs - 70 575 ms 30 µs - years - years - cycles 21 tersscr Erase Flash Sector execution time trd1all Read 1s All Blocks execution time 23 22 trdonce Read Once execution time tpgmonce Program Once execution time 23 tersall Erase All Blocks execution time tvfykey Verify Backdoor Access Key execution 22 time - - tflashret10k Data retention after up to 10 K cycles 5 50 tflashret1k nflashcyc Data retention after up to 1 K cycles Cycling endurance 25 20 24 100 24 24 10 K 50 K 12-bit Cyclic ADC Electrical Specifications Symbol VDDA VREFHX fADCCLK RADC Characteristic Supply voltage 26 Min. 3.0 27 VREFH supply voltage 28 ADC conversion clock Typ. 3.3 VDDA - 0.6 Max. Unit 3.6 V VDDA V 0.1 - 10 MHz -( VREFH - VREFL) VREFL - VREFH VREFL VREFH V V 29 Conversion range • Fully differential • Single-ended/unipolar WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 13 VADCIN 30 Input voltage range (per input) • External Reference • Internal Reference VREFL VSSA - VREFH VDDA V V tADC Conversion time - 8 - tADCCLK tADCPU ADC power-up time (from adc_pdn) - 13 - tADCCLK IADCRUN ADC RUN current (per ADC block) - 1.8 - mA IADPWRDWN ADC power down current (adc_pdn enabled) - 0.1 - µA IVREFH VREFH current (in external mode) - 190 225 µA INLADC Integral non-linearity - +/- 1.5 +/- 2.2 LSB DNLADC Differential non-linearity - +/- 0.5 +/- 0.8 LSB VOFFSET Offset • Fully differential • Single ended/Unipolar - +/- 8 +/- 12 - mV mV EGAIN Gain Error - 0.996 to 1.004 0.99 to 1.101 - ENOB Effective number of bits - 10.6 - bits 34 - - +/-3 mA - 4.8 - pF 31 31 32 32 33 IINJ Input injection current CADCI Input sampling capacitance 12-bit DAC Electrical Specifications Symbol Characteristic Min. Typ. Max. Unit tSETTLE Settling time under RLD = 3 kΩ, CLD = 400 - 1 - µs - - 11 µs - +/- 3 +/- 4 LSB +/- 0.8 +/- 0.9 LSB 35 pF tDACPU DAC power-up time (from PWRDWN release to valid DACOUT) 37 INLDAC Integral non-linearity DNLDAC Differential non-linearity - MONDAC Monotonicity (> 6 sigma monotonicity, < 3.4 ppm non-monotonicity) Guaranteed VOFFSET Offset error 37 37 37 (5% to 95% of full range) (5% to 95% of full range) 36 36 - - +/- 25 +/- 43 mV - +/- 0.5 +/- 1.5 % EGAIN Gain error VOUT Output voltage range VSSA + 0.04 - VDDA - 0.04 V SNR Signal-to-noise ratio - 85 - dB ENOB Effective number of bits - 11 - bits Comparator and 6-bit DAC Electrical Specifications Symbol VDD Description Supply voltage Min. 2.7 Typ. - Max. 3.6 Unit V WCT1111DS, Rev. 1.1, 09/2015 14 Freescale Semiconductor IDDHS Supply current, High-speed mode(EN=1, - 300 - µA - 36 - µA PMODE=1) IDDLS Supply current, Low-speed mode(EN=1, PMODE=0) VAIN Analog input voltage Vss - VDD V VAIO Analog input offset voltage - - 20 mV VH Analog comparator hysteresis • CR0[HYSTCTR]=00 • CR0[HYSTCTR]=01 • CR0[HYSTCTR]=10 • CR0[HYSTCTR]=11 - 5 13 mV - 25 48 mV - 55 105 mV - 80 148 mV 38 VCMPOh Output high VDD - 0.5 - - V VCMPOl Output low - - 0.5 V tDHS Propagation delay, high-speed - 25 50 ns - 60 200 ns mode(EN=1, PMODE=1) tDLS 39 Propagation delay, low-speed mode(EN=1, PMODE=0) 39 40 tDInit Analog comparator initialization delay - 40 - µs IDAC6b 6-bit DAC current adder (enabled) - 7 - µA RDAC6b 6-bit DAC reference inputs VDDA - VDD V INLDAC6b 6-bit DAC integral non-linearity -0.5 - 0.5 LSB DNLDAC6b 6-bit DAC differential non-linearity -0.3 - 0.3 LSB 41 41 eFlexPWM Timing Parameters Symbol fPWM Characteristic Min. PWM clock frequency 42,43 SPWMNEP NanoEdge Placement (NEP) step size tDFLT Delay for fault input activating to PWM output deactivated tPWMPU Power-up time 44 Typ. Max. Unit - 100 - MHz - 312 - ps 1 - - ns - 25 - µs Quad Timer Timing Symbol Characteristic Min. Max. Unit Notes PIN Timer input period 2Ttimer + 6 - ns 45 PINHL Timer input high/low period 1Ttimer + 3 - ns 45 POUT Timer output period 2Ttimer - 2 - ns 45 POUTHL Timer output high/low period 1Ttimer - 2 - ns 45 WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 15 QSPI Timing Min. Symbol Max. Characteristic Unit Master Slave Master Slave tC Cycle time 60 60 - - ns tELD Enable lead time - 20 - - ns tELG Enable lag time - 20 - - ns tCH Clock (SCLK) high time 28 28 - - ns tCL Clock (SCLK) low time 28 28 - - ns tDS Data set-up time required for inputs 20 1 - - ns tDH Data hold time required for inputs 1 3 - - ns tA Access time (time to data active from high-impedance state) 5 - ns tD Disable time (hold time to high-impedance state) 5 - ns tDV Data valid for outputs - - tDI Data invalid 0 0 - - ns tR Rise time - - 1 1 ns tF Fall time - - 1 1 ns ns QSCI Timing Symbol Characteristic Min. Max. Unit BRSCI Baud rate - (fMAX_SCI /16) Mbit/s PW RXD RXD pulse width 0.965/BRSCI 1.04/BRSCI ns PW TXD TXD pulse width 0.965/BRSCI 1.04/BRSCI ns Notes 46 CAN Timing Symbol Characteristic Min. Max. Unit BRCAN Baud rate - 1 Mbit/s TWAKEUP CAN Wakeup dominant pulse filtered - 1.5 µs TWAKEUP CAN Wakeup dominant pulse pass 5 - µs Notes IIC Timing Min. Symbol Max. Characteristic Unit Min. Max. Min. Notes Max. fSCL SCL clock frequency 0 100 0 400 kHz tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 - 0.6 - µs tSCL_LOW LOW period of the SCL clock 4.7 - 1.3 - µs tSCL_HIGH HIGH period of the SCL clock 4 - 0.6 - µs WCT1111DS, Rev. 1.1, 09/2015 16 Freescale Semiconductor tSU_STA Set-up time for a repeated START condition 4.7 tHD_DAT Data hold time for IIC bus devices 0 - 47 tSU_DAT Data set-up time 250 tr Rise time of SDA and SCL signals tf 3.45 50 0.6 48 0 49 - 100 - 1000 Fall time of SDA and SCL signals - tSU_STOP Set-up time for STOP condition tBUS_Free tSP 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 0.9 51 µs 47 µs - ns 48 20 + 0.1Cb 300 ns 52 300 20 + 0.1Cb 300 ns 51 4 - 0.6 - µs Bus free time between STOP and START condition 4.7 - 1.3 - µs Pulse width of spikes that must be suppressed by the input filter N/A N/A 0 50 ns CPU clock = 4 MHz and System running from 8 MHz IRC Applicable to all wakeup times: Wakeup times (in 1,2,3,4) are measured from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from respective stop/wait mode. CPU clock = 200 kHz and 8 MHz IRC on standby. Exit via interrupt on Port C GPIO. Clock configuration: CPU and system clocks= 100 MHz; Bus Clock = 50 MHz. Exit via an interrupt on PortC GPIO. Using 64 KHz external clock; CPU Clock = 32 KHz. Exit via an interrupt on PortC GPIO. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion must be greater than 21 ns. TOSC means oscillator clock cycle; TSYSCLK means system clock cycle. During 3.3 V VDD power supply ramp down. During 3.3 V VDD power supply ramp up (gated by LVI_2p7). Value is after trim. Guaranteed by design. The chip may not function if the high or low pulse width is smaller than 6.25 ns. External clock input rise time is measured from 10% to 90%. External clock input fall time is measured from 90% to 10%. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8 MHz input. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must be set to 400 MHz. This is the time required after the PLL is enabled to ensure reliable operation. Frequency after application of 8 MHz trimmed. Frequency after application of 200 kHz trimmed. Standby to run mode transition. Power down to run mode transition. Maximum time based on expectations at cycling end-of-life. Assumes 25 MHz flash clock frequency. Maximum times for erase parameters based on expectations at cycling end-of-life. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 25. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 26. The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed. 27. When the input is at the VREFL level, the resulting output is all zeros (hex 000), plus any error contribution due to offset and gain error. When the input is at the VREFH level the output is all ones (hex FFF), minus any error contribution due to offset and gain error. 28. ADC clock duty cycle is 45% ~ 55%. 29. Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively. 30. In unipolar mode, positive input must be ensured to be always greater than negative input. 31. INLADC/DNLADC is measured from VADCIN = VREFL to VADCIN = VREFH using Histogram method at x1 gain setting. 32. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain setting. 33. Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk). 34. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the ADC. 35. Settling time is swing range from VSSA to VDDA. WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 17 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. LSB = 0.806 mV. No guaranteed specification within 5% of VDDA or VSSA. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD-0.7 V. Signal swing is 100 mV. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 1 LSB = Vreference/64. Reference IPbus clock of 100 MHz in NanoEdge Placement mode. Temperature and voltage variations do not affect NanoEdge Placement step size. Powerdown to NanoEdge mode transition. Ttimer = Timer input clock cycle. For 100 MHz operation, Ttimer = 10 ns. fMAX_SCI is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock or 2x bus clock for the device. The master mode IIC deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. The maximum tHD_DAT must be met only if the device does not stretch the LOW period (tSCL_LOW) of the SCL signal. Input signal Slew = 10 ns and Output Load = 50 pF Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 51. A Fast mode IIC bus device can be used in a Standard mode IIC bus system, but the requirement tSU_DAT ≥ 250 ns must then be met. This occurs when the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU_DAT = 1000 + 250 = 1250 ns (according to the Standard mode IIC bus specification) before the SCL line is released. 52. Cb = total capacitance of the one bus line in pF. 2.3 Thermal Operating Characteristics Table 7. General Thermal Characteristics Symbol Description Min. Max. Unit TJ Die junction temperature -40 125 °C TA Ambient temperature -40 85 °C WCT1111DS, Rev. 1.1, 09/2015 18 Freescale Semiconductor 3 Typical Performance Characteristics 3.1 System Efficiency The maximum system efficiency (receiver output power vs. transmitter input power) on Freescale WCT1111 based transmitter solutions can usually reach more than 70%. Of course, the detailed number depends on the specific solution type. For example, Freescale WCT-15W1COILTX reference solution has more than 75% system efficiency with MP Qi Receiver Simulator. Note: Power components are the main factor to determine the system efficiency, such as drivers and MOSFETs. 3.2 Standby Power The purpose of the standby mode of operation is to reduce the power consumption of a wireless power transfer system when power transfer is not required. There are two ways to enter standby mode. The first is when the transmitter does not detect the presence of a valid receiver. The second is when the receiver sends only an End Power Transfer Packet. In standby mode, the transmitter only monitors if a receiver is placed on the active charging area of the transmitter or removed from there. It is recommended that the transmitter’s power consumption in standby mode meets the relative regional regulations especially for “No-load power consumption”. In Freescale MP TX WCT-15W1COILTX reference design solution: • Transmitter power consumption in standby mode with analog PING: < 8mA (96mW with 12 V DC input) 3.3 Digital Demodulation To optimize system BOM cost, the WCT1111 solution employs digital demodulation algorithm to communicate with the receiver. This method can achieve high performance, low cost, and very simple coil signal sensing circuit with less components. 3.4 Foreign Object Detection The WCT1111 solution supports medium power FOD framework, which is based on calibrated power loss method and quality factor (Q factor) method. WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 19 4 Device Information 4.1 Functional Block Diagram This functional block diagram just shows the functional block pin assignment information of MWCT1111CLH. For the detailed pin multiplexing information, see Section 4.4 “Pin Function Description”. Figure 3. MWCT1111CLH Functional Block Diagram 4.2 Product Features Overview The following table highlights the main on-chip features of MWCT1111CLH device. Table 8. Product Features Overview Part WCT1111 Maximum Core/Bus Clock (MHz) 100/50 Maximum Fully Run Current Consumption (mA) 38.1 (VDD) + 9.9 (VDDA) On-Chip Program Flash Memory Size (KB) 64 On-Chip SRAM Memory Size (KB) 8 Memory Resource Protection Yes Inter-Peripheral Crossbar Switches with AOI Yes On-Chip Relaxation Oscillator 1 (8 MHz) + 1 (200 kHz) WCT1111DS, Rev. 1.1, 09/2015 20 Freescale Semiconductor Windowed Computer Operating Properly 1 External Watchdog Monitor 1 Cyclic Redundancy Check 1 Periodic Interrupt Timer 2 Quad Timer 1x4 12-bit Cyclic ADC Channels 2x8 PWM Channels High-Resolution 8 Standard 4 12-bit DAC 2 Analog Comparator /w 6-bit REF DAC 4 DMA Channels 4 Queued Serial Communications Interface 2 Queued Serial Peripheral Interface 2 Inter-Integrated Circuit 1 Controller Area Network (MSCAN) 1 GPIO 54 Package 64 LQFP WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 21 4.3 Pinout Diagram Figure 4. MWCT1111CLH Pinout Diagram 4.4 Pin Function Description By default, each pin is configured for its primary function (listed first). Any alternative functionality, shown in parentheses, can be programmed through GPIO module peripheral enable registers and SIM module GPIO peripheral select registers. Table 9. Pin Signal Descriptions Signal Name TCK Pin No. 1 Multiplexing Signals GPIOD2 Function Description Test Clock Input — This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-up resistor. A Schmitt-trigger input is used for noise immunity. WCT1111DS, Rev. 1.1, 09/2015 22 Freescale Semiconductor Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. RESET 2 GPIOD4 After reset, the default state is TCK. RESET — This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the reset state. A Schmitt-trigger input is used for noise immunity. The internal reset signal is de-asserted synchronous with the internal clocks after a fixed number of internal clocks. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. If RESET functionality is disabled in this mode and the chip can be reset only via POR, COP reset, or software reset. GPIOC0 3 EXTAL/CLKIN0 After reset, the default state is RESET. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. EXTAL — External Crystal Oscillator Input. This input connects the internal crystal oscillator input to an external crystal or ceramic resonator. CLKIN0 — This pin serves as an external clock input 0. GPIOC1 4 XTAL After reset, the default state is GPIOC0. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. XTAL — External Crystal Oscillator Output. This output connects the internal crystal oscillator output to an external crystal or ceramic resonator. GPIOC2 5 TXD0/XB_OUT 11/XB_IN2/CLK O0 After reset, the default state is GPIOC1. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. TXD0 — The SCI0 transmit data output or transmit/receive in single wire operation. XB_OUT11 — Crossbar module output 11. XB_IN2 — Crossbar module input 2. CLKO0 — This is a buffered clock output 0; the clock source is selected by clock out select (CLKOSEL) bits in the clock output select register (CLKOUT) of the SIM. GPIOF8 6 RXD0/XB_OUT 10/CMPD_O/P WM_2X After reset, the default state is GPIOC2. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. RXD0 — The SCI0 receive data input. XB_OUT10 — Crossbar module output 10. CMPD_O — Analog comparator D output. PWM_2X — NanoEdge eFlexPWM sub-module 2 output X or input capture X. After reset, the default state is GPIOF8. WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 23 GPIOC3 7 TA0/CMPA_O/ RXD0/CLKIN1 Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. TA0 — Quad timer module A channel 0 input/output. CMPA_O — Analog comparator A output. RXD0 — The SCI0 receive data input. CLKIN1 — This pin serves as an external clock input 1. GPIOC4 8 TA1/CMPB_O/X B_IN6/ EWM_OUT After reset, the default state is GPIOC3. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. TA1 — Quad timer module A channel 1 input/output. CMPB_O — Analog comparator B output. XB_IN6 — Crossbar module input 6. EWM_OUT — External watchdog monitor output. GPIOA7 9 ANA7&CMPD_I N3 After reset, the default state is GPIOC4. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA7&CMPD_IN3 — Analog input to channel 7 of ADCA and input 3 of analog comparator D. When used as an analog input, the signal goes to the ANA7 and CMPD_IN3. GPIOA6 10 ANA6&CMPD_I N2 After reset, the default state is GPIOA7. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA6&CMPD_IN2 — Analog input to channel 6 of ADCA and input 2 of analog comparator D. When used as an analog input, the signal goes to the ANA6 and CMPD_IN2. GPIOA5 11 ANA5&CMPD_I N1 After reset, the default state is GPIOA6. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA5&CMPD_IN1 — Analog input to channel 5 of ADCA and input 1 of analog comparator D. When used as an analog input, the signal goes to the ANA5 and CMPD_IN1. GPIOA4 12 ANA4&CMPD_I N0 After reset, the default state is GPIOA5. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA4&CMPD_IN0 — Analog input to channel 4 of ADCA and input 0 of analog comparator D. When used as an analog input, the signal goes to the ANA4 and CMPD_IN0. GPIOA0 13 ANA0&CMPA_I N3/CMPC_O After reset, the default state is GPIOA4. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA0&CMPA_IN3 — Analog input to channel 0 of ADCA and input 3 of WCT1111DS, Rev. 1.1, 09/2015 24 Freescale Semiconductor analog comparator A. When used as an analog input, the signal goes to the ANA0 and CMPA_IN3. CMPC_O — Analog comparator C output. GPIOA1 14 After reset, the default state is GPIOA0. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA1&CMPA_I N0 ANA1 and CMPA_IN0 — Analog input to channel 1 of ADCA and input 0 of analog comparator A. When used as an analog input, the signal goes to the ANA1 and CMPA_IN0. GPIOA2 15 After reset, the default state is GPIOA1. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA2&VREFH A&CMPA_IN1 ANA2&VREFHA&CMPA_IN1 — Analog input to channel 2 of ADCA and analog references high of ADCA and input 1 of analog comparator A. When used as an analog input, the signal goes to ANA2 and VREFHA and CMPA_IN1. ADC control register configures this input as ANA2 or VREFHA. GPIOA3 16 After reset, the default state is GPIOA2. Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA3&VREFLA &CMPA_IN2 ANA3&VREFLA&CMPA_IN2 — Analog input to channel 3 of ADCA and analog references low of ADCA and input 2 of analog comparator A. When used as an analog input, the signal goes to ANA3 and VREFLA and CMPA_IN2. ADC control register configures this input as ANA3 or VREFLA. GPIOB7 17 After reset, the default state is GPIOA3. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB7&CMPB_I N2 ANB7&CMPB_IN2 — Analog input to channel 7 of ADCB and input 2 of analog comparator B. When used as an analog input, the signal goes to the ANB7 and CMPB_IN2. GPIOC5 18 DACA_O/XB_IN 7 After reset, the default state is GPIOB7. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. DACA_O — 12-bit Digital-to-Analog Converter A output. XB_IN7 — Crossbar module input 7. GPIOB6 19 ANB6&CMPB_I N1 After reset, the default state is GPIOC5. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB6&CMPB_IN1 — Analog input to channel 6 of ADCB and input 1 of analog comparator B. When used as an analog input, the signal goes to the ANB6 and CMPB_IN1. GPIOB5 20 ANB5&CMPC_I N2 After reset, the default state is GPIOB6. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB5&CMPC_IN2 — Analog input to channel 5 of ADCB and input 2 of WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 25 analog comparator C. When used as an analog input, the signal goes to the ANB5 and CMPC_IN2. GPIOB4 21 ANB4&CMPC_I N1 After reset, the default state is GPIOB5. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB4&CMPC_IN1 — Analog input to channel 4 of ADCB and input 1 of analog comparator C. When used as an analog input, the signal goes to the ANB4 and CMPC_IN1. VDDA 22 - VSSA 23 - GPIOB0 24 ANB0&CMPB_I N3 After reset, the default state is GPIOB4. Analog Power — This pin supplies 3.3 V power to the analog modules. It must be connected to a clean analog power supply. Analog Ground — This pin supplies an analog ground to the analog modules. It must be connected to a clean power supply. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB0&CMPB_IN3 — Analog input to channel 0 of ADCB and input 3 of analog comparator B. When used as an analog input, the signal goes to ANB0 and CMPB_IN3. GPIOB1 25 ANB1&CMPB_I N0/DACB_O After reset, the default state is GPIOB0. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB1&CMPB_IN0 — Analog input to channel 1 of ADCB and input 0 of analog comparator B. When used as an analog input, the signal goes to ANB1 and CMPB_IN0. DACB_O — 12-bit Digital-to-Analog Converter B output. VCAP1 26 - GPIOB2 27 ANB2&VREFH B&CMPC_IN3 After reset, the default state is GPIOB1. Connect a 2.2 μF or greater bypass capacitor between this pin and VSS to stabilize the core voltage regulator output required for proper device operation. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB2&VREFHB&CMPC_IN3 — Analog input to channel 2 of ADCB and analog references high of ADCB and input 3 of analog comparator C. When used as an analog input, the signal goes to ANB2 and VREFHB and CMPC_IN3. ADC control register configures this input as ANB2 or VREFHB. GPIOB3 28 ANB3&VREFLB &CMPC_IN0 After reset, the default state is GPIOB2. Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB3&VREFLB&CMPC_IN0 — Analog input to channel 3 of ADCB and analog references low of ADCB and input 0 of analog comparator C. When used as an analog input, the signal goes to ANB3 and VREFLB and CMPC_IN0. ADC control register configures this input as ANB3 or VREFLB. VDD1 VSS1 GPIOC6 29 30 31 TA2/XB_IN3/C MP_REF/SS0 After reset, the default state is GPIOB3. I/O Power — Supplies 3.3 V power to on-chip digital module. I/O Ground — Provides ground on-chip digital module. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. WCT1111DS, Rev. 1.1, 09/2015 26 Freescale Semiconductor TA2 — Quad timer module A channel 2 input/output. XB_IN3 — Crossbar module input 3. CMP_REF — Input 5 of analog comparator A and B and C and D. SS0 — SS0 is used in slave mode to indicate to the SPI0 module that the current transfer is to be received. GPIOC7 32 SS0/TXD0/XB_I N8 After reset, the default state is GPIOC6. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. SS0 — SS0 is used in slave mode to indicate to the SPI0 module that the current transfer is to be received. TXD0 — SCI0 transmit data output or transmit/receive in single wire operation. XB_IN8 — Crossbar module input 8. GPIOC8 33 MISO0 /RXD0/XB_IN9/ XB_OUT6 After reset, the default state is GPIOC7. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. MISO0 — Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO0 line of a slave device is placed in the high-impedance state if the slave device is not selected. RXD0 — SCI0 receive data input. XB_IN9 — Crossbar module input 9. XB_OUT6 — Crossbar module output 6. GPIOC9 34 SCLK0/XB_IN4/ TXD0/XB_OUT 8 After reset, the default state is GPIOC8. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. SCLK0 — The SPI0 serial clock. In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. XB_IN4 — Crossbar module input 4. TXD0 — SCI0 transmit data output or transmit/receive in single wire operation. XB_OUT8 — Crossbar module output 8. GPIOC10 35 MOSI0 /XB_IN5/MISO0 /XB_OUT9 After reset, the default state is GPIOC9. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. MOSI0 — Master out/slave in. In master mode, this pin serves as the data output. In slave mode, this pin serves as the data input. XB_IN5 — Crossbar module input 5. WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 27 MISO0 — Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO0 line of a slave device is placed in the high-impedance state if the slave device is not selected. XB_OUT9 — Crossbar module output 9. GPIOF0 36 XB_IN6/SCLK1 After reset, the default state is GPIOC10. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. XB_IN6 — Crossbar module input 6. SCLK1 — The SPI1 serial clock. In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. GPIOC11 37 CAN_TX/SCL0/ TXD1 After reset, the default state is GPIOF0. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. CANTX — CAN transmit data output. SCL0 — IIC0 serial clock. TXD1 — SCI1 transmit data output or transmit/receive in single wire operation. GPIOC12 38 CAN_RX/SDA0/ RXD1 After reset, the default state is GPIOC11. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. CANRX — CAN receive data input. SDA0 — IIC0 serial data line. RXD1 — SCI1 receive data input. GPIOF2 39 SCL0/XB_OUT 6/MISO1 After reset, the default state is GPIOC12. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. SCL0 — IIC0 serial clock. XB_OUT6 — Crossbar module output 6. MISO1 — Master in/slave out. In master mode, this pin serves as the data input. In slave mode, this pin serves as the data output. The MISO1 line of a slave device is placed in the high-impedance state if the slave device is not selected. GPIOF3 40 SDA0/XB_OUT 7/ MOSI1 After reset, the default state is GPIOF2. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. SDA0 — IIC0 serial data line. XB_OUT7 — Crossbar module output 7. MOSI1 — Master out/slave in. In master mode, this pin serves as the data output. In slave mode, this pin serves as the data input. WCT1111DS, Rev. 1.1, 09/2015 28 Freescale Semiconductor GPIOF4 41 TXD1/XB_OUT 8/PWM_0X/PW M_FAULT6 After reset, the default state is GPIOF3. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. TXD1 — The SCI1 transmit data output or transmit/receive in single wire operation. XB_OUT8 — Crossbar module output 8. PWM_0X — NanoEdge eFlexPWM sub-module 0 output X or input capture X. PWM_FAULT6 — NanoEdge eFlexPWM fault input 6. GPIOF5 42 RXD1/XB_OUT 9/PWM_1X/PW M_FAULT7 After reset, the default state is GPIOF4. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. RXD1 — The SCI1 receive data input. XB_OUT9 — Crossbar module output 9. PWM_1X — NanoEdge eFlexPWM sub-module 1 output X or input capture X. PWM_FAULT7 — NanoEdge eFlexPWM fault input 7. VSS2 VDD2 GPIOE0 43 44 45 PWM_0B After reset, the default state is GPIOF5. I/O Ground — Provides ground to on-chip digital module. I/O Power — Supplies 3.3 V power to on-chip digital module. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_0B — NanoEdge eFlexPWM sub-module 0 output B or input capture B. GPIOE1 46 PWM_0A After reset, the default state is GPIOE0. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_0A — NanoEdge eFlexPWM sub-module 0 output A or input capture A. GPIOE2 47 PWM_1B After reset, the default state is GPIOE1. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_1B — NanoEdge eFlexPWM sub-module 1 output B or input capture B. GPIOE3 48 PWM_1A After reset, the default state is GPIOE2. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_1A — NanoEdge eFlexPWM sub-module 1 output A or input capture A. GPIOC13 49 TA3/XB_IN6/ After reset, the default state is GPIOE3. Port C GPIO — This GPIO pin can be individually programmed as an input WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 29 EWM_OUT or output pin. TA3 — Quad timer module A channel 3 input/output. XB_IN6 — Crossbar module input 6. EWM_OUT — External watchdog monitor output. GPIOF1 50 CLKO1/XB_IN7/ CMPD_O After reset, the default state is GPIOC13. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. CLKO1 — This is a buffered clock output 1; the clock source is selected by clock out select (CLKOSEL) bits in the clock output select register (CLKOUT) of the SIM. XB_IN7 — Crossbar module input 7. CMPD_O — Analog comparator D output. GPIOE4 51 PWM_2B/XB_I N2 After reset, the default state is GPIOF1. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_2B — NanoEdge eFlexPWM sub-module 2 output B or input capture B. XB_IN2 — Crossbar module input 2. GPIOE5 52 PWM_2A/XB_I N3 After reset, the default state is GPIOE4. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_2A — NanoEdge eFlexPWM sub-module 2 output A or input capture A. XB_IN3 — Crossbar module input 3. GPIOE6 53 PWM_3B/XB_I N4 After reset, the default state is GPIOE5. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_3B — NanoEdge eFlexPWM sub-module 3 output B or input capture B. XB_IN4 — Crossbar module input 4. GPIOE7 54 PWM_3A/XB_I N5 After reset, the default state is GPIOE6. Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_3A — NanoEdge eFlexPWM sub-module 3 output A or input capture A. XB_IN5 — Crossbar module input 5. GPIOC14 55 SDA0/XB_OUT 4/PWM_FAULT 4 After reset, the default state is GPIOE7. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. WCT1111DS, Rev. 1.1, 09/2015 30 Freescale Semiconductor SDA0 — IIC0 serial data line. XB_OUT4 — Crossbar module output 4. PWM_FAULT4 — NanoEdge eFlexPWM fault input 4. GPIOC15 56 SCL0/XB_OUT 5/PWM_FAULT 5 After reset, the default state is GPIOC14. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. SCL0 — IIC0 serial clock. XB_OUT5 — Crossbar module output 5. PWM_FAULT5 — NanoEdge eFlexPWM fault input 5. VCAP2 57 - GPIOF6 58 PWM_3X/XB_I N2 After reset, the default state is GPIOC15. Connect a 2.2 μF or greater bypass capacitor between this pin and VSS to stabilize the core voltage regulator output required for proper device operation. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM_3X — NanoEdge eFlexPWM sub-module 3 output X or input capture X. XB_IN2 — Crossbar module input 2. GPIOF7 59 CMPC_O/SS1/X B_IN3 After reset, the default state is GPIOF6. Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. CMPC_O— Analog comparator C output. SS1 — SS1 is used in slave mode to indicate to the SPI1 module that the current transfer is to be received. XB_IN3 — Crossbar module input 3. VDD3 VSS3 TDO 60 61 62 GPIOD1 After reset, the default state is GPIOF7. I/O Power — Supplies 3.3 V power to on-chip digital module. I/O Ground — Provides ground to on-chip digital module. Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. TMS 63 GPIOD3 After reset, the default state is TDO. Test Mode Select Input — This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TMS. NOTE: Always tie the TMS pin to VDD through a 2.2 kΩ resistor if need to WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 31 TDI 64 keep on-board debug capability. Otherwise, directly tie to VDD. Test Data Input — This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. GPIOD0 Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is TDI. 4.5 Ordering Information Table 10 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office to determine availability and to order this device. Table 10 MWCT1111CLH Ordering Information Device MWCT1111CLH Supply Voltage 3.0 to 3.6V Package Type LQFP Pin Count 64 Ambient Temp. -40 to +85℃ Order Number MWCT1111CLH 4.6 Package Outline Drawing To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number of 98ASS23234W. WCT1111DS, Rev. 1.1, 09/2015 32 Freescale Semiconductor 5 Software Library WCT1111 does not only run the core wireless charging function, but also allows the user to add user application functions. Freescale provides Medium Power Wireless Charging Transmitter (WCT) software libraries (WCT1012 TX library) for different solutions designed with WCT1111. In the library, low level drivers of HAL (Hardware Abstract Layer), callback functions for library access are open to the user. For the software API and library details, see WCT1012 TX Library User’s Guide in the WCT-15W1COILTX reference design platform. 5.1 Memory Map WCT1111 has large on-chip Flash memory and RAM for user design. Besides for wireless charging transmitter library code, the user can develop private functions and link them to the library through predefined APIs. Table 11. WCT1111 Memory Footprint Part WCT1111 Memory Total Size Example Code Size Library Size FreeMASTER Size Free Size Flash 64 Kbytes 40.8 Kbyte 26.8 Kbytes 1.5 Kbytes 23.2 Kbytes RAM 8 Kbytes 4.67 Kbyte 3.4 Kbytes 0.1 Kbytes 3.33 Kbytes 5.2 Software Library and API Description For more detailed information about the WCT software library and API definition, see the WCT1012 TX Library User’s Guide in the WCT-15W1COILTX reference design platform. WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 33 6 Design Considerations 6.1 Electrical Design Considerations Use the following list of considerations to assure correct operation of the device and system: • The minimum bypass requirement is to place 0.01 - 0.1μF capacitors positioned as near as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerances. • Bypass the VDD and VSS with approximately 10μF, plus the number of 0.1μF ceramic capacitors. • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. • Take special care to minimize noise levels on the VDDA, and VSSA pins. • Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite bead in serial with VDDA trace. • If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the range of 4.7 kΩ – 10 kΩ; and the capacitor value should be in the range of 0.1 μF – 4.7 μF. • Add a 2.2 kΩ external pull-up on the TMS pin of the JTAG port to keep device in a restate during normal operation if JTAG converter is not present. • During reset and after reset but before I/O initialization, all I/O pins are at input mode with internal weak pull-up. • To eliminate PCB trace impedance effect, each ADC input should have a no less than 33 pF/10 Ω RC filter. • To assure chip reliable operation, reserve enough margins for chip electrical design. The figure 6 shows the relationship between electrical ratings and electrical operating characteristics for correct chip operation. WCT1111DS, Rev. 1.1, 09/2015 34 Freescale Semiconductor ) ) ax. in. s (m ) in. l ica ctr Ele Fatal range Expected permanent failure in rat in rat Degraded operating range - No permanent failure - Possible decreased life l ica ctr Ele e act har gc m g( s (m ic rist ope Normal operating range - No permanent failure - Correct operation l ica ctr Ele e act har gc in rat ic rist Degraded operating range - No permanent failure - Possible decreased life x.) ma g( ope l ica ctr Ele in rat Fatal range Expected permanent failure - Possible incorrect operation - Possible incorrect operation −∞ +∞ Operating (power on) ing n.) mi g( in rat ing ndl ndl Ha x.) ma g( in rat Ha Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure −∞ Handling (power off) +∞ Figure 6. Relationship between Ratings and Operating Characteristics 6.2 PCB Layout Considerations • Provide a low-impedance path from the board power supply to each VDD pin on the device and from the board ground to each VSS pin. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS pins are as short as possible. • PCB trace lengths should be minimal for high-frequency signals. • Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces. • The decoupling capacitors of 0.1μF must be placed on the VDD pins as close as possible, and place those ceramic capacitors on the same PCB layer with WCT1111 device. VIA is not recommend between the VDD pins and decoupling capacitors. • The WCT1111 bottom EP pad should be soldered to the ground plane, which makes the system more stable, and VIA matrix method can be used to connect this pad to the ground plane. • As the Wireless Charging system functions as a switching-mode power supply, the power components layout is very important to the whole system power transfer efficiency and EMI performance. The power routing loop should be as small and short as possible, especially for the resonant network. The traces of this circuit should be short and wide, and the current loop should be optimized smaller for the MOSFETs, resonant capacitor and primary coil. Another important thing is that the control circuit and power circuit should be separated. WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 35 6.3 Thermal Design Considerations WCT1111 power consumption is not so critical, so there is not additional part needed for power dissipation. However, the power inverter needs an additional PCB Cu copper to dissipate the heat, so good thermal package MOSFET is recommended to select, such as DFN package, and for the resonant capacitor, COG material, and 1206 package is recommended to meet the thermal requirement. The worst thermal case is on the inverter, so the user should make some special actions to dissipate the heat for good transmitter system thermal performance. WCT1111DS, Rev. 1.1, 09/2015 36 Freescale Semiconductor 7 Links • freescale.com • freescale.com\wirelesscharging • www.wirelesspowerconsortium.com WCT1111DS, Rev. 1.1, 09/2015 Freescale Semiconductor 37 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ©2015 Freescale Semiconductor, Inc. Document Number: WCT1111DS Rev. 1.1 09/2015