INTEGRATED CIRCUITS DATA SHEET UAA3535HL Low power GSM/DCS/PCS multi-band transceiver Objective specification File under Integrated Circuits, IC17 2000 Feb 17 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver FEATURES UAA3535HL The second section is the IF section, which further amplifies the chosen channel and performs gain control to adjust the output level to the desired value. The IF gain can be varied over more than 64 dB gain range. • Multi-band application for GSM, DCS and PCS cellular phone systems • Low noise and wide dynamic range low IF receiver The transmitter also consists of two sections. The first is a high precision I/Q modulator which converts the baseband modulation up to the transmit IF. The second is a modulation loop architecture which converts the signal to RF. • More than 35 dB on-chip image rejection in receive mode • More than 64 dB gain control range in receive mode • Integrated channel filter • Integrated TX low-pass filter The Local Oscillator (LO) signals are provided by an on-chip Voltage Controlled Oscillator (VCO) for operation of the IF section and are provided externally for operation of the RF section. The frequencies of the RF and IF VCOs are set by internal PLL circuits, which are programmable via a 3-wire serial bus. Comparison frequencies are 200 kHz (100 kHz step programmability) and 13 MHz for the RF and IF PLL respectively, and are derived from a 13 MHz reference signal which has to be supplied externally. The quadrature-phase RF LO signals required for I/Q mixers in reception are generated internally. The quadrature LO signals required for operation of the I/Q modulator are generated inside the IF VCO. • High precision I/Q modulator • Multi-band TX modulation loop architecture including offset mixer and phase-frequency detector • Dual PLL with on-chip fully integrated IF VCO • Fully differential design minimizing crosstalk and spurious signals • Functional down to 2.4 V and up to 3.6 V • 3-wire serial bus interface • LQFP48 package. The circuit can be powered-up into one of three different modes: RX, TX or SYN mode, depending on the logic state of pins RXON, TXON and SYNON, respectively. It is also possible to set the IC in one of these modes by software, using the 3-wire bus serial programming. In RX (TX) mode, all sections required for receive (transmit) are turned on. The SYN mode is used to power-up the synthesizers prior to the RX or TX mode. In the SYN mode, some internal LO buffers are also powered-up in such a way that VCO pulling is minimized when switching on the receiver or the transmitter. Additional band selection is done using the 3-wire bus serial programming, allowing the required enabling of the Low Noise Amplifiers (LNAs) and charge pumps current programming. APPLICATIONS • GSM 900 MHz, DCS 1800 MHz and PCS 1900 MHz hand-held transceivers. GENERAL DESCRIPTION The UAA3535HL is intended for Global Systems for Mobile communication (GSM), Digital Cellular communication Systems (DCS) and Personal Communication Services (PCS). The circuit integrates the receiver and most of the transmitter section of hand-held transceivers for these applications. The receiver consists of two sections. The first section is the RF receiver front-end, which amplifies the GSM, DCS or PCS aerial signal, then converts the chosen channel down to a low Intermediate Frequency (IF) of 100 kHz, and also provides more than 35 dB image suppression. Some selectivity is provided at this stage by an on-chip low-pass filter and channel selectivity is provided by a high performance integrated band-pass filter. ORDERING INFORMATION TYPE NUMBER UAA3535HL 2000 Feb 17 PACKAGE NAME DESCRIPTION VERSION LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2 2 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver UAA3535HL BLOCK DIAGRAM handbook, full pagewidth RFGND1 GSMIA GSMIB RFGND2 VCC(RF) DCSPCSIA DCSPCSIB RFLOGND VCC(RFLO) RFLOIA RFLOIB RFCPO RFCPGND VCC(RFCP) RFGND3 TXRFI VCC(TXCP) TXCPO TXCPGND RFGND4 EXTRES 38 39 7 × 40 8 36 35 34 33 41 37 QUAD 42 9 × 43 10 29 32 1 : 1/2 30 31 24 MAIN DIVIDER REFERENCE DIVIDER 26 44 2 1 POWER ENABLE PHASE-FREQUENCY DETECTOR AND CHARGE PUMP 23 45 3-WIRE BUS CONTROL REGISTER × 11 12 25 22 1 : 1/2 3 5 14 15 PHASE-FREQUENCY DETECTOR AND CHARGE PUMP 20 PHASE-FREQUENCY DETECTOR AND CHARGE PUMP 1 : 6/7 21 × 19 4 48 13 1 : 1/2 46 16 17 18 UAA3535HL 6 × 47 91 MHz GSM/DCS 78 MHz PCS 28 27 FCA074 Fig.1 Block diagram. 2000 Feb 17 3 IA IB IFCIA IFCIB IFCQA IFCQB QA QB DATA CLK E RXON TXON SYNON REFIN TXIFA TSTO VCC2(IF) IFGND2 IFCPO IFCPGND VCC(IFCP) IFGND1 IFTUNE VCC1(IF) SYNGND VCC(SYN) Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver PINNING SYMBOL TXCPO SYMBOL PIN 1 DESCRIPTION VCC(RFCP) PIN 26 UAA3535HL DESCRIPTION RF charge pump supply voltage transmit modulation loop GSM charge pump output VCC(SYN) 27 synthesizers supply voltage SYNGND 28 synthesizers ground RFLOGND 29 RF LO ground RFLOIA 30 RF LO input A RFLOIB 31 RF LO input B VCC(RFLO) 32 RF LO supply voltage IFCQB 33 RX IF Q test pin B IFCQA 34 RX IF Q test pin A IFCIB 35 RX IF I test pin B IFCIA 36 RX IF I test pin A VCC(RF) 37 RF front-end and transmit modulation loop supply voltage RFGND1 38 RF front-end and transmit modulation loop ground 1 VCC(TXCP) 2 transmit modulation loop charge pump supply voltage TXIFA 3 transmit IF test pin IFGND1 4 IF ground 1 TSTO 5 test mode output VCC1(IF) 6 IF supply voltage 1 IA 7 I path A baseband input/output IB 8 I path B baseband input/output QA 9 Q path A baseband input/output QB 10 Q path B baseband input/output RXON 11 RX mode control input TXON 12 TX mode control input IFTUNE 13 transmit IF VCO tune input GSMIA 39 receiver GSM RF input A VCC2(IF) 14 IF supply voltage 2 GSMIB 40 receiver GSM RF input B IFGND2 15 IF ground 2 RFGND2 41 DATA 16 3-wire bus data input RF front-end and transmit modulation loop ground 2 CLK 17 3-wire bus clock input DCSPCSIA 42 receiver DCS/PCS RF input A E 18 3-wire bus enable control input (active LOW) DCSPCSIB 43 receiver DCS/PCS RF input B RFGND3 44 RF front-end and transmit modulation loop ground 3 VCC(IFCP) 19 transmit IF charge pump supply voltage TXRFI 45 input from RF transmit VCOs IFCPO 20 transmit IF charge pump output RFGND4 46 IFCPGND 21 transmit IF charge pump ground RF front-end and transmit modulation loop ground 4 REFIN 22 synthesizers reference input EXTRES 47 RFCPGND 23 RF charge pump ground reference resistor for transmit modulation loop RFCPO 24 RF charge pump output TXCPGND 48 SYNON 25 SYN mode control input transmit modulation loop charge pump ground 2000 Feb 17 4 Philips Semiconductors Objective specification UAA3535HL 37 VCC(RF) 38 RFGND1 39 GSMIA 40 GSMIB 41 RFGND2 42 DCSPCSIA 43 DCSPCSIB 44 RFGND3 45 TXRFI 46 RFGND4 handbook, full pagewidth 47 EXTRES 48 TXCPGND Low power GSM/DCS/PCS multi-band transceiver 1 36 IFCIA VCC(TXCP) 2 35 IFCIB TXCPO TXIFA 3 34 IFCQA IFGND1 4 33 IFCQB 32 VCC(RFLO) TSTO 5 VCC1(IF) 6 31 RFLOIB UAA3535HL IA 7 30 RFLOIA IB 8 29 RFLOGND QA 9 28 SYNGND QB 10 27 VCC(SYN) RFCPO 24 RFCPGND 23 REFIN 22 IFCPGND 21 IFCPO 20 E 18 VCC(IFCP) 19 CLK 17 DATA 16 25 SYNON IFGND2 15 TXON 12 IFTUNE 13 26 VCC(RFCP) VCC2(IF) 14 RXON 11 FCA068 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION Channel filter and AGC RF receiver The front-end IF I and Q outputs are first applied to an amplifier circuit with provision for three 8 dB gain step adjustment possibilities and then to an integrated band-pass channel filter. The filter is a fifth-order band-pass filter centred around 100 with 220 kHz bandwidth. After filtering the IF I and Q signals are further amplified with provision for eleven 4 dB gain steps and DC offset compensation. The receiver front-end converts the aerial RF signal from EGSM (Extended GSM; 925 to 960 MHz), DCS (1805 to 1880 MHz) or PCS (1930 to 1990 MHz) bands down to an IF signal of 100 kHz. The first stages are symmetrical LNAs that are matched to 50 Ω using external baluns. The LNAs are followed by an I/Q down-mixer. The I/Q down-mixer consists of two mixers in parallel but driven by quadrature out of phase LO signals. The In-phase (I) and Quadrature- phase (Q) IF signals are then low-pass filtered to provide protection from high frequency offset interferers. The IF I and Q signals are then fed into the channel filter. 2000 Feb 17 I/Q modulator I and Q baseband signals are applied to the I/Q modulator where the modulation spectrum is shifted up to the transmit IF frequency. For low harmonic distortion, low carrier leakage and high image rejection, the phase error must be kept as small as possible. The IF output of the modulator is fed to an integrated low-pass filter where unwanted spurious signals are suppressed, prior to being fed to the phase detector. 5 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver Transmit modulation loop The ‘main’ path consists of a programmable divider chain that divides the RF and IF LO signals down to frequencies of 200 kHz (100 kHz step programmability) and 13 MHz respectively. Their phase is then compared in a digital Phase-Frequency Detector (PFD) with that of a reference signal derived from an external 13 or 26 MHz clock signal. The phase error information is fed back to the VCO via the charge pump circuit that ‘sinks’ into or ‘sources’ current from the loop filter capacitor, thereby changing the VCO frequency so that the loop becomes ‘phase locked’. The analog transmit modulation loop consists of an on-chip offset mixer, a phase-frequency detector, an off-chip loop filter and a transmit VCO. The analog PLL copies the modulation to the off-chip transmit VCO and acts as a tracking filter. A PLL of at least third-order is required to meet noise requirements at 20 MHz offset from the carrier. The PLL bandwidth must be greater than 600 kHz in order to keep a low dynamic phase error and to minimize the acquisition time. Operating modes RF and IF LO sections BASIC OPERATING MODES The RF LO input covering the 1788 to 2002 MHz bandwidth is connected to an external RF VCO module. The RF LO section includes the LO buffering for the RF PLL, a divider-by-2 or 1 for GSM and DCS/PCS respectively which drives a quadrature generation network for use in the RX I/Q down-mixer or the transmit modulation loop offset mixer. The IF LO section consists of a fully integrated IF VCO which internally provides the I/Q modulator with the necessary quadrature signals. The circuit can be powered-up into different operating modes depending on the voltage level applied at pins RXON, TXON and SYNON (hardware control). This defines the three main modes; RX, TX and SYN. Table 1 describes the different operating modes as defined by hardware control. The operation mode status depends on the control bits SYNON, RXON and TXON (see Table 1). When the receiver is on, it is possible to switch-off the low noise amplifier to perform DC offset compensation in the receiver (see Section “LNA power control”). Dual PLL A high performance dual PLL is included on-chip which enables the frequencies of the RF VCO to be synthesized off-chip and that of the IF VCO on-chip. Very low close-in phase noise is achieved which allows the PLL loop bandwidth to be widened to achieve a shorter settling time. The charge pump circuit has very low leakage current, in the nA range, so that the spurious signals are hardly detectable. Table 1 UAA3535HL When in TX mode, it is possible to enable the IF synthesizer and VCO independently from the rest of the TX section via bit TXIFON via the control bus. Basic operating mode control CONTROL PIN LEVEL POWER STATUS MODE SYNON RXON TXON SYNTHESIZER RECEIVER TRANSMITTER SYN HIGH LOW LOW on off off RX HIGH HIGH LOW on on off TX HIGH LOW HIGH on off on Idle LOW LOW LOW off off off 2000 Feb 17 6 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver UAA3535HL IF SYNTHESIZER AND VCO CONTROL SIDEBAND SELECTION CONTROL The IF synthesizer is only necessary in transmit mode. The TX IF VCO and synthesizer section can be powered-up with the control bit TXIFON; see Table 2. If TXIFON is not used, the IF VCO and synthesizer section will be enabled with the signal TXON. The receiver includes an image rejection front-end which allows the use of a RF LO 100 kHz below the RF input frequency (infradyne) or 100 kHz above the RF input frequency (supradyne). Between these two states the proper image should be selected for rejection. The selection of these 2 modes is accomplished by the control bit SBD; see Table 5. Table 2 IF synthesizer and VCO power control BIT TXIFON IF SYNTHESIZER AND VCO MODE 0 off BIT SBD 1 on 0 supradyne 1 infradyne Table 5 Sideband selection control SIDEBAND MODE LNA POWER CONTROL TX CHARGE PUMP CURRENT CONTROL When the receiver is on, it is possible to switch-off the low noise amplifier separately. Separate control of the low noise amplifier is accomplished by the control bit LNA; see Table 3. Table 3 The transmit modulation loop includes a transmit charge pump where sink and source currents are determined by an external resistor. When determined, this nominal current can be divided-by-1 or 2 to cope with different transmit VCO gains. The selection of these 2 modes is accomplished by the control bit TXI; see Table 6. LNA power control BIT LNA LNA MODE 0 off 1 on Table 6 BIT TXI BAND SELECTION CONTROL The receiver includes two RF front-end and RF LO sections; one for GSM where the RF LO is divided-by-2 and fed to the 925 to 960 MHz front-end, and the other one for DCS and/or PCS where the RF LO is not divided and fed to the 1805 to 1990 MHz front-end. The selection of these 2 modes is accomplished by the control bit BND; see Table 4. Table 4 2000 Feb 17 TX CHARGE PUMP CURRENT MODE 0 nominal current 1 nominal current divided-by-2 REFERENCE DIVIDER CONTROL The reference divider can be programmed to divide the external reference frequency by 65 or 130. The selection of these 2 modes is accomplished by the control bit REFDIV; see Table 7. Band selection control BIT BND TX charge pump current control Table 7 Reference divider control BIT REFDIV BAND MODE REFERENCE DIVIDER MODE 0 GSM 0 divide-by-65 1 DCS and/or PCS 1 divide-by-130 7 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver IF DIVIDER CONTROL Programming The IF divider can be programmed to divide the integrated IF VCO frequency by 1 or 2. The selection of these 2 modes is accomplished by the control bit IFDIV; see Table 8. SERIAL PROGRAMMING BUS UAA3535HL The transmit section integrates two switchable low-pass filters, one for a 45.5 MHz IF and the other one for 91 MHz IF. The selection of these 2 modes is accomplished by the control bit FILT; see Table 9. A simple 3-wire unidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLK and E (enable). The data sent to the device is loaded in bursts framed by E. Programming clock edges are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns inactive HIGH. This is allowed when CLK is in either state without causing any consequences to the register data. Only the last 17 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programming data even during power-down of both synthesizers. Table 9 DATA FORMAT Table 8 IF divider control BIT IFDIV IF DIVIDER MODE 0 IF = fVCO 1 IF = fVCO divided by 2 TXIF FILTER CONTROL TXIF filter control The IF synthesizer divider can be programmed to divide the semi-integrated IF VCO frequency by 6 or 7. The selection of these 2 modes is accomplished by the control bit IFO; see Table 10. Data is entered with the most significant bit first. The leading bits make up the data field, while the trailing 4 bits are an address field. The address bits are decoded on the rising edge of E. This produces an internal load pulse to store the data in the addressed latch. To ensure that data is correctly loaded on first power-up, E should be held LOW and only taken High after having programmed an appropriate register. To avoid erroneous divider ratios, the pulse is inhibited during the period when data is read by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer. Table 10 IF synthesizer divider control The allocation of the register bits is given in Table 11. BIT FILT TXIF FILTER MODE 0 IF 45.5 MHz 1 IF 91 MHz IF SYNTHESIZER DIVIDER CONTROL BIT IFO IF SYNTHESIZER DIVIDER MODE 0 divide-by-6 1 divide-by-7 REGISTER PRESET CONDITIONS The UAA3535HL programming registers have a preset state. The preset values can be found in Table 12. Conditions for guaranteed preset values at power-on are as follows: • DATA, CLOCK, E, SYNON, RXON and TXON must be at 0 V • Preset value is guaranteed 2 ms after VCC(SYN) rises to 90% of 2.6 V • E should stay at 0 V up to the end of the first programming word. 2000 Feb 17 8 ADDRESS FIELD DATA FIELD BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X RF 14 RF 13 RF 12 RF 11 RF 10 RF 9 RF 8 RF 7 RF 6 RF 5 RF 4 RF 3 RF 2 RF 1 RF 0 0 0 1 1 X X X X X 0 0 0 0 0 LNA G5 G4 G3 G2 G1 G0 0 0 1 0 X X X 0 FILT REF DIV IFO IF DIV TXI SBD BND 1 1 TXIF ON SYN ON RX ON TX ON 0 0 0 1 0 0 0 0 for test purpose only; bit usage to be defined; this is a forbidden address LAST 4 BITS Notes 1. The 15-bit RF divider is programmable through the 15 bits RF0 to RF14, in steps of 100 kHz. 2. X = don’t care. 3. The 6-bit AGC attenuator is programmable through the 6 bits G0 to G5 in 17 steps of 4 dB (see Table 13). 9 Table 12 Preset values; note 1 REGISTER ALLOCATION ADDRESS FIELD DATA FIELD BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X 1 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 1 X X X X X 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 X X X 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 for test purpose only; bit usage to be defined; this is a forbidden address Objective specification 1. X = don’t care. UAA3535HL Note LAST 4 BITS Philips Semiconductors REGISTER ALLOCATION Low power GSM/DCS/PCS multi-band transceiver 2000 Feb 17 Table 11 Register bit allocation; notes 1 and 2 and 3 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver UAA3535HL Table 13 AGC gain look-up table; note 1 G5(2) G4(2) G3 G2 G1 G0 ATTENUATION (dB)(3) 1 1 1 1 1 1 0 1 1 1 1 1 0 4 1 0 1 1 1 1 8 1 0 1 1 1 0 12 0 1 1 1 1 1 16 0 1 1 1 1 0 20 0 1 1 1 0 1 24 0 1 1 1 0 0 28 0 1 0 1 1 1 32 0 1 0 1 1 0 36 0 0 0 1 1 1 40 0 0 0 1 1 0 44 0 0 0 1 0 1 48 0 0 0 1 0 0 52 0 0 0 0 1 1 56 0 0 0 0 1 0 60 0 0 0 0 0 1 64 0 0 0 0 0 0 68 Notes 1. Codes not included in the table are forbidden. 2. Steps at the input of the band-pass filter. 3. The figure represents the total attenuation in the receive path, with respect to the maximum gain. 2000 Feb 17 10 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver UAA3535HL LIMITING VALUES SYMBOL DESCRIPTION MIN. MAX. UNIT VCC supply voltage −0.3 +3.6 V VCC(TXCP); VCC(RFCP) supply voltage for RX and TX charge pumps −0.3 +4.25 V Pmax maximum power dissipation − 1 W Tamb ambient temperature −30 +70 °C Tstg storage temperature −40 +150 °C THERMAL CHARACTERISTICS SYMBOL Rth(j-c) PARAMETER VALUE UNIT 65 K/W thermal resistance from junction to case DC CHARACTERISTICS VCC = VCC(TXCP) = VCC(RFCP) = 2.6 V; Tamb = 25 °C; unless otherwise specified. SYMBOL ICC PARAMETER supply current VCC(RF) RF front-end and transmit modulation loop supply voltage ICC(RF) RF front-end and transmit modulation loop supply current VCC1(IF) IF supply voltage 1 ICC1(IF) IF supply current 1 VCC2(IF) IF supply voltage 2 ICC2(IF) IF supply current 2 2000 Feb 17 CONDITIONS MIN. TYP. MAX. UNIT normal mode; total power-down; note 1 − 10 50 µA preset mode; total power-down; note 2 − 100 200 µA RX and SYN mode − 51.5 60 mA TX, TXIF and SYN mode − 54 66 mA SYN mode − 17 20 mA TXIF and SYN mode − 29 37 mA 2.4 − 3.3 V RX mode; one LNA and quadrature mixer active − 17 − mA RX mode; one LNA active − 6 − mA TX mode; transmit modulation loop active without charge pump − 6 − mA 2.4 − 3.3 V RX mode; I/Q low IF band-pass filter active − 7 − mA TX mode; I/Q modulator active − 9 − mA 2.4 − 3.3 V RX mode; I/Q AGC active − 4 − mA TXIF mode; TX IF VCO active − 9 − mA 11 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver SYMBOL PARAMETER VCC(RFLO) RF LO supply voltage ICC(RFLO) RF LO supply current VCC(SYN) synthesizers supply voltage ICC(SYN) synthesizers supply current VCC(IFCP) transmit IF charge pump supply voltage ICC(IFCP) transmit IF charge pump supply current VCC(TXCP) transmit modulation loop charge pump supply voltage ICC(TXCP) transmit modulation loop charge pump supply current VCC(RFCP) RF charge pump supply voltage ICC(RFCP) RF charge pump supply current UAA3535HL CONDITIONS MIN. TYP. MAX. UNIT − 3.3 V RX and SYN mode; RF LO buffer − and divider section active 10 − mA TX and SYN mode; RF LO buffer − and divider section active 10 − mA 6 − mA 2.4 SYN mode; RF LO buffer active − 2.4 − 3.3 V SYN mode; RF synthesizer active − 9.5 − mA TXIF mode; IF synthesizer active − 0.5 − mA 2.4 − 3.3 V − 1.5 − mA 2.4 − 4.25 V − 1.0 − mA 2.4 − 4.25 V SYN mode; RF LO charge pump active; in lock − 4.5 − mA TXIF mode; IF LO charge pump active; in lock TX mode; TX RF charge pump active; in lock; external resistance is 1800 Ω Baseband section: pins IA, IB, QA and QB VI(CM) common mode input-output voltage I V IA + V IB V I = ----------------------2 1.15 1.25 1.35 V VQ(CM) common mode input-output voltage Q V QA + V QB V Q = --------------------------2 1.15 1.25 1.35 V Logic input levels: pins DATA, CLK, E, TXON, RXON and SYNON VIH HIGH-level input voltage 0.9 − − V VIL LOW-level input voltage − − 0.3 V Notes 1. VCC(TXCP) = VCC(RFCP) = 4.2 V; pins TXON, RXON and SYNON are HIGH impedance; pins DATA, CLK and E are HIGH impedance. 2. VCC(TXCP) = VCC(RFCP) = 4.2 V; pins TXON, RXON and SYNON are LOW; pins DATA, CLK and E are HIGH. 2000 Feb 17 12 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver UAA3535HL AC CHARACTERISTICS VCC = VCC(CP) = 2.6 V; Tamb = −30 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT RF receiver section; measured in a 50 Ω impedance system, including external input baluns and matching networks to 50 Ω PINS: GSMIA AND GSMIB fi(RF) RF input frequency 925 − 960 MHz Ri(dif) differential input resistance parallel RC input model − 75 − Ω Ci(dif) differential input capacitance parallel RC input model − 1.5 − pF F noise figure for Ri; maximum AGC; notes 1 and 2 − 3.5 4 dB αoff LNA off-state attenuation bit LNA = 0; note 1 − 45 − dB Poff LNA off-state power handling bit LNA = 0; notes 1 and 3 3 − − dBm DES3i input referred 3 dB desensitization dBm ∆f = 3 MHz; Tamb = 25 °C; note 1 −25 − − PINS: DCSPCSIA AND DCSPCSIB fi(RF) RF input frequency 1805 − 1990 MHz Ri(dif) differential input resistance parallel RC input model − 120 − Ω Ci(dif) differential input capacitance parallel RC input model − 1.0 − pF F noise figure for Ri; maximum AGC; notes 1 and 2 − 4 4.5 dB αoff LNA off-state attenuation bit LNA = 0; note 1 − 45 − dB Poff LNA off-state power handling bit LNA = 0; notes 1 and 3 6 − − dBm DES3i input referred 3 dB desensitization −28 − − dBm ∆f = 3 MHz; Tamb = 25 °C; note 1 PINS: GSMIA, GSMIB, DCSPCSIA AND DCSPCSIB s11 input reflection coefficient note 2 − −15 −10 dB SPURP(RFin) power level of spurious signals at RF input 900 to 1000 MHz band − − −57 dBm 1800 to 2000 MHz band − − −47 dBm out of preceding bands − − −45 dBm CP1 1 dB input compression point minimum AGC; Tamb = 25 °C; note 1 −25 − − dBm IP3i input referred third-order intercept maximum AGC; Tamb = 25 °C; note 1 −18 − − dBm IP2i input referred second-order intercept maximum AGC; note 4 − 30 − dBm DES3i input referred 3 dB desensitization ∆f = 3 MHz; Tamb = 25 °C; note 1 −23 − − dBm IR image rejection fIF = 200 kHz; Tamb = 25 °C; note 1 35 38 − dB ∆Gv(RF) gain mismatch GSM and DCS paths note 5 − − 2 dB 2000 Feb 17 13 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver SYMBOL PARAMETER CONDITIONS UAA3535HL MIN. TYP. MAX. UNIT PINS IA, IB, QA AND QB (RX MODE) Gv(min) minimum voltage conversion gain gain set to minimum; notes 1 and 5 19 25 31 dB Gv(max) maximum voltage conversion gain set to maximum; gain notes 1 and 5 89 93 97 dB Gv(step) voltage conversion gain step note 5 − 4 − dB ∆Gv(I/Q) gain mismatch I and Q paths note 5 − − 0.5 dB ∆Φ quadrature-phase error I and Q paths peak error − − 5 deg LEAGC gain control linearity over full gain range; note 2 −2 − +2 dB Vo(peak) maximum output voltage per pin Io(peak) maximum output current per pin Voffset output offset voltage HP−3dB −3 dB high-pass corner frequency BIF(−3dB) −3 dB IF filter bandwidth ∆td(g) group delay variation α5(IF) IF filter attenuation (fifth-order) over any 20 dB gain range −0.5 − +0.5 dB 3% T.H.D.; RL = 100 kΩ per pin 0.75 − − V 25 50 − µA −300 − +300 mV 4 6 8 kHz 100 kHz centre frequency 220 − 250 kHz 30 kHz < fo < 170 kHz − 1.5 2 µs fo = 100 kHz ± 200 kHz 17 31 − dB fo = 100 kHz ± 400 kHz 54 64 − dB fo = 100 kHz ± 600 kHz 73 82 − dB under static conditions Transmit IF section (initial conditions: Vmod(peak) = 0.5 V; fmod = 67.7 kHz; unless otherwise specified) PINS IA, IB, QA AND QB (TX MODE) fmod modulation frequency 3 dB low-pass cut-off frequency 1 − − MHz Vmod(peak) modulation level single-ended; peak value − 0.5 0.55 V Ri(D) dynamic input resistance single-ended − 25 − kΩ IF LO oscillator (measured and guaranteed on demonstration board at Tamb = 25 °C) fIFLO range of possible operation with programming 78 − 91 MHz KVCO VCO gain Vtune from 0.6 V to VCC − 0.6 V − 30 − MHz/V Vtune tuning voltage referenced to VCC(IFCP) 0.4 − VCC − 0.4 V ∆fVCC frequency variation with respect to the supply voltage pushing − − 1 MHz/V ∆fTRON frequency variation pulling −5 − +5 kHz 880 − 1910 MHz Transmit modulation loop section OFFSET MIXER; PIN TXRFI fRF 2000 Feb 17 RF input frequency 14 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver SYMBOL PARAMETER CONDITIONS UAA3535HL MIN. TYP. MAX. UNIT Ri input resistance single-ended − 50 − Ω Ci input capacitance single-ended − − − pF Pi input power −23 −20 −17 dBm s11 input reflection coefficient − −10 − dB F noise figure Tamb = 25 °C − 10 − dB CP1 1 dB input compression point Tamb = 25 °C − −20 − dBm SPURP(RFin) power level of spurious signals at RF input LO leakage − −50 −45 dBm other − − −45 dBm GSM mode; external resistance of 1800 Ω 1% for minimum output current; TXI = 0; note 6 1 2 4 mA DCS and PCS mode; external resistance of 1800 Ω 1% for minimum output current; TXI = 1; note 6 0.5 1 2 mA PHASE DETECTOR; PIN TXCPO ICP(max) charge pump maximum sink or source current KΦ phase-frequency detector gain for ICP = 1 mA − 0.16 − mA/rad ∆KΦ phase-frequency detector gain variation over output voltage range − − 10 % Vo output voltage 0.4 − VCC(CP) − 0.4 V Ro output resistance V CC(PHD) V o = ---------------------2 − 10 − kΩ Ro(pd) output resistance power down TX mode disabled − 1 − kΩ LOo local oscillator feedthrough note 7 − −40 −32 dBc IM3o third-order products level offset +3 × 67.7 kHz or −3 × 67.7 kHz; note 7 − −55 −50 dBc IMo image level fIFLO − 67.7 kHz; note 7 − −45 −37 dBc ΦNOISE phase noise output power density ∆f = 400 kHz; Tamb = 25 °C; note 7 − − −117 dBc/Hz ∆f = 1.8 MHz; Tamb = 25 °C; note 7 − − −117 dBc/Hz ∆f = 20 MHz; Tamb = 25 °C − − −136 dBc/Hz SPURL(4fm) level of spurious signals at 4 × fmod fmod = 67.7 kHz; notes 7 and 8 − − −50 dBc SPURL(8fm) level of spurious signals at 8 × fmod fmod = 67.7 kHz; note 7 − − −55 dBc 1788 − 2002 MHz RF LO buffer RF SOURCE CONNECTED AT PIN RFLOIA AND RFLOIB fi(RF) 2000 Feb 17 RF input frequency 15 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver SYMBOL PARAMETER CONDITIONS UAA3535HL MIN. TYP. MAX. UNIT Ri(dif) differential input resistance parallel RC input model − 50 − Ω Ci(dif) differential input capacitance parallel RC input model − 0.2 − pF s11 input reflection coefficient − −15 −10 dB PLO power available from the LO source −8 −5 −2 dBm REFDIV = 0 − 13 − MHz REFDIV = 1 − 26 − MHz 60 − 220 mV − 10 − kΩ 1700 − 2100 MHz RF and IF synthesizers REFERENCE INPUT; PIN REFIN fref reference frequency Vi(rms) input voltage level (RMS value) Ri input resistance fref = 13 MHz RF SYNTHESIZER; PIN RFCPO fRFLO synthesizer frequency fcomp(RF) comparison frequency − 200 − kHz fcomp(leak) 200 kHz comparison frequency leakage with recommended loop filter − −50 − dBc fstep(RF) frequency step programmability fcomp(RF) = 200 kHz − 100 − kHz Φnoise close-in phase noise ∆f = 2 kHz − −80 −76 dBc/Hz SPURP(RF) power level of spurious signals f > 400 kHz − − −70 dBc ICP(nom) nominal charge pump output current sink or source 1.7 2.0 2.3 mA KΦ phase-frequency detector gain ICP = 2 mA − 0.32 − mA/rad ∆KΦ phase-frequency detector gain variation over VCP range − − 10 % IL(CP) charge pump leakage current in off state −5 − +5 nA VCP charge pump output voltage ICP within specified range 0.4 − VCC − 0.4 V Ro output resistance SYN mode disabled; power-down − 1 − kΩ 2000 Feb 17 16 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver SYMBOL PARAMETER CONDITIONS UAA3535HL MIN. TYP. MAX. UNIT IF SYNTHESIZER; PINS IFTUNE AND IFCPO fIFLO synthesizer frequency 70 − 100 MHz fcomp(IF) comparison frequency − 13 − MHz Φnoise close-in phase noise − − −117 dBc/Hz SPURP(IF) power level of spurious signals − − −70 dBc ICP charge pump output current sink or source 0.85 1.0 1.15 mA KΦ phase-frequency detector gain for ICP = 1 mA − 0.16 − mA/rad ∆KΦ phase-frequency detector gain variation over VCP range − − 10 % IL charge pump leakage current off state −5 − +5 nA VCP charge pump output voltage 0.4 − VCC − 0.4 V Ro output resistance TXIFON and TXON mode disabled; power-down − 1 − kΩ ∆f = 400 kHz DIVIDERS RATIOS D/DRF(main) RF main divider ratio ratio between RFLOI frequency and fcomp(RF) 8940 − 10 010 D/DIF(main) IF main divider ratio ratio between IF VCO frequency and fcomp(IF) 6 − 7 REFDIV = 0 − 65 − REFDIV = 1 − 130 − REFDIV = 0 − 1 − REFDIV = 1 − 2 − 90% of the final current − − 200 D/DRF(REFDIV) RF reference divider ratio D/DIF(REFDIV) IF reference divider ratio General tON turn-on time µs Notes 1. Measured and guaranteed only on OM 5178 demonstration board. 2. This value includes printed-circuit board and balun losses. 3. The power level of the spurious signals in this measurement is less than specified under SPURP(RFin). 4. IP2i related to an IM2 measurement in low gain mode. 5. Voltage gain defined as the differential baseband RMS output voltage (either at pins IA and IB or pins QA and QB measured in standard load) divided by the RMS input voltage at the RF baluns. 6. This range is obtained through variation of the external reference resistor. 7. Measured at external transmit VCO output. 8. This is based on an adjustment in such a way, that a difference of 36 dBc is obtained in the level of the wanted signal at the frequency fIF + fmod and the level of the signal at the frequency 3fIF − fmod, measured at the input of the phase-frequency comparator for IF frequencies of 45.5 and 91 MHz. 2000 Feb 17 17 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver UAA3535HL SERIAL TIMING CHARACTERISTICS Initial parameter values: VCC = 2.6 V ±5%; Tamb = −30 to +70 °C; unless otherwise specified; see Fig.3. SYMBOL PARAMETER MIN. TYP. MAX. UNIT Serial programming clock: pin CLK tr rise time − 10 20 ns tf fall time − 10 20 ns Tcy clock cycle time 200 − − ns Enable programming: pin E tsu(E) delay to rising clock edge 200 − − ns th(E) delay from last falling clock edge 100 − − ns tW(E) minimum inactive pulse width 4000 − − ns tsu(E) enable set-up time to next clock edge 200 − − ns Register serial input data: pin DATA tsu(D) input data to clock set-up time 50 − − ns th(D) input data to clock hold time 50 − − ns tSU;DAT handbook, full pagewidth tHD;DAT tf Tcy tEND tSU;E tr CLK DATA MSB LSB ADDRESS E tSTART MGD565 Fig.3 Timing diagram 3-wire serial bus. 2000 Feb 17 18 tW(min) This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... RFGND2 PCSRX VCC(RF) 37 BALUN RFLOGND VCC(RFLO) BALUN 36 35 34 33 QUAD 9 × 43 1 : 1/2 30 31 3-WIRE BUS CONTROL REGISTER MAIN DIVIDER GSM/DCS/PCS 24 19 RFCPGND VCC(RFCP) RFGND3 VCC(TXCP) 44 2 1 GSMTX REFERENCE DIVIDER 26 45 POWER ENABLE PHASE-FREQUENCY DETECTOR AND CHARGE PUMP 23 × PHASE-FREQUENCY DETECTOR AND CHARGE PUMP 1 : 1/2 PHASE-FREQUENCY DETECTOR AND CHARGE PUMP 1 : 6/7 TXCPGND × RFGND4 IFCQB QA TXIFA TSTO VCC2(IF) 20 IFCPO 28 27 FCA075 Fig.4 Application diagram. SYNON 13 MHz VTCXO IFGND2 IFCPGND VCC(IFCP) IFGND1 IFTUNE VCC1(IF) SYNGND VCC(SYN) Objective specification × TXON REFIN 6 91 MHz GSM/DCS 78 MHz PCS RXON 3 5 14 15 13 UAA3535HL 47 DATA CLK E 22 4 1 : 1/2 QB UAA3535HL EXTRES 11 12 25 19 48 46 16 17 18 21 DCSTX PCSTX IB IFCIA IFCIB IFCQA 10 29 32 IA 8 41 42 GSMRX 7 × 40 Philips Semiconductors BALUN Low power GSM/DCS/PCS multi-band transceiver 38 39 DCSRX APPLICATION INFORMATION handbook, full pagewidth 2000 Feb 17 RFGND1 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver UAA3535HL PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M pin 1 index θ bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 MS-026 2000 Feb 17 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 20 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver • For packages with leads on two sides and a pitch (e): SOLDERING – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 2000 Feb 17 UAA3535HL 21 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver UAA3535HL Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 2000 Feb 17 22 Philips Semiconductors Objective specification Low power GSM/DCS/PCS multi-band transceiver NOTES 2000 Feb 17 23 UAA3535HL Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403506/01/pp24 Date of release: 2000 Feb 17 Document order number: 9397 750 06172