TEMIC U3810BM

U3810BM
TELEFUNKEN Semiconductors
Multi Standard Feature Phone Integrated Circuit
Description
The U3810BM multi-standard feature phone circuit is
designed to be used with a microcontroller using a 2-wire
serial bus. It performs all speech and line interface
functions required in an electronic telephone set: the
ringing function with switching regulator and melody
generator, the DTMF dialling, the loudhearing with
antilarsen and antidistortion systems, a power supply, a
clock and a reset for the microcontroller. Transmit, receive
and loudhearing gains control / AGC range / DTMF
frequencies, pre-emphasis and level / melody generator,
and mutes are programmable through the serial bus.
Block diagramm
Loudhearing
Speech
circuit
LH
Serial bus
and
Tone ringing
DTMF
dialer
Tone
ringer
MC
with
EEPROM
93 7600 e
Figure 1
Applications
D Feature phones
D Answering machines
D Fax machines
Rev. A1: 19.01.1996
Benefits
D Complete system integration of analog signal
processing and digital control circuitry
D One IC for various PTT standards, e.g. programmable
specification via mC
D Only three low-cost transducers needed (instead of
four)
1 (31)
U3810BM
TELEFUNKEN Semiconductors
Features
D Slope of DC characteristics adjustable by an external
resistor
D Gain of transmit and receive amplifiers automatically
adjusted by line length control
D Regulation range adjustable by the serial bus
D Possibility of fixed gain (PABX)
D Sidetone balancing system adjustable with line length
or by the serial bus
D Dynamic
impedance
adjustable
by
external
components
D
D
D
D
D
Extra transmit input for handsfree and answering
machine purpose
D +6 dB possibility on receive gain
D Receive amplifier for dynamic or piezo-electric
earpieces
D Extra receive output for handsfree purpose
D High impedance microphone inputs suitable for
or
electret
D Distortion of line signal and sidetone prevented by
in
D Loudhearing anti-distortion system by automatic gain
control versus available current and voltage
D Switching regulator in ringing phase
D Input ringing detection, threshold and impedance
adjustable with external resistors
the serial bus
Transmit and receive gains adjustable by serial bus
limitation
inhibiting squelch
D Ringing programmable gain in eight steps of 4 dB using
+6 dB possibility on second stage transmit gain
dynamic
range
(anti-clipping)
D Anti-larsen system efficiency is increased when
microprocessor
Confidence level during dialling
piezo-electric
using the serial bus, or linearly adjusted, using a
potentiometer
D Ringing zero crossing information for external
Stabilized power supply for peripherals
dynamic, magnetic,
microphone
D Loudhearing gain programmable in eight steps of 4 dB,
transmission
D Melody generator, with 30 frequencies in steps of semi
tones, driven by serial bus
D Internal speed-up circuit permits a faster charge of
VDD and VCC capacitor
D DTMF dialer driven by serial bus, in particular level
and pre-emphasis adjustment
D Ability to transmit a confidence tone in speech mode
using melody generator frequencies
D Five independent mutes driven by serial bus (two in
transmission, two in reception, one for the transmit /
receive loop)
D Standard low-cost ceramic 455 kHz / clock output for
the microcontroller
D Squelch system in transmission prevents “room noise”
D Extra loudhearing input for answering machines,
are being transmitted, and improves anti-larsen
efficiency (can be inhibited).
handsfree and base station of phones cordless with
loudhearing
2 (31)
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
Block diagram
94 9329
Figure 2
Rev. A1: 19.01.1996
3 (31)
U3810BM
TAD
TELEFUNKEN Semiconductors
IOS
COS
IMPA
VRI
RPI
THA
ZCO
ESI
XCK
RESET
ISQ
CO
ANTI–
DISTORTION
SQUELCH
TAL
ANTI–
LARSEN
VDD
IAL
LVIO
VCC
C
SERIAL
BUS
VL
9
MELODY–/
DTMF–
GENERATOR
AMF
SIN0,1
M0,1,2,3,4
SAI
3
D
8
MF
4
STS
3
RECI
SAIX
NEA0,1,2
MIS
EA
VSA
IM
IR
TX0,1,2
STL
RX0,1,2,6
SO1
RECOX
SO2
RECO1
GND
RECO2
RREF
IE1
IE2
IT
TX6
EC
AGA/
SIDETONE–
BALANCING
AR0,1 AT0,1
BAL0,1,2
IAGC IBAL
CEI
RDC
AGA
MICX
signal path (analog)
MIC1
MIC2
ZAC
TO MICO TIN
TACL
94 9330
control path (digital)
Figure 3 Digital adjustment of the analog parameters by the serial bus microprocessor-interface
4 (31)
Rev. A1: 19.01.1996
Rev. A1: 19.01.1996
L1
Lineinterface
L2
VZ = 15 V
CVDD
RAL
CAL
RAGA2
RAGA1
61.9 k
CSO
CVSA
RSAI CSAI
CVCC
DSC
6
5
4
3
2
RIN
220 n
1
44
200 k
43
42
41
40
455 kHz
RECOX 31
15 SO2
CEI
18
16 GND
19
RDC
20
MIC
22
23
RTO
CTO*
CZAC2*
21
24
26
RZAC
CZAC1
25
4.7 nF
CDTMF2
EAR
LVIO
CDTMF1
RDTMF1
C
Micro
controller
CEAR
470 nF
CE
GND
RESET
ZC
RACL
CACL
RDTMF2
28
47 nF
27
RECO1 30
MICO RECO2
MIC1
ZAC
RREF AGA
17 CEI RDC
MICX
TIN TACL 29
MIC2
TO
STL 32
RECI 33
STS 34
35
36
14 SO1
13 VSA
U3810BM
11 SAI
12 SAIX
MF
VL
C 37
D
VCC
9
10
ESI RESET 39
COS
VRI
THA
7 TAD
IMPA
TAL IOS
RPI
ZCO
XCK CO
8 VDD
LVIO 38
CAD
RAD
TSC
VZ = 30 V
Pulse
D
RSTL1
C1
C2
C3
C4
C5
C6
1
CSTL1*
6
R
8
9
7
0
CSTL2*
CSTL3
CSTS1
RSTL3
CSTS3
CSTS2*
RSTS3
serial bus
Key board
Pause
5
#
RSTS1
RSTL2
RSTS2
4
RD
3
2
*
LSC
CSC
VDD
TELEFUNKEN Semiconductors
U3810BM
94 9331
Figure 4 Application for feature phone
5 (31)
U3810BM
TELEFUNKEN Semiconductors
Typical value of external components
Components
RIN
Min.
0.3 MW
Typ.
1.0 MW
Max.
1.5 MW
Components
(CZAC2
Min.
Typ.
Max.
470 pF)
CSC
0.1 mF
TSC
2N5401A
RDMTF2
330 kW
LSC
1 mH
CDTMF1
4.7 nF
DSC
SD103A
CDTMF2
220 pF
RDTMF1
RAD
100 kW
CAD
470 nF
RACL
CAL
470 nF
CEAR
RAL
CVDD
RSAI
CSAI
CVSA
CSO
CVCC
RAGA1
RAGA2
CEI
RDC
RTO
(CTO
CZAC1
RZAC
6 (31)
68 kW
470 mF
20 kW
0.1 mF
220 mF
47 mF
100 mF
100 kW
51 kW
0.47 mF
20 kW
62 W
0.33 mF)
0.47 mF
12 kW
CACL
82 kW
Earphone
Loudspeaker
240 kW
0.47 mF
6.8 MW
4.7 mF
1 kW
100 W
RSTL1
6.2 kW
(CSTL1
330 pF)
RSTS1
6.2 kW
(CSTS1
330 pF)
RSTL2
RSTS2
RSTL3
43 kW
18 kW
100 kW
RSTS3
75 kW
CSTL3
10 nF
CSTS3
10 nF
CSTS2
470 pF
CSTL2
1.2 nF
X1
CSB455E
(Murata)
Rev. A1: 19.01.1996
TELEFUNKEN Semiconductors
U3810BM
Pin description
Pin
1
Symbol
RPI
2
VRI
3
IMPA
4
COS
5
IOS
6
TAD
7
8
9
TAL
VDD
VCC
10
11
VL
SAI
12
SAIX
13
VSA
14
15
SO1
SO2
Rev. A1: 19.01.1996
Function
Ringing power information. The RC combination smooths the drive current of the
loudspeaker amplifier.
Tone-ringer supply voltage. The rectified ringing voltage is delivered to VRI and then
converted into the lower supply voltage, VSA, by the converter.
External adjustment of input ringing impedance. IMPA is adjusted with a resistance
between pin 2 and 3.
ZIN = RIN/100
Control output switching supply. COS drives the base of the external switching transistor of the converter.
Current output of switching supply. This output provides a constant current, which
supplies the external part of converter. The magnitude of the current depends on the
VRI voltage and the value of resistance RIN.
Adjustment of antidistortion time constant in loudhearing with external RC
combination.
Adjustment of antilarsen time constant in loudhearing with external RC combination.
External logic supply.
Power supply for peripherals. VCC and VDD are stabilized supply voltages buffered
with external capacitors. They are derived internally from the same voltage source, but
are separated from each other by electronic switches. VDD also supplies the digital
part of the circuit and is achieved in all three modes: speech mode, ringing mode and
operation with external supply. According to the application, peripherial modules are
connected to VDD which, in addition to speech mode, must be supplied at least in one
of the two other modes. The digital part of circuit and microprocessor must continue
operating during line breaks, as they occur during pulse dialing or during flash-signal
transmission. Since VDD in this time intervals is fed only from the buffer capacity, the
power consumption from VDD must not cause the total voltage dump. VCC supplies
no internal parts of circuit and is supplied exclusively in speech mode. External
components, which must operate only in this mode, can be connected here. The power
is drawn only from the relevant buffer capacitor in the supply intervals during pulse
dialing or flash-signal transmission.
Line voltage.
Speaker amplifier input. The signal coming from the receive part, e.g. from REC01 or
RECO2, is fed in here.
Speaker amplifier input for special application i.e. answering machine. SAIX is
selected via the serial bus. SAIX has to be selected for ringing. IF ringing, Antidistortion and Antilarsen are disabled.
Supply voltage for the loudhearing amplifier. Stabilized supply voltage buffered with
an external capacitor for the loudhearing amplifier and zero crossing detector; aditional
connection point for an external supply. In speech mode, VSA is supplied by the
analog part of the circuit. In this case, the stabilization point is adjusted to the DC line
voltage VSA= VL/1.5. In ringing mode, and VSA is supplied directly from the converter. The stabilization point is permanently set. The logic supply, VDD, is fed by a
switch from VSA. VSA=5.2V. In the case of an external supply, VSA serves as a point
for a current from a power supply. The stabilization point of VSA and supply for the
logic correspond to the operation conditions in ringing mode.
Loudspeaker output 1.
Loudspeaker output 2. Differential output of loudhearing amplifier. The loudspeaker
can also be connected asymmetrically to ground or to VSA via a capacitor at one of the
two outputs. As a result of this connection there is a bigger output power in reference
to low line currents and loudspeakers with low impedance, while the differential
connection method results in a higher power output and lower harmonic distortion with
medium or high line currents and/or loudspeaker impedances
7 (31)
U3810BM
TELEFUNKEN Semiconductors
Pin description
Pin
16
17
Symbol
GND
RREF
18
CEI
19
RDC
20
AGA
Line length adjustment. Reference voltage level for AGA. The potential at this point
defines the start threshold for the AGA and the automatic balancing in the receive part
(both can be switched off by the serial bus). The potential is normally formed between
VCC and ground using a voltage divider. When the line voltage exceeds the threshold
level, the AGA or balancing becomes effective.
21
MICX
22
23
24
MIC1
MIC2
ZAC
25
TO
26
27
28
MICO
TIN
TACL
29
30
31
32
33
34
35
RECO2
RECO1
RECOX
STL
RECI
STS
MF
36
D
Asymmetrical microphone input for special applications. The input of the first stage of
the transmit amplifier, selected by the serial bus. Anticlipping is not effective at this
input.
Inverting input of microphone amplifier.
Noninverting input of microphone amplifier.
AC impedance adjustment. Adjustment of the ac circuit impedance to the line by
changing of RZAC.
Transmit amplifier output. Transmit amplifier output modulates the current flowing
into this output (typically 4.8 mA).
Microphone amplifier output. Output MICO; open-circuit potential = 2*Vbe
Transmit and DTMF input. Input of the second transmit stage.
Adjustment of anticlipping time constant with external RC combination. Anticlipping
controls the transmitter input level to prevent clipping with high signal levels. The
dynamic range of the transmit peak limiter is controlled by an internal circuit.
Symmetrical output of receive amplifier.
Symmetrical output of receive amplifier.
Receive amplifier output for handsfree and answering machine applications.
Long line sidetone network.
Receive amplifier input. It is driven by a signal from VL.
Short line sidetone network.
Multifrequency output. Output DTMF signal and confidence tone in pulse–density
modulated form. DTMF signal and confidence tone are generated by special generators
in the digital part of the circuit. The DTMF signal consists of two weighted and
superimposed pulse-density modulated signals, while in the case of confidence tone, a
pulse–density modulated signal is superimposed on a high frequency rectangular–pulse
signal with pulse duty factor 0.5. The superimposed signals are sent out to MF for
further processing.
Data input of serial bus (see Pin 37). Serial data input from microprocessor for
programming the circuit.
8 (31)
Function
Ground.
External reference resistor. Connection for external reference resistor to generate the
reference current. All basic currents of the circuit which must satisfy certain absolute
accuracy requirements depend on this current.
Capacitor for electronic inductance. Connection for capacitor of the electronic coil.
The circuit contains a first order RC-active low-pass filter. The capacitor is connected
externally between CEI and VL.
DC characteristic slope adjustment. A voltage across resistor RDC is proportional to
the dc line voltage. This means the current flow through RDC is also proportional to
the line voltage. This current drives the supply currents drawn from VL by the most
important loads, and therefore defines the total current consumption of the circuit.
Adjustment to the slope characteristic is realized by modification of RDC resistance.
Rev. A1: 19.01.1996
TELEFUNKEN Semiconductors
U3810BM
Pin description
Pin
37
Symbol
C
Function
Clock line: 2-wire serial bus. This pin is used together with the data input (pin 36) to
transfer data from the microprocessor to the circuit. The last 8 bits, consisting of 5 data
bits and 3 address bits, are accepted by the circuit if, during the high phase at pin 37, a
positive edge on pin 36 takes place.
38
LVIO
Line voltage information output. State indicator of the line voltage, VL, and the supply
voltage, VDD. Indicates to microprocessor whether line voltage VL is present across
the circuit and the supply voltage VDD is sufficiently high. If both conditions are
fulfilled, LVIO is on high level.
39
CO
Clock output. Output 455 kHz clock pulse for the microprocessor. The 455 kHz clock
signal generated in the circuit is amplified and sent to CO. This signal is delivered to
the microprocessor as a clock signal. Various internal signals can be output to CO in
test mode.
40
RESET
41
XCK
42
ESI
Reset signal for periphery. A reset signal (active low) is generated to clear all registers
of the circuit. This can be tapped by peripheral modules, particularly by the microprocessor. This pin enables synchronous resetting of the circuit and peripheral modules.
Clock signal generator. Connector for ceramic resonator (455 kHz). The clock for the
digital part of the circuit is generated by a one-pin oscillator, the frequency of which is
determined by the ceramic resonator.
Input for external supply information. Input to indicate the operating state external
supply. In the case of VSA supplied by a power supply unit, the supply source is connected directly to ESI. ESI is connected to VSA by an external diode in forward mode.
The ESI voltage will be one forward voltage higher than the voltage on VSA. This
voltage causes the circuit to be in external supply mode.
43
ZCO
44
THA
Rev. A1: 19.01.1996
Zero crossing output in ringing phase. ZCO operates when the ringer voltage, VRI, and
the supply voltage, VSA, are sufficiently high. The output voltage ZCO changes state
each time the rectified AC signal of THA crosses the ringing detect turn–on and turn–
off thresholds, thus providing information on the frequency of the ring signal. Further
analysis of the ring frequency is be done by the microprocessor. Secondly, this pin is
used as an input for switching on the test mode. Therefore, a negative voltage of
approximately 1 V must be applied to pin 43.
Ringing detection threshold adjustment. Input amplitude and frequency identification.
The rectified ringing voltage is present at this pin. The circuit evaluates the amplitude
of the rectified voltage at THA and the supply voltage VSA (pin 13 ). If both voltages
exceed certain thresholds, the signal present at THA is converted to a rectangular–
pulse signal and is sent via pin 43 to the microprocessor. If the frequency is in the
required range, the microprocessor initiates transmission of the ringing signal. The start
threshold can be raised with a resistor connected in series to pin 44.
9 (31)
U3810BM
TELEFUNKEN Semiconductors
Absolute maximum ratings
Parameters
Symbol
VRI
IR
VL
DC calling voltage (pin 2)
DC calling current (pin 2)
Conversation line voltage (pin 10)
Conversation line current
Total power dissipation *)
Operating temperature range
Storage temperature range
Junction temperature
IL
Ptot
Tamb
Tstg
Tj
Value
35
30
15
17
150
1
– 25 to + 55
– 55 to + 150
125
Unit
V
mA
V
V pulse 20 ms
mA
W
°C
°C
°C
Symbol
RthJA
Value
70
Unit
K/W
Thermal resistance
Parameters
Junction ambient *)
Electrical characteristics
IL = 28 mA, Tamb = 25°C, f = 1 kHz, RDC = 20 kΩ, all internal registers cleared, unless otherwise specified
C1
D 455 kHz ceramic resonator: MURATA or equivalent
D Refer to the tests circuits
R1
L1
C0
94 7894 e
Figure 5
Resonance factor Qm = 3100, L1 = 6.1 mH, C1 = 21 pF, CO = 268.5 pF, R1 = 5.5 (Schematic above)
All resistances are specified at 1%, all capacitances at 2%.
Parameters
Line voltage
VDD, VCC stabilized
power supply
IDD at VDD = 3.5 V
Internal operating supply
current
Leakage current
Speed up off threshold
VSOFF
Speed up on line– current
ISON
Speed up current
Test conditions
IL = 15 mA
IL = 28 mA
IL = 60 mA
IL = 8 mA, –Idd (ICC) = 0.6 mA
IL = 28 mA, –Idd (ICC) = 2.3 mA
S4 on 3
Min.
4.2
6.7
12.8
2.5
3.2
Typ.
4.75
7.2
13.45
2.65
3.45
180
See fig. 11
2.45
See fig. 14
VL = 4 V
*) Note: Assembly on PC board
10 (31)
ILmax = 80 mA
VL = 4 V
IL decreasing
VDD = 2.8 V
w 24
Max.
5.2
7.5
14.1
Unit
Fig.
V
6
3.6
210
A
V
6
9
2.65
100
2.8
nA
V
7
5.0
5.9
7.5
mA
40
70
mA
7
cm2 assumed
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
Parameters
Transmission
Transmit gain (note 1)
on MIC1 / MIC2
Test conditions
VMIC = 3 mVrms
MIS
max. gain
0
min. gain
0
TX2
1
0
TX1
1
0
TX0
1
0
Min.
Typ.
Max.
Unit
47.0
39.8
48.0
41.0
49.0
42.2
dB
dB
VMICX = 5 mVrms
MIS TX2 TX1 TX0
on MICX
43.0
44.0
45.0
max.gain
1
1
1
1
35.8
37.0
38.2
min. gain
1
0
0
0
Gain adjustment of microGain change between two steps (both on
phone amplifier
MIC1/MIC2 and on MICX)
0.8
1.0
1.2
Transmit gain without AGC VMIC = 3 mVrms, Bit AGC=1
GT at 28 mA
TX2 TX1 TX0
0
1
1
DGT at IL = 20 to 28 mA
42.6
44.0
45.5
0
1
1
DGT at IL = 28 to 60 mA
–0.5
0.0
ă0.5
0
1
1
–0.5
0.0
ă0.5
Gain change between
VMIC = 3mVrms:
AT1 AT0
28 and 60 mA
(MIS = 0)
0
0
3.6
4.1
4.6
on MIC1 / MIC2
0
1
4.9
5.35
5.9
on MICX
or VMICX = 5 mVrms
6.3
6.9
7.4
1
0
7.7
8.2
8.7
(MIS = 1)
1
1
+6 dB delta transmit gain
IL = 28 mA and 60 mA
VMIC = 1.5 mVrms , Bit TX6 = 1
5.4
6.0
6.6
Noise at line
GT = max. gain
psophometrically weighted VMIC = 0 (MIS = 0) ISQ = 0
– 79
– 75
VMIC = 0 (MIS = 0) ISQ = 1
– 73
– 70
– 64
VMICX = 0 (MIS = 1) ISQ = 1
*Max. gain is without + 6 dB function which is especially devoted for DTMF
Muted gain
VMIC = 3 mVrms (MIS = 0) or
VMIC = 5 mVrms (MIS = 1)
(at max. and min. gain)
Bit IM = 1
65
on MIC1 / MIC2
Bit IT = 1
65
VMIC = 3 mVrms (MIS = 1) or
60
on MICX
VMIC = 5 mVrms (MIS = 0)
60
Microphone input
impedance
on MIC1/MIC 2
VMIC = 3 mVrms (MIS = 0)
70
110
on MICX
VMICX = 5 mVrms (MIS = 1)
35
55
CMRR common mode
GT = at maximum gain
65
rejection ratio
Voltage step on pin 26
IL =28 mA and 60 mA
when going from transmis- VMIC = 0 (MIS = 0) or
– 75
+75
sion to mute mode
VMICX = 0 (MIS = 1)
Bit IM from 0 to 1
At maximum gain
Dynamic limiter (anti-clipping) CACL = 470 nF, RACL = 6.8 MW operational only on MIC1/MIC2
Output voltage swing
TX2 TX1 TX0
(peak to peak value)
1
1
1
3.3
4.4
VMIC = 4 mVrms + 10 dB
Delta output voltage swing
TX2 TX1 TX0
0
0
0
–200
0
200
VMIC = 9 mVrms + 10 dB
Rev. A1: 19.01.1996
Fig.
6
dB
dB
dB
6
dB
6
dB
6
dB
6
6
dBmp
dB
dB
dB
dB
kW
kW
dB
6
6
6
mV
6
Vpp
6
mVpp
6
11 (31)
U3810BM
Parameters
Delta output voltage swing
Line distortion
(on 600 W)
TELEFUNKEN Semiconductors
Test conditions
TX2 TX1 TX0
0 0 0
IL = 60 mA
AT1 = AT0 = 1
VMIC = 22 mVrms + 10 dB
Min.
Typ.
Max.
Unit
Fig.
–200
0
200
mVpp
6
2
3
%
%
1 VMIC = 2 mVrms
VMIC = 2 mVrms+26 dB
2
3.5
%
%
IL = 60 mA
AT0 = AT1 = 1
0 VMIC = 22 mVrms
VMIC=22mVrms+24dB
3
3
%
%
10.3
0.3
dB
dB
TX6 TX2 TX1 TX0
0
0
0
0 VMIC = 9 mVrms
VMIC =9 mVrms+26 dB
1
1
0
1
0
0
Squelch function
CAL = 470 nF, RAL = 68 kW
Dynamic range attenuation (note 2)
IL = 28 mA and 60 mA
Squelch inhibition
DGT = GT1(ISQ = 1) – GT2(ISQ = 0)
(tested on GT)
GT1 (VMIC = 160 mVrms),
GT2 (VMIC = 3 mVrms)
At maximum gain
8.3
–0.3
9.3
0
6
6
6
ESI
XCK
VCC
C 37
10
VL
D 36
11
SAI
12
SAIX
MF 35
U3810M
SO2
RECOX 31
16
GND
RECO1 30
RECO2 29
TACL
4.7uF
470nF
0.1uF
6.8 M
330k
240k
220pF
47nF
12k
470nF
1k
4.7nF
22uF
20k
470nF
51k
47uF
22uF
270
100k
18 19 20 21 22 23 24 25 26 27 28
60k
6.2k
15
470nF
6.2k
STL 32
MICO
TIN
RECI 33
SO1
TO
VSA
14
RREF
CEI
60k
STS 34
13
17
serial bus
4.7nF
RPI
THA
VRI
ZCO
IMPA
IOS
VDD
9
ZAC
61.9k
455kHz
44 43 42 41 40
RESET 39
CO
LVIO 38
MIC2
VZ=17V
1
MIC1
600
IDC
VL
2
MICX
47uF
Il
3
AGA
470uF
4
8
7
RDC
470nF
6
5
TAD
TAL
COS
68k
V
62
AC VMIC
94 9332
Figure 6 Test circuit
12 (31)
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
GT
94 7895 e
D Note 1: transmit gain: GT = VL/VMIC on MIC1/MIC2
GT = VL/VMIC on MICX with the above values of
RAG1 and RAG2
D Note 2: Squelch dynamic range: DGT = GT0 – GT1
GT0 measured at VMIC = 1 mVrms
GT1 measured at VMIC = 160 mVrms
IL
12
Parameters
Receive
GR receiving gain
GR = VR*/VL
(for normal output)
DGR = VR/VRECOX
Gain adjustment at
earphone
Test conditions
Noise at earpiece
psophometric weighted
Receiving distortion
Receiver output
impedance on
RECO1/RECO2
(pins 29–30)
Receiver output
impedance on RECOX
(pin 31)
50 mA
Min.
Typ.
Max.
Unit
Fig.
3.5
– 3.7
4.5
– 2.5
5.5
– 1.3
dB
dB
7
14.0
15.0
16.0
dB
7
0.8
1.0
1.3
dB
7
–3
– 0.5
– 0.5
– 1.5
0
0
0
0.5
0.5
dB
dB
dB
7
3.6
4.9
6.3
7.5
4.1
5.5
6.9
8.3
4.6
5.9
7.4
8.7
dB
dB
dB
dB
5.6
6.1
6.7
dB
7
dB
dB
dB
7
VGEN = 0.3 Vrms
maximum gain
minimum gain
RX2
1
0
RX1
1
0
RX0
1
0
VGEN = 0.3 Vrms
IL = 28 mA and 60 mA
Attenuation between two steps
(both on REC01/REC02 and on
RECOX)
Receiving gain without
VGEN = 0.3 Vrms
Bit: AGC =1
AGC
IBAL = 1
GR = VR/VL
Bits RX2 RX1 RX0
1
1
1
GR at 28 mA
1
1
1
DGR at 20 mA < IL < 28 mA
1
1
1
DGR at 28 mA < IL < 60 mA
DGR receiving gain
VGEN = 0.3 Vrms
Bits AR1 AR0
betw. 28 and 60 mA
0
0
on RECO1/RECO2
0
1
and on RECOX
1
0
1
1
+6 dB delta receiving gain
on RECO1/RECO2
and on RECOX
Muted gain
30
VGEN = 0.3 Vrms, IL = 28mA and 60mA
(At maximum and minimum gain)
Bit RX6 = 1
VGEN = 0.3 Vrms
Mute on REC01/REC02
Bit IR=1
Bit IE1 = IE2 = 1
RECOX
Bit IR=1
65
60
36
At maximum gain
VGEN = 0 V
IL = 28 mA and 60 mA
max gain, RX6 = 1 VR = 5 Vpp
min. gain, RX6 = 0 VR = 2 Vpp
7
150
220
mVp
7
1
3
%
7
VR = 50 mVrms,
40
65
85
W
7
VRECOX = 50 mVrms
800
950
1100
W
7
* VR = VRECO1 – VRECO2
Rev. A1: 19.01.1996
13 (31)
U3810BM
Parameters
Receiver output
offset (pin 29 – 30)
Automatic sidetone
balancing (VR*/VMIC)
Digital balanced sidetone
tested on receiving gain
VR/VL
Confidence level
attenuation
Confidence level gain
VR/VMIC
Z line match. impedance
TELEFUNKEN Semiconductors
Test conditions
IL = 28 mA and 60 mA
Maximum gain RX6 = 1
At maximum gain
VMIC = 4 mVrms
IL = 28 mA
IL = 60 mA
VGEN = 0.3 Vrms maximum gain
close switch S1 Bit IBAL = 1
Bits BAL2 BAL1BAL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
Min.
– 800
Typ.
Max.
+600
Unit
mV
Fig.
7
dB
dB
6
dB
dB
dB
dB
dB
dB
dB
7
dB
6
dB
6
7
24
16
18.0
16.9
15.5
19.0
17.9
16.5
14.5
12.3
9.2
5.7
4.2
VMIC = 2 mVrms Bit IR = 1
20.0
18.9
17.5
7.2
60
VMIC = 2 mVrms IR = 1 EC = 1
VGEN = 0.3 Vrms IL = 28 and 60 mA
19.5
520
22.0
570
23.5
620
W
68k
41
455kHz
40
37
10
VL
D
36
11
SAI
MF
35
12
SAIX
STS
34
13
VSA
RECI
33
14
SO1
STL
32
15
SO2
RECOX
31
16
GND
RECO1
30
17
RREF
CEI
RECO2
TACL
29
27
28
470nF
4.7nF
6.8M
270
20k
26
6.2k
25
VE3
0.1uF
6.2k
24
60k
470nF
10k
23
S1
60k
47nF
22
MICO
TIN
TO
21
12k
ZAC
20
serial bus
4.7uF
1k
RPI
THA
IOS
19
47uF
470nF
RESET 39
CO
U3810BM
100k
18
ESI
XCK
38
C
ZCO
LVIO
VCC
VRI
VDD
9
COS
8
IMPA
TAD
TAL
VZ=17V
51k
42
4.7uF
43
MIC2
61.9k
44
MIC1
SIN
1
MICX
VGEN
2
AGA
47uF
VL
600
IDC
3
7
470uF
Il
4
RDC
470nF
5
470nF
6
62
94 9333
Figure 7 Test circuit
14 (31)
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
Parameters
Speaker amplifier
VSA shunt regulator
power supply (pin 13)
in transmission mode
Loudhearing gain (note3)
from SAI/SAIX to SO1,
SO2
Test conditions
Speaker amplifier without signal
EA = 1
IL = 28 mA
IL = 60 mA
– VSO2
+ VSO1VSAI
GSA2 + VSO1 – VSO2
VSAIX
GSA1
EA = 1
gain change between two steps
EA = 1
Bits
NEA2 NEA1 NEA0 VSAI
1
1
1
VSAI = 12 mVrms
Input impedance SAI
SAIX
Confidence gain in loudhearing
Loudhearing input
cross talk attenuation
0
0
(Note 4, 6)
Antilarsen system
Dynamic range attenuation
Rev. A1: 19.01.1996
āā
IL = 20 mA
IL = 28 mA
4.0
7.85
4.3
8.3
4.6
8.7
V
V
Fig.
8
33
5
34
6
35
7
dB
dB
– 0.5
0
0.5
dB
8
3.8
4.0
4.2
dB
8
2.0
4.0
1.5
%
%
%
8
2.0
2.0
10
10
40
%
%
āāā
VSO
EA = 1
VMIC EC = 1, ITAL = 1
NEA
=7
EA = 1
VSAI =12 mVrms
LIS = 1
VSAIX = 12 mVrms
LIS = 0
IL = 60 mA
Output offset
(pin 14 – 15)
Leakage current (pin 6)
Offset (pin 7)
āā
VMIC = 4 mV
EA =1
Unit
VSAI = 30 mVrms
VSAI = 250 mVrms
Bits EA = 1
IL = 60 mA
NEA2 NEA1 NEA0
1
1
1
VSAI = 80 mVrms
0
0
0
VSAI = 250 mVrms
EA = 1
Output power
Max.
EA = 1
EA = 1
0
Typ.
8
Bits
NEA2 NEA1 NEA0 VSAI = VSAIX
1
1
1
VSAI=3.5mVrms
0
0
0
VSAI = 88 mVrms
Loudhearing gain between
28 and 60 mA
GSA1 and GSA2 (note 3)
Gain adjustment of speaker
amplifier
Distortion (measured on
100 Ω load)
Min.
50 W load
100 W load
50 W load
100 W load
50 W load
100 W load
asym.
sym.
asym.
sym.
asym.
sym.
LIS = 0, 1
EA = 1
max. and min. gain
EA = 1
RAL = 68 kW
IL = 28 mA and 60 mA
EA = 1
CAL = 470 nF, RAL = 68 kW
(note 5)
IL = 28 mA and 60 mA
EA = 1 VSAI = 6 mVrms
Bit ISQ = 0
BIT ISQ = 1
4
4
36
7
7
60
60
9.0
19.0
140
dB
dB
12,5
11,5
24
30
120
170
– 200
11
23
kW
dB
12
26
8
8
8
mW
mW
mW
mW
mW
8
+200
mV
8
140
140
nA
mV
8
6
13
29
dB
dB
8
15 (31)
U3810BM
100k
470nF
11
SAI
MF
35
12
SAIX
STS
34
13
VSA
RECI
33
14
SO1
STL
32
15
SO2
RECOX
31
16
GND
17
RREF
CEI
TO
MICO
TIN
21
22
23
24
25
26
X
60k
470nF
60k
1k
RECO1 30
RECO2 29
TACL
47nF
27
0.1uF
4.7uF
28
470nF
6.8 M
4.7nF
12k
20
22nF
19
ZAC
U3810BM
serial bus
6.2k
ESI
XCK
ZCO
36
20k
470nF
RPI
37
D
62
D
VRI
C
VL
100k
51k
IMPA
IOS
VCC
47uF
D
RESET 39
CO
10
18
D
THA
9
COS
38
470nF
61.9k
455kHz
40
LVIO
MIC2
VZ=17V
41
22uF
VSO
47uF
42
MIC1
100
43
VDD
270
600
220uF
44
8
22uF
VL
IDC
1
MICX
470nF
2
AGA
47uF
S2
3
4
7
470uF
Il
5
6.2k
6
TAD
TAL
RDC
68k
470nF
TELEFUNKEN Semiconductors
VMIC
94 9334
Figure 8 Test circuit
Note 3: GSA1 measured with S2 on 11
The circuit conforms to the T/CS 46–02 CEPT
GSA2 measured with S2 on 12 and Bit LIS = 1
recommendation concerning DTMF option 1 (–9/–11
dBm) and option 2 (–6/–8 dBm) transmit level 5 (example:
Note 4: Antilarsen dynamic range:
in fig. 6, option 2 can be fulfilled with 3.5 dB pre–emphasis
DGLS = GLSA – GLSB
and 1.5 Vpp low frequency level pin 35).
GLSA measured at VMIC = 160 mVrms
GLSB measured at VMIC = 1 mVrms
Two different low levels (with 3 dB difference) and two
different pre–emphasis (2.5 and 3.5 dB) can be chosen
Note 5: The available output current of the speaker
through the serial bus.
amplifier can be increased by reduction of the quiescent
current of the receiver output stage ( bits IE1, IE2, see Melody – confidence tone
“contents of internal registers” ).
Melody/confidence tone frequencies are given in table 2.
DTMF dialing
The output pin MF provides the multifrequency signal to
be transmitted on line. This signal is the result of the sum
of two frequency pulse modulations and requires an
external filter to compose a dual sine wave. The
frequencies are chosen in a low group and a high group.
16 (31)
In the state SIN1 = 1, SIN0 = 0, the IC delivers a single
pulse density modulated frequency at pin MF (the same
behavior as DTMF), denoted as a confidence tone. The
confidence tone is sent either to the line or on the
earpiece.In the state SIN1 = 0, SIN0 = 1, a square wave is
sent to the loudhearing input for ringing melodies.
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
Table 1: Frequency tolerance of the output tones for DTMF signalling tone output frequency when using 455 kHz
Standard frequency
Hz
Tone output
frequency
Hz
%
Hz
Low Group
697
770
852
941
697.85
771.18
852.06
940.08
0.12
0.15
0.01
– 0.10
+0.85
+1.18
+0.06
– 0.92
High Group
1209
1336
1477
1633
1210.1
1338.2
1477.3
1636.7
0.09
0.17
0.02
0.22
+1.1
+2.2
+0.3
+3.7
Frequency deviation
Note: Frequency can be directly measured on CO when S3 is closed (figure 9)
AMF
1
0
0
0
697
770
852
941
Rev. A1: 19.01.1996
SIN0
1
1
1
0
1209
1
4
7
*
SIN1
1
1
0
1
1336
2
5
8
0
CO
DTMF : HF
DTMF : LF
MELODY
CONFIDENCE TONE
1477
3
6
9
#
1633
A
B
C
D
17 (31)
U3810BM
TELEFUNKEN Semiconductors
Standard
frequency
Hz
440
466.16
493.88
523.25
554.36
587.33
622.25
659.25
698.46
740
784
830
880
932.3
987.77
1046.5
1108.73
1174.66
1244.5
1318.5
1396.9
1480
1568
1661.2
1760
1864.65
1975.5
2093
2217.46
2349.3
Table 2:
Frequency
deviation
0/
00
0.09
0.06
– 0.78
– 0.50
0.92
0.89
– 1.07
0.26
– 0.87
1.41
0.62
– 0.37
– 1.84
0.08
1.38
1.80
0.93
– 1.69
– 1.07
– 2.63
– 0.86
– 1.84
0.62
– 0.37
2.03
0.06
1.40
– 2.79
– 3.93
– 1.68
Frequency tolerance of the output tone
Tone output frequency when using 455 kHz
Parameters
DTMF generation (specified pin MF)
Tone frequency accuracy
See table 1
Low group tone level
Note 7
without attenuation
S3 closed
High group tone level
Note 7
without attenuation
S3 closed
Pre-emphasis A
Note 7
without attenuation
S3 closed
Pre-emphasis B
Note 7
without attenuation
S3 closed
Low group tone level
Note 7
with attenuation
S3 closed
High group tone level
Note 7
with attenuation
S3 closed
18 (31)
Tone output
frequency
Hz
440.04
466.19
493.49
522.99
554.88
587.86
621.58
659.42
697.85
741.04
784.48
830.29
878.38
932.38
989.13
1048.39
1109.76
1172.68
1243.17
1315.03
1395.71
1477.27
1568.97
1660.58
1763.57
1864.75
1978.26
2087.16
2208.74
2345.36
Test conditions
Min.
Typ.
Max.
Unit
Fig.
BFOA (pre-emphasis A)
BFOB (pre-emphasis B)
HFOA (pre-emphasis A)
HFOB (pre-emphasis B)
PROA
1.35
1.25
1.80
1.90
2.04
1.50
1.40
2.00
2.10
2.54
1.65
1.55
2.20
2.35
3.04
V
V
V
V
dB
9
PROB
3.02
3.52
4.02
dB
9
BF1A (pre-emphasis A)
BF1B (pre-emphasis B)
HF1A (pre-emphasis A)
HF1B (pre-emphasis B)
0.95
0.90
1.25
1.35
1.05
1.00
1.40
1.50
1.15
1.10
1.55
1.65
V
V
V
V
9
9
9
9
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
Parameters
Pre-emphasis A
with attenuation
Pre-emphasis B
with attenuation
Leakage
Test conditions
Note 7
PR1A
S3 closed
Note 7
PR1B
S3 closed
S4 = 2
Bits
SIN1
S3 closed
0
IL = 28 mA
M = 8 Key = «3»
TX6 = 1
IM = 1
Distortion at line
Low group tone level
at line
Melody generation
Tone frequency accuracy
Confidence tone level
SIN0
0
Min.
2.04
Typ.
2.54
Max.
3.04
Unit
dB
Fig.
9
3.02
3.52
4.02
dB
9
100
nA
9
1
3
%
– 100
6
IL = 28 mA and 60 mA
M = 8 Key = «3»
TX6 = 1
IM = 1
– 10
–8
–6
dBm
see table 2
Note: 7
2.10
2.33
2.60
V
6
CTL
9
VTM
S3
42
41
ESI
XCK
VRI
43
ZCO
IMPA
44
THA
COS
1
RPI
2
40
7
TAD
TAL
8
VDD
9
VCC
C
37
VL
D
36
10
RESET
39
CO
LVIO
38
11
MF
35
SAI
12
SAIX
STS
34
13
14
VSA
RECI
33
SO1
STL
32
15
SO2
RECOX
31
16
GND
RECO1
30
17
RREF
CEI
RECO2
TACL
29
ZAC
TO
MICO
20
21
22
23
24
25
26
TIN
MIC2
19
MIC1
18
serial bus
–A +
S4
U3810BM
MICX
A–
3
AGA
+
4
RDC
3.5V
5
IOS
455 kHz
6
27
0
1
2
3
1.4V
28
94 9335
Figure 9 Test circuit
Rev. A1: 19.01.1996
19 (31)
U3810BM
S4 (Fig. 9)
0
0
0
0
0
1
1
1
1
1
AMF
0
0
0
0
1
0
0
0
0
1
Internal registers
set by serial bus
SIN1
SIN0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
TELEFUNKEN Semiconductors
Internal signal set
by clock count
FB
FH
F227
1
0
X
0
1
X
0
1
X
0
X
1
0
0
1
0
1
X
1
0
X
1
0
X
1
X
0
1
1
0
M4
0
0
1
0
X
1
0
1
X
X
I measured
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
X: either 1 or 0
Note 7: DTMF calculations
BF level without attenuation with
pre-emphasis A:
BF level without attenuation with
pre-emphasis B:
ǒ
ǒ
+ǒ )
+ǒ )
Ǔ
Ǔ
) ) Ǔ
) ) Ǔ
ǒ Ǔ
ǒ Ǔ
+ I1 )I1 I7 ) I6 )I6 I2
I1 ) I6
BFOB +
I1 ) I8 I6 ) I3
BFOA
HF level without attenuation with
pre-emphasis A:
HFOA
HF level without attenuation with
pre-emphasis B:
HFOB
Pre-emphasis A without attenuation:
PROA
I2
I2
I3
I3
I7
I6
I7
I6
I8
VDD
2
VDD
2
I1
VDD
2
I1
VDD
2
I8
BF level with attenuation with
pre-emphasis B:
+ 20 log HFOA
BFOA
PROB + 20 log HFOB
BFOB
I1
BF1A +
) I6
I1 ) I7 ) I10 I6 ) I2 ) I5
I1
BF1B +
) I6
I1 ) I8 ) I10 I6 ) I3 ) I5
HF level with attenuation
with pre-emphasis A:
HF1A
HF level with attenuation
with pre-emphasis B:
HF1B
Pre-emphasis A
without attenuation:
PR1A
+ 20 log
Pre-emphasis B
without attenuation:
PR1B
+ 20 log
Confidence tone level:
CTL
Pre-emphasis B without attenuation:
BF level with attenuation with
pre-emphasis A:
20 (31)
ǒ
ǒ
+ǒ )
+ǒ )
I2
I3
ǒ
) I10 ) I7 ) I1
I3
) I8
I6 ) I10 I8 ) I1
I7
I2
I6
ǒ Ǔ
ǒ Ǔ
Ǔ
Ǔ
) Ǔ
) Ǔ
VDD
2
VDD
2
I5
VDD
2
I5
VDD
2
HF1A
BF1A
HF1B
BF1B
+ I1 )I1 I9 ) I6 )I6 I4
Ǔ
VDD
2
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
Parameters
Ringer
THA threshold voltage
THTV
THA hysteresis DTH
VSA threshold voltage
VSAON (ring detector enabled)
VSA threshold voltage
VSAOFF (ring detector disabled)
Switching supply output
current
Input impedance VIN/IIN
Test conditions
Min.
Typ.
Max.
Unit
Fig.
S5 on 1
8.30
8.75
9.20
V
10
VS = 5 V
S5 on 1
VTHA = 12 V
S5 on 1
435
3.0
465
3.2
495
3.4
mV
V
10
10
VTHA = 12 V
2.45
2.5
2.65
V
10
33
37
mA
10
VS = 5 V
S5 on 1
VS = 5 V
VIN = 30 V
S7 on 1
S5 on 1 RIN = 300 kW
S5 on 1
VS = 5 V S7 on 1
Off state VIN = 5 V
RIN = 300 kW
On state VIN = 30 V RIN = 300 kW
On state VIN = 30 V RIN = 1500 kW
RIN = 300 kW
S7 on 2
S5 on 2 VIN = 30 V VESI = 0 V
S5 on 1 VIN = 0 V VESI = 5 V
VSA/VDD switch off VSA- S8 closed
OFF1
S5 on 1
IVDD = – 1 mA
(measured on VSA)
VSA shunt regulator
VSAL
S5 on 3
ISA = 2 mA
VSAH
ISA = 45 mA
Difference between
max. VSA voltage and
VSADIFF = VSAOFF1 – VSAH
cut off voltage
ZCO
VS = 5 V S5 on 1
S6 closed
Zero crossing information
IZCO = 100 mA
VTHA = 7.5 V
IZCO = –100 mA
VTHA = 12.0 V
Ringer output power
VIN = 30 V
RIN = 300 kW
(on 100 W load)
S7 on 2
S5 on 2
SIN1 SIN0 LIS EA
0
1
1
1
NEA – maximum gain
RPI
ringing power information
Extra ringing attenuation
Rev. A1: 19.01.1996
VIN = 30 V
RIN = 300 kW
S7 on 2
S5 on 2
SIN1 SIN0 LIS AMF EA
0
1
1
1
1
NEA – maximum gain
13.4
2.90
14.1
3.05
15.0
kW
kW
kW
1.48
1.57
1.55
1.61
1.64
1.64
V
V
10
5.55
5.8
6.0
V
10
4.75
5.0
5.0
5.3
5.15
5.7
V
V
10
250
500
mV
10
0.5
V
V
10
50.0
ă2.78
4.4
10
70
105
130
mW
10
– 12.8
– 12.2
– 11.6
dB
10
21 (31)
U3810BM
TELEFUNKEN Semiconductors
2
5V
–A +
S7
1
220uF
0.1uF
1mH
VIN
IZC
VTHA
VESI
S6
S8
470uF
43
42
ESI
41
XCK
44
ZCO
1
THA
2
VRI
TAL
3
1
2
3
100
RESET
39
CO
8
VDD
LVIO 38
9
VCC
C 37
10
VL
D 36
11
SAI
MF 35
12
SAI
13
VSA
RECI 33
14
SO1
STL 32
15
SO2
RECOX 31
16
GND
RECO1 30
17
RREF
CEI
U3810BM
STS 34
VSO
ISA
455kHz
40
serial bus
VS
S5
TAD
4
IMPA
7
5
COS
6
IOS
470nF
IVDD
RPI
RIN
100k
200k
2N5401A
SD103A
MIC1
MIC2
ZAC
TO
MICO
20
21
22
23
24
25
26
TIN
MICX
19
AGA
18
RDC
47uF
27
RECO2 29
TACL
28
94 9336
Figure 10 Test circuit
937608
22 (31)
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
Electrical characteristics of logical part
fxck = 455 kHz
VDD = 3.5 V
Parameter
Min.
INPUTS : C, D
Low-voltage input Vil
High-voltage input Vih
–1
Output: RESET, CO, LVIO
Low-voltage output (Iol = 100 mA) Vol
High-voltage output (Ioh = – 100 mA) Voh
3.1
CLOCK: CO (fig. 15)
Using reference ceramic resonator
period:
tcyc
High pulse width:
twch
2.19
1.10
RESET TIMING (figure 11, 12 and 13)
Clock start-up time
ton
Clock inhibition time
toff
Reset time (without ton)
tr
Rev. A1: 19.01.1996
Max.
Unit
0.7
V
V
1
mA
0.35
V
V
2.21
1.45
ms
ms
2.8
Input leakage current Ii
(0 < VI < VDD)
SERIAL BUS (figure 19)
Data set–up time
Data hold time
Clock low time
Clock high time
Hold time before transfer condition
Data low pulse on transfer condition
Data high pulse on transfer condition
Typ.
tsud
thd
tcl
tch
teon
teh
teoff
2.20
ms
ms
ms
ms
ms
ms
ms
0.1
0
2
2
0.1
0.2
0.2
3
70
30
31.6
5
150
32
ms
ms
ms
23 (31)
U3810BM
TELEFUNKEN Semiconductors
Power-on-reset and reset pin
The system (U3810BM + microcontroller) is woken up by
an initial condition:
– line voltage
(VL)
– ringer
(THA)
– external supply (ESI)
To avoid undefined states of the system when it is powered
on, an internal reset clears the internal registers, and
maintains pin RESET low during trt.
1.) Power on in speed-up condition (VDD < VSON)
LINE
LVIO
SHUTDOWN
VDD
CO
RESETN
937609
Figure 11
2.) Power on without speed-up (VDD > VSON)
LINE
LVIO
SHUTDOWN
VDD
CO
RESETN
937610
Figure 12
24 (31)
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
3.) Line break
LINE
LIVO
SHUTDOWN
VDD
CO
RESETN
937611
Figure 13
When the microprocessor detects LIVO low during t > tmP (internal microprocessor timing special for line breaks), it
forces high the shutdown bit through the serial bus, thus leading the IC, after toff, to go into standby mode (oscillator stop).
Pin RESET remains high.
When the line break is shorter than tmP, nothing appears.
4.) Line current fall
LINE
LIVO
SHUTDOWN
VDD
CO
937612
RESET
Figure 14
Rev. A1: 19.01.1996
25 (31)
U3810BM
TELEFUNKEN Semiconductors
CO
94 7896 e
CLOCK OUTPUT <CO>
Figure 15
Serisl bus
The circuit is remoted by an external microcontroller
through the serial bus:
The data line must be stable when the clock is high and data
must be serially shifted.
The data is an 8-bit word:
B7 – B6 – B5: address of the destination register (0 to 7)
B4 – B0: contents of register
After 8 clock periods, the transfer to the destination register
is (internally) generated by a low to high transition of the
data line when the clock is high.
DATA
D
mP
C
CLOCK
937613
Figure 16
937614
Figure 17
26 (31)
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
Serial Bus Interface
8 bits register
DATA
CLOCK
937616
Analog Commands
Figure 18
937615
Figure 19
Content of internal registers
0: Transmission mode
TX6
TX2
TX1
TX0
MIS:
TX6:
TX:
Microphone input switching
+6dB
Transmission gain adjustment
RX6
RX2
RX1
RX0
LIS:
RX6:
RX:
Loudhearing input switching
+6dB
Reception gain adjustment
MIS
1: Reception mode
LIS
Rev. A1: 19.01.1996
27 (31)
U3810BM
TELEFUNKEN Semiconductors
2: Loudhearing mode
IAL
EA
NEA2
NEA1
NEA0
AR1
AR0
AT1
AT0
IBAL
BAL2
BAL1
BAL0
IAL:
EA:
NEA:
Antilarsen inhibition
Loudhearing enable
Loudhearing gain adjustment
3: AGC mode
IAGC
IAGC: AGC inhibition
AT:
Transmission AGC adjustment
AR:
Reception AGC adjustment
4: Sidetone mode
IE2:
IE2
BAL
0
1
2
3
4
5
6
7
Reception output amplifier current
adjustment
IBAL: Inhibition of automatic sidetone
balance
Z
1
5/6
2/3
1/2
1/2
1/3
1/6
STS
STS + 1/6 STL
STS + 1/3 STL
STS + 1/2 STL
STS + 1/2 STL
STS + 2/3 STL
STS + 5/6 STL
1 STL
5: Internal inhibitions
IR
EC
IT
IE1
0
0
1
1
IE2
0
1
0
1
IREC
3 mA
2 mA
1 mA
0 mA
IM
IE1
IR:
EC:
IT:
IM:
IE1:
Reception inhibition
Confidence enable
Transmit inhibition
Microphone inhibition
Reception output amplifier current
adjustment
Earpiece inhibition
6: Melody / DTMF choice
M4
28 (31)
M3
M2
M1
M0
Rev. A1: 19.01.1996
U3810BM
TELEFUNKEN Semiconductors
DTMF mode
M
Melody or confidence tone output
A3
440.0
A#3
466.2
B3
493.5
C4
523.0
C#4
554.9
D4
587.8
D#4
621.6
E4
659.4
F4
697.8
F#4
741.0
G4
784.5
G#4
830.3
A4
878.4
A#4
932.4
B4
989.1
C5
1048.4
C#
1109.7
D5
1172.7
D#5
1243.2
E5
1315.0
F5
1395.7
F#5
1477.3
G5
1569.0
G#5
1660.6
A5
1763.6
A#5
1864.7
B5
1978.3
C6
2087.2
C#6
2208.7
D6
2345.4
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Key
HF/LF
«1»
«4»
«7»
«*»
«2»
«5»
«8»
«0»
«3»
«6»
«9»
«#»
«A»
«B»
«C»
«D»
«1»
«4»
«7»
«*»
«2»
«5»
«8»
«0»
«3»
«6»
«9»
«#»
«A»
«B»
«C»
«D»
2.5 dB
”
”
”
”
”
”
”
”
”
”
”
”
”
”
”
3.5 dB
”
”
”
”
”
”
”
”
”
”
”
”
”
”
”
Table 3
7: Control register
AMF:
ISQ
AMF
SD
SIN1
SIN0
ISQ:
SD:
SIN:
MF output attenuation –3 dB
extra ringing attenuation (12 dB)
Squelch inhibition
Shutdown
Generator mode
0: OFF
1: Melody (Ringer)
2: Confidence tone
3: DTMF
Order Information
Package
PLCC 44
SSO 44
Rev. A1: 19.01.1996
Type
U3810BM-CP
U3810BM-FN
Electrostatic sensitive device.
Observe precautions for handling.
29 (31)
U3810BM
TELEFUNKEN Semiconductors
Dimensions in mm
Package: PLCC 44
Package: SSO 44
94 8888
30 (31)
Rev. A1: 19.01.1996
TELEFUNKEN Semiconductors
U3810BM
OZONE DEPLETING SUBSTANCES POLICY STATEMENT
It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to
1. Meet all present and future national and international statutory requirements and
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on the
environment.
Of particular concern is the control or elimination of releases into the atmosphere of these substances which are known
as ozone depleting substances ( ODSs).
The Montreal Protocol ( 1987) and its London Amendments ( 1990) will severely restrict the use of ODSs and forbid their
use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous
improvements to eliminate the use of any ODSs listed in the following documents that all refer to the same substances:
(1)
Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments
respectively
(2)
Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the
Environmental Protection Agency ( EPA) in the USA and
(3)
Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances )
respectively.
TEMIC can certify that our semiconductors are not manufactured with and do not contain ozone depleting substances.
We reserve the right to make changes to improve technical design without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application,
the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or
indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.
TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 ( 0 ) 7131 67 2831, Fax Number: 49 ( 0 ) 7131 67 2423
Rev. A1: 19.01.1996
31 (31)