74LVC374A-Q100 Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Rev. 1 — 22 November 2012 Product data sheet 1. General description The 74LVC374A-Q100 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C 5 V tolerant inputs/outputs; for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels High-impedance when VCC = 0 V 8-bit positive edge-triggered register Independent register and 3-state buffer operation Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74LVC374AD-Q100 Temperature range Name Description Version 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVC374APW-Q100 40 C to +125 C 40 C to +125 C 74LVC374ABQ-Q100 DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm SOT764-1 4. Functional diagram 1 11 EN C1 11 3 4 7 8 13 14 17 18 3 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 2 4 5 6 7 6 9 8 9 12 13 12 14 15 17 16 18 19 5 15 16 19 OE 1 Fig 1. Logic symbol 74LVC374A_Q100 Product data sheet 2 1D mna196 mna891 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 2 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 13 D4 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 FF1 to FF8 3-STATE OUTPUTS Q4 12 11 CP 1 OE mna892 Fig 3. Functional diagram D0 D1 D Q D2 D CP Q D CP FF1 D3 Q D CP FF2 D4 Q D CP FF3 D5 Q D CP FF4 D6 Q D CP FF5 D7 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna893 Fig 4. Logic diagram 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 3 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 5. Pinning information 5.1 Pinning 2( WHUPLQDO LQGH[DUHD /9&$4 2( 4 9&& 4 ' 9&& /9&$4 4 4 ' ' ' ' ' 4 4 4 ' 4 4 ' 4 4 ' ' ' ' ' 4 4 4 *1' &3 ' *1' ' 4 &3 *1' ' 4 DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description 1 OE output enable input (active LOW) 11 CP clock input (LOW to HIGH, edge-triggered) D[0:7] 3, 4, 7, 8, 13, 14, 17, 18 data input Q[0:7] 2, 5, 6, 9, 12, 15, 16, 19 3-state flip-flop output 10 GND ground (0 V) 20 VCC supply voltage 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 4 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 6. Functional description Table 3. Function table[1] Operating mode Load and read register Load register and disable outputs [1] Input Internal flip-flop Output OE CP Dn Qn L l L L L h H H H l L Z H h H Z H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition Z = high-impedance OFF-state = LOW to HIGH clock transition 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions Min VI < 0 [1] Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V mA - 50 output HIGH or LOW state [2] 0.5 VCC + 0.5 V output 3-state [2] 0.5 +6.5 V - 50 mA 100 mA VO > VCC or VO < 0 IO output current ICC supply current - IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot [1] VO = 0 V to VCC Tamb = 40 C to +125 C [3] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO20 packages: above 70 C derate linearly with 8 mW/K. For TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K. 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 5 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions VI input voltage VO output voltage Min Typ Max Unit 1.65 - 3.6 V functional 1.2 - - V 0 - 5.5 V output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V 40 - +125 C Tamb ambient temperature in free air t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 1.2 V Product data sheet 40 C to +125 C Max Min Max Unit 1.08 - - 1.08 - V 0.65 VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V 0.12 V VCC = 1.65 V to 1.95 V VCC = 1.2 V - - 0.12 - VCC = 1.65 V to 1.95 V - - 0.35 VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC 0.2 - - VCC 0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A 0.35 VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V VI = VIH or VIL input leakage VCC = 3.6 V; VI = 5.5 V or GND current 74LVC374A_Q100 Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 6 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Min Typ[1] Max Min Max Unit IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND; - 0.1 5 - 20 A IOFF power-off leakage supply VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC 0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 4.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol Parameter tpd propagation delay 40 C to +85 C Conditions enable time CP to Qn; see Figure 7 VCC = 1.2 V disable time Product data sheet Min Max - 16 - - - ns VCC = 1.65 V to 1.95 V 2.2 7.4 16.3 2.2 18.8 ns 1.5 3.9 8.4 1.5 9.7 ns VCC = 2.7 V 1.5 3.5 8.0 1.5 10.0 ns 1.5 3.3 7.0 1.5 9.0 ns - 19 - - - ns VCC = 1.65 V to 1.95 V 1.5 6.6 16.7 1.5 19.3 ns VCC = 2.3 V to 2.7 V 1.5 3.7 9.3 1.5 10.8 ns VCC = 2.7 V 1.5 3.8 8.5 1.5 11.0 ns VCC = 3.0 V to 3.6 V 1.5 3.0 7.5 1.5 9.5 ns - 8.0 - - - ns [2] OE to Qn; see Figure 8 [2] OE to Qn; see Figure 8 VCC = 1.2 V 74LVC374A_Q100 Max VCC = 2.3 V to 2.7 V VCC = 1.2 V tdis Typ[1] [2] VCC = 3.0 V to 3.6 V ten 40 C to +125 C Unit Min VCC = 1.65 V to 1.95 V 2.3 4.0 10.1 2.3 11.7 ns VCC = 2.3 V to 2.7 V 1.0 2.2 5.7 1.0 6.7 ns VCC = 2.7 V 1.5 3.1 6.5 1.5 9.0 ns VCC = 3.0 V to 3.6 V 1.5 2.9 6.0 1.5 7.5 ns All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 7 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol Parameter 40 C to +85 C Conditions Min tW pulse width set-up time tsu hold time th maximum frequency fmax Typ[1] Max 40 C to +125 C Unit Min Max clock HIGH or LOW; see Figure 7 VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.0 - - 4.5 - ns VCC = 3.0 V to 3.6 V 3.0 1.5 - 4.5 - ns VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns VCC = 2.3 V to 2.7 V 3.0 - - 3.0 - ns VCC = 2.7 V 2.0 - - 2.0 - ns VCC = 3.0 V to 3.6 V 2.0 0 - 2.0 - ns VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns VCC = 2.7 V 1.5 - - 1.5 - ns VCC = 3.0 V to 3.6 V 1.5 0.6 - 1.5 - ns VCC = 1.65 V to 1.95 V 100 - - 64 - MHz VCC = 2.3 V to 2.7 V 125 - - 100 - MHz VCC = 2.7 V 150 - - 120 - MHz 150 - - 120 - MHz - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 11.6 - - pF VCC = 2.3 V to 2.7 V - 13.6 - - pF VCC = 3.0 V to 3.6 V - 15.4 - - pF Dn to CP; see Figure 9 Dn to CP; see Figure 9 see Figure 7 VCC = 3.0 V to 3.6 V tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per flip-flop; VI = GND to VCC [4] [1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL VCC2 fo) = sum of the outputs 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 8 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 11. Waveforms 1/f max VI CP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna894 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Clock input to output propagation delays, pulse width, output transition times, and the maximum frequency VI OE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled mna644 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. 3-state enable and disable times 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 9 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state VI VM CP input GND tsu tsu th th VI VM Dn input GND VOH VM Qn output VOL mna202 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 9. Table 8. Data set-up and hold times for the Dn input to the CP input Measurement points Supply voltage Input VCC VI VM VM VX VY 1.2 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V 1.65 V to 1.95 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V 2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 74LVC374A_Q100 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 10 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Load circuitry for switching times Table 9. Test data Supply voltage Input VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC 2 ns 30 pF 1 k open 2 VCC GND 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k open 2 VCC GND 2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 74LVC374A_Q100 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 11 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT163-1 (SO20) 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 12 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT360-1 (TSSOP20) 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 13 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT764-1 (DHVQFN20) 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 14 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic MIL Military 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC374A_Q100 v.1 20121122 Product data sheet - - 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 15 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC374A_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 16 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC374A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 November 2012 © NXP B.V. 2012. All rights reserved. 17 of 18 74LVC374A-Q100 NXP Semiconductors Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 November 2012 Document identifier: 74LVC374A_Q100