S6E1C3 Series
32-bit ARM® Cortex®-M0+
FM0+ Microcontroller
The S6E1C3 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power
consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of
2
2
peripheral functions such as various timers, ADC and communication interfaces (UART, CSIO (SPI), I C, I S, Smart Card, and USB).
The products which are described in this data sheet are placed into TYPE3-M0+ product categories in "FM0+ Family Peripheral
Manual".
Features
Bulk-transfer,
Interrupt-transfer and Isochronous-transfer
support
USB Device connected/disconnected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet-length supported
Wake-up function supported
32-bit ARM Cortex-M0+ Core
Processor version: r0p1
Maximum operating frequency: 40.8 MHz
Nested Vectored Interrupt Controller (NVIC): 1 NMI
(non-maskable interrupt) and 24 peripheral interrupt with 4
selectable interrupt priority levels
24-bit System timer (Sys Tick): System timer for OS task
Multi-Function Serial Interface (Max 6channels)
3 channels with 64Byte FIFO (Ch.4, 6 and 7), 3 channels
without FIFO (Ch.0, 1 and 3)
management
The operation mode of each channel can be selected from
Bit Band Operation
one of the following.
UART
CSIO (CSIO is known to many customers as SPI)
2
I C
Compatible with Cortex-M3 bit band operation.
On-Chip Memory
UART
Flash memory
Full
duplex double buffer
can be enabled or disabled.
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control* : Automatically control the
transmission by CTS/RTS (only ch.4)
* : S6E1C32B0A/S6E1C31B0A and
S6E1C32C0A/S6E1C31C0A do not support Hardware
Flow control.
Various error detection functions (parity errors, framing
errors, and overrun errors)
Up
to 128 Kbytes
Read cycle: 0 wait-cycle
Security function for code protection
Parity
SRAM
The on-chip SRAM of this series has one independent SRAM .
Up to 16 Kbytes
4Kbytes: can retain value in Deep standby Mode
USB Interface
USB interface is composed of Device and Host
With Main PLL, USB clock can be generated by multiplication
of Main clock.
CSIO (also known as SPI)
Full
duplex double buffer
dedicated baud rate generator
Overrun error detection function
Serial chip select function (ch1 and ch6 only)
Data length: 5 to 16 bits
Built-in
USB Device
USB
2.0 Full-Speed supported
6 EndPoint supported
EndPoint 0 is control transfer
EndPoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
EndPoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 comprise Double Buffer
The size of each EndPoint is according to the follows
EndPoint 0, 2 to 5 : 64 bytes
EndPoint 1 : 256 bytes
Max
•
•
•
•
•
•
•
I2 C
Standard-mode
(Max: 100 kbps) supported / Fast-mode
(Max 400 kbps) supported.
I2S (MFS-I2S)
2
Using
CSIO (Max 2 ch: ch.4, ch.6) and I S clock generator
Supports two transfer protocol
2
• IS
• MSB-justified
Master mode only
USB host
USB
2.0 Full/Low-Speed supported
Cypress Semiconductor Corporation
Document Number: 002-00233 Rev.*B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 4, 2016
S6E1C3 Series
I2C Slave
Free-running mode
I2C Slave supports the slave function of I2C and wake-up
Periodic mode (= Reload mode)
function from Standby mode.
Descriptor System Data Transfer Controller (DSTC)
(64 Channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the Descriptor system and,
following the specified contents of the Descriptor that has
already been constructed on the memory, can access directly
the memory / peripheral device and performs the data
transfer operation.
It supports the software activation, the hardware activation,
and the chain activation functions
One-shot mode
Real-Time Clock
The Real-time Clock counts
year/month/day/hour/minute/second/day of the week from year
00 to year 99.
The RTC can generate an interrupt at a specific time
(year/month/day/hour/minute/second/day of the week) and
can also generate an interrupt in a specific year, in a specific
month, on a specific day, at a specific hour or at a specific
minute.
It has a timer interrupt function generating an interrupt upon
a specific time or at specific intervals.
A/D Converter (Max: 8 Channels)
It can keep counting while rewriting the time.
12-bit A/D Converter
It can count leap years automatically.
Successive
approximation type
Conversion time: 2.0 μs @ 2.7 V to 3.6 V
Priority conversion available (2 levels of priority)
Scan conversion mode
Built-in FIFO for conversion data storage (for scan
conversion: 16 steps, for priority conversion: 4 steps)
Base Timer (Max: 8 Channels)
Watch Counter
The Watch Counter wakes up the microcontroller from the low
power consumption mode. The clock source can be selected
from the main clock, the sub clock, the built-in high-speed CR
clock or the built-in low-speed CR clock.
Interval timer: up to 64 s (sub clock: 32.768 kHz)
The operation mode of each channel can be selected from one
of the following.
External Interrupt Controller Unit
16-bit PWM timer
Up to 12 external interrupt input pins
16-bit PPG timer
Non-maskable interrupt (NMI) input pin: 1
16/32-bit reload timer
Watchdog Timer (2 Channels)
16/32-bit PWC timer
The watchdog timer generates an interrupt or a reset when the
counter reaches a time-out value.
General-Purpose I/O Port
This series consists of two different watchdogs, hardware
watchdog and software watchdog.
This series can use its pin as a general-purpose I/O port when
it is not used for an external bus or a peripheral function. All
ports can be set to fast general-purpose I/O ports or slow
general-purpose I/O ports. In addition, this series has a port
relocate function that can set to which I/O port a peripheral
function can be allocated.
All ports are Fast GPIO which can be accessed by 1cycle
The hardware watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the hardware watchdog is
active in any low-power consumption modes except RTC, Stop,
Deep standby RTC and Deep standby Stop mode.
CRC (Cyclic Redundancy Check) Accelerator
Capable of reading pin level directly
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
Port relocate function
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
Capable of controlling the pull-up of each pin
Up to 54 fast general-purpose I/O ports @64-pin package
Certain ports are 5 V tolerant.
See 4.List of Pin Functions and 5.I/O Circuit Typefor the
corresponding pins.
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters. The operation mode of each timer channel can be
selected from one of the following.
Document Number: 002-00233 Rev.*B
CCITT
CRC16 Generator Polynomial: 0x1021
CRC32 Generator Polynomial: 0x04C11DB7
IEEE-802.3
HDMI-CEC/Remote Control Receiver (Up to 2
Channels)
HDMI-CEC transmitter
Header
block automatic transmission by judging Signal
free
Generating status interrupt by detecting Arbitration lost
Page 2 of 107
S6E1C3 Series
Generating
START, EOM, ACK automatically to output
CEC transmission by setting 1 byte data
Generating transmission status interrupt when transmitting
1 block (1 byte data and EOM/ACK)
HDMI-CEC receiver
Automatic
ACK reply function available
Line error detection function available
Remote control receiver
4
bytes reception buffer
Repeat code detection function available
Smart Card Interface (Max 1 Channel)
Compliant with ISO7816-3 specification
Card Reader only/B class card only
Available protocols
Transmitter:
8E2, 8O2, 8N2
Receiver: 8E1, 8O1, 8N2, 8N1, 9N1
Inverse mode
TX/RX FIFO integrated (RX: 16-bytes, TX:16-bytes)
Clock and Reset
Clocks
A clock can be selected from five clock sources (two external
oscillators, two built-in CR oscillator, and main PLL).
Main clock:
8 MHz to 48 MHz
Sub clock:
32.768 kHz
Built-in high-speed CR clock: 8 MHz
Built-in low-speed CR clock: 100 kHz
Main PLL clock
8MHz to 16MHz (Input),
75MHz to 150MHz (Output)
Resets
Reset
request from the INITX pin
on reset
Software reset
Watchdog timer reset
Low-voltage detection reset
Clock supervisor reset
Power
Low-Voltage Detector (LVD)
This series monitors the voltage on the VCC pin with a 2-stage
mechanism. When the voltage falls below a designated voltage,
the Low-voltage Detector generates an interrupt or a reset.
LVD1: monitor VCC and error reporting via an interrupt
LVD2: auto-reset operation
Low Power Consumption Mode
This series has six low power consumption modes.
Sleep
Timer
RTC
Stop
Deep standby RTC (selectable between keeping the value of
RAM and not)
Deep standby Stop (selectable between keeping the value of
RAM and not)
Peripheral Clock Gating
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral functions
not used.
Debug
Serial Wire Debug Port (SW-DP)
Micro Trace Buffer (MTB)
Unique ID
A 41-bit unique value of the device has been set.
Power Supply
Wide voltage range:
VCC = 1.65V to 3.6 V
VCC = 3.0V to 3.6V (when USB is used)
Clock Supervisor (CSV)
The Clock Supervisor monitors the failure of external clocks
with a clock generated by a built-in CR oscillator.
If an external clock failure (clock stop) is detected, a reset is
asserted.
If an external frequency anomaly is detected, an interrupt or
a reset is asserted.
Document Number: 002-00233 Rev.*B
Page 3 of 107
S6E1C3 Series
Table of Contents
Features................................................................................................................................................................................... 1
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 15
5. I/O Circuit Type................................................................................................................................................................ 28
6. Handling Precautions ..................................................................................................................................................... 33
6.1
Precautions for Product Design ................................................................................................................................... 33
6.2
Precautions for Package Mounting .............................................................................................................................. 34
6.3
Precautions for Use Environment ................................................................................................................................ 36
7. Handling Devices ............................................................................................................................................................ 37
8. Block Diagram ................................................................................................................................................................. 40
9. Memory Map .................................................................................................................................................................... 41
10. Pin Status in Each CPU State ........................................................................................................................................ 44
11. Electrical Characteristics ............................................................................................................................................... 47
11.1 Absolute Maximum Ratings ......................................................................................................................................... 47
11.2 Recommended Operating Conditions.......................................................................................................................... 48
11.3 DC Characteristics....................................................................................................................................................... 49
11.3.1 Current Rating .............................................................................................................................................................. 49
11.3.2 Pin Characteristics ....................................................................................................................................................... 54
11.4 AC Characteristics ....................................................................................................................................................... 55
11.4.1 Main Clock Input Characteristics .................................................................................................................................. 55
11.4.2 Sub Clock Input Characteristics ................................................................................................................................... 56
11.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 57
11.4.4 Operating Conditions of Main PLL (In the Case of Using the Main Clock as the Input Clock of the PLL) .................... 58
11.4.5 Operating Conditions of Main PLL (In the Case of Using the Built-in High-Speed CR Clock as the Input Clock
of the Main PLL) ........................................................................................................................................................... 58
11.4.6 Reset Input Characteristics .......................................................................................................................................... 59
11.4.7 Power-on Reset Timing................................................................................................................................................ 59
11.4.8 Base Timer Input Timing .............................................................................................................................................. 60
11.4.9 CSIO/SPI/UART Timing ............................................................................................................................................... 61
11.4.10 External Input Timing ................................................................................................................................................ 78
2
11.4.11 I C Timing / I2C Slave Timing ................................................................................................................................... 79
2
11.4.12 I S Timing (MFS-I2S Timing) .................................................................................................................................... 80
11.4.13 Smart Card Interface Characteristics ........................................................................................................................ 82
11.4.14 SW-DP Timing .......................................................................................................................................................... 83
11.5 12-bit A/D Converter .................................................................................................................................................... 84
11.6 USB Characteristics .................................................................................................................................................... 87
11.7 Low-Voltage Detection Characteristics ........................................................................................................................ 92
11.7.1 Low-Voltage Detection Reset ....................................................................................................................................... 92
11.7.2 Low-Voltage Detection Interrupt ................................................................................................................................... 93
11.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 94
11.9 Return Time from Low-Power Consumption Mode ...................................................................................................... 95
11.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 95
11.9.2 Return Factor: Reset .................................................................................................................................................... 97
12. Ordering Information ...................................................................................................................................................... 99
13. Package Dimensions .................................................................................................................................................... 100
Document History ............................................................................................................................................................... 106
Document Number: 002-00233 Rev.*B
Page 4 of 107
S6E1C3 Series
Sales, Solutions, and Legal Information........................................................................................................................... 107
Document Number: 002-00233 Rev.*B
Page 5 of 107
S6E1C3 Series
1. Product Lineup
Memory Size
S6E1C31B0A/
S6E1C31C0A/
S6E1C31D0A
64 Kbytes
12 Kbytes
Product name
On-chip Flash memory
On-chip SRAM
Function
Product name
Pin count
CPU
Frequency
Power supply voltage range
USB2.0 (Device/Host)
DSTC
Multi-function Serial Interface
2
(UART/CSIO/I C/I2S)
Base Timer
(PWC/Reload timer/PWM/PPG)
Dual Timer
HDMI-CEC/ Remote Control
Receiver
I2C Slave
Smart Card Interface
Real-time Clock
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupt
S6E1C32B0A/
S6E1C32C0A/
S6E1C32D0A
128 Kbytes
16 Kbytes
S6E1C32B0A
(WLCSP)
TBD
S6E1C32B0A/
S6E1C32C0A/
S6E1C31B0A
S6E1C32C0A
32
48
Cortex-M0+
40.8 MHz
1.65 V to 3.6 V
1 unit
64 ch.
6 ch. (Max)
4 ch. (Max)
2 ch. (Max)
Ch.0/1/3 without
Ch.0/1/3 without
Ch.0/3 without
FIFO
FIFO
FIFO
Ch.4/6/7 with
Ch. 6 with FIFO
FIFO
I2S : 1 ch (Max)
I2S : No
Ch. 6 with FIFO
S6E1C31D0A/
S6E1C32D0A
64
6 ch. (Max)
Ch.0/1/3 without
FIFO
Ch.4/6/7 with
FIFO
I2S : 2 ch (Max)
Ch. 4/6 with FIFO
8 ch. (Max)
1 unit
1 ch.(Max)
Ch.1
2 ch (Max)
Ch.0/1
1 ch (Max)
No
No
5 pins (Max),
NMI × 1
20 pins (Max)
4 ch (1 unit)
1 unit
1 unit
Yes
1 ch. (SW) + 1 ch. (HW)
7 pins (Max),
9 pins (Max),
NMI x 1
NMI x 1
24 pins (Max)
38 pins (Max)
6 ch. (1 unit)
8 ch. (1 unit)
Yes
2 ch.
8 MHz (Typ)
100 kHz (Typ)
SW-DP
Yes
1 ch (Max)
12 pins (Max),
NMI x 1
54 pins (Max)
8 ch. (1 unit)
I/O port
12-bit A/D converter
CSV (Clock Supervisor)
LVD (Low-voltage Detection)
High-speed
Built-in CR
Low-speed
Debug Function
Unique ID
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use
the port relocate function of the I/O port according to your function use.
See "11. Electrical Characteristics 11.4 AC Characteristics 11.4.3 Built-in CR Oscillation Characteristics" for accuracy of built-in
CR.
Document Number: 002-00233 Rev.*B
Page 6 of 107
S6E1C3 Series
2. Packages
Product name
Package
WLCSP (TBD)
LQFP: LQB032 (0.80 mm pitch)
QFN: WNU032 (0.50 mm pitch)
LQFP: LQA048-02 (0.50 mm pitch)
QFN: WNY048 (0.50 mm pitch)
LQFP: LQD064-02 (0.50 mm pitch)
QFN: WNS064 (0.50 mm pitch)
: Available
S6E1C32B0A
(WLCSP)
-
S6E1C32B0A/
S6E1C31B0A
-
S6E1C32C0A/
S6E1C31C0A
-
S6E1C32D0A/
S6E1C31D0A
-
-
Note:
See "13. Package Dimensions" for detailed information on each package.
−
Document Number: 002-00233 Rev.*B
Page 7 of 107
S6E1C3 Series
3. Pin Assignment
LQD064-02
(TOP VIEW)
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-00233 Rev.*B
Page 8 of 107
S6E1C3 Series
WNS064
(TOP VIEW)
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-00233 Rev.*B
Page 9 of 107
S6E1C3 Series
LQA048-02
(TOP VIEW)
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-00233 Rev.*B
Page 10 of 107
S6E1C3 Series
WNY048
(TOP VIEW)
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-00233 Rev.*B
Page 11 of 107
S6E1C3 Series
LQB032
(TOP VIEW)
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-00233 Rev.*B
Page 12 of 107
S6E1C3 Series
WNU032
(TOP VIEW)
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-00233 Rev.*B
Page 13 of 107
S6E1C3 Series
WLCSP
TBD
Note:
−
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-00233 Rev.*B
Page 14 of 107
S6E1C3 Series
4. List of Pin Functions
List of Pin Numbers
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel
on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select
the pin to be used.
Pin no.
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
1
1
2
-
Pin Function
P50
SIN3_1
I/O circuit
type
Pin state
type
D
K
D
K
D
K
D
K
D
K
H
K
H
K
H
K
H
K
INT00_0
P51
2
2
3
-
3
3
4
-
SOT3_1
INT01_0
P52
SCK3_1
INT02_0
P53
4
4
-
-
TIOA1_2
INT07_2
P30
SCS60_1
5
5
-
-
TIOB0_1
INT03_2
MI2SWS6_1
P31
6
6
-
-
SCK6_1
SI2CSCL6_1
INT04_2
MI2SCK6_1
-
-
5
-
P31
SCK6_1
SI2CSCL6_1
INT04_2
P32
SOT6_1
7
7
-
-
SI2CSDA6_1
TIOB2_1
INT05_2
MI2SDO6_1
P32
SOT6_1
-
-
6
-
SI2CSDA6_1
TIOB2_1
INT05_2
Document Number: 002-00233 Rev.*B
Page 15 of 107
S6E1C3 Series
Pin no.
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
Pin Function
I/O circuit
type
Pin state
type
H
K
H
K
D
K
D
K
D
K
D
K
D
K
D
K
D
K
D
K
D
K
D
K
P33
ADTG_6
8
8
-
-
SIN6_1
INT04_0
MI2SDI6_1
P33
-
-
7
-
ADTG_6
SIN6_1
INT04_0
P34
9
-
-
-
SCS61_1
TIOB4_1
MI2SMCK6_1
P34
-
10
9
-
-
-
-
-
SCS61_1
MI2SMCK6_1
P35
SCS62_1
TIOB5_1
INT08_1
P3A
TIOA0_1
11
-
-
-
INT03_0
RTCCO_2
SUBOUT_2
IC1_CIN_0
P3A
TIOA0_1
-
10
-
-
INT03_0
RTCCO_2
SUBOUT_2
P3B
12
-
-
-
-
11
-
-
13
-
-
-
-
12
-
-
14
-
-
-
Document Number: 002-00233 Rev.*B
TIOA1_1
IC1_DATA_0
P3B
TIOA1_1
P3C
TIOA2_1
IC1_RST_0
P3C
TIOA2_1
P3D
TIOA3_1
IC1_VPEN_0
Page 16 of 107
S6E1C3 Series
Pin no.
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
15
-
-
-
Pin Function
P3E
TIOA4_1
I/O circuit
type
Pin state
type
D
K
IC1_VCC_0
P3F
16
-
-
-
TIOA5_1
IC1_CLK_0
D
K
17
13
8
-
I
F
18
14
9
-
MD0
PE2
A
A
19
15
10
-
A
B
20
-
-
-
D
K
21
-
-
-
D
K
D
K
D
K
D
K
D
K
D
K
22
-
-
-
23
-
-
-
24
-
-
-
X0
PE3
X1
P40
TIOA0_0
INT12_1
P41
TIOA1_0
INT13_1
P42
TIOA2_0
P43
ADTG_7
TIOA3_0
P4C
SCK7_1
TIOB3_0
P4C
-
16
-
-
25
17
-
-
26
18
-
-
SIN7_1
INT06_2
D
K
27
28
19
20
11
12
-
VCC
C
-
-
29
21
13
-
-
-
30
22
14
-
VSS
P46
C
C
31
23
15
-
C
D
32
24
16
-
B
E
H
K
33
25
17
Document Number: 002-00233 Rev.*B
-
SCK7_1
P4D
SOT7_1
P4E
X0A
P47
X1A
INITX
P60
TIOA2_2
INT15_1
CEC1_0
Page 17 of 107
S6E1C3 Series
Pin no.
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
34
-
-
-
Pin Function
P1E
RTS4_1
I/O circuit
type
Pin state
type
D
K
D
K
D
K
D
K
D
K
H
K
H
K
D
K
F
J
G
J
F
J
F
J
F
J
MI2SMCK4_1
P1D
35
-
-
-
36
-
-
-
CTS4_1
MI2SWS4_1
P1C
SCK4_1
MI2SCK4_1
P1B
37
-
-
-
-
26
-
-
SOT4_1
MI2SDO4_1
P1B
SOT4_1
P1A
SIN4_1
38
-
-
-
INT05_1
CEC0_0
MI2SDI4_1
P1A
-
27
-
-
39
-
-
-
40
28
18
-
41
29
19
-
SIN4_1
INT05_1
CEC0_0
P1F
ADTG_5
P10
AN00
P11
AN01
SIN1_1
INT02_1
WKUP1
42
30
20
-
P12
AN02
SOT1_1
P13
43
31
21
-
AN03
SCK1_1
RTCCO_1
SUBOUT_1
P14
AN04
44
32
-
-
SIN0_1
SCS10_1
INT03_1
Document Number: 002-00233 Rev.*B
Page 18 of 107
S6E1C3 Series
Pin no.
LQFP-64
QFN-64
45
LQFP-48
QFN-48
33
LQFP-32
QFN-32
-
WLCSP
(TBD)
-
Pin Function
P15
AN05
SOT0_1
SCS11_1
P23
AN06
I/O circuit
type
Pin state
type
F
J
F
J
46
34
22
-
47
35
23
-
P22
AN07
F
J
48
36
24
-
TIOB7_1
VCC
-
-
49
50
37
38
25
-
AVRH *
AVRL
-
-
51
39
26
-
P21
INT06_1
E
K
E
K
D
K
E
K
D
K
E
K
-
-
52
-
-
-
53
40
27
-
54
-
-
-
55
41
28
-
SCK0_0
TIOA7_1
WKUP2
P00
WKUP4
P01
SWCLK
SOT0_0
P02
WKUP5
P03
SWDIO
SIN0_0
TIOB7_0
P05
MD1
56
42
29
-
TIOA5_2
INT00_1
57
43
-
-
58
44
30
-
P80
UDM0
J
G
59
45
31
-
P81
UDP0
J
G
60
46
32
-
VSS
P61
-
-
61
47
-
-
UHCONX0
TIOB2_2
H
K
62
-
-
-
E
K
WKUP3
VCC
P0B
TIOB6_1
WKUP6
Document Number: 002-00233 Rev.*B
Page 19 of 107
S6E1C3 Series
Pin no.
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
63
-
-
-
Pin Function
P0C
TIOA6_1
I/O circuit
type
Pin state
type
E
K
E
I
WKUP7
P0F
64
48
1
-
NMIX
WKUP0
RTCCO_0
SUBOUT_0
CROUT_1
*: In case of 32-pin package, AVRH pin is internally connected to VCC pin.
Document Number: 002-00233 Rev.*B
Page 20 of 107
S6E1C3 Series
List of Pin Functions
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel
on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select
the pin to be used.
Pin no.
Pin function
Pin name
ADC
ADTG_5
ADTG_6
ADC
Base Timer 0
Base Timer 1
Function description
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
39
8
8
7
-
ADTG_7
AN00
23
40
28
18
-
AN01
AN02
41
42
29
30
19
20
-
43
44
31
32
21
-
-
AN05
AN06
45
46
33
34
22
-
AN07
TIOA0_0
47
20
35
-
23
-
-
Base timer ch.0 TIOB pin
11
5
10
5
-
-
Base timer ch.1 TIOA pin
21
12
11
-
-
4
22
4
-
-
-
13
33
12
25
17
-
AN03
AN04
TIOA0_1
TIOB0_1
TIOA1_0
TIOA1_1
A/D converter external trigger input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
TIOA1_2
TIOA2_0
Base Timer 2
Base Timer 3
Base Timer 4
Base Timer 5
Base Timer 6
Base Timer 7
TIOA2_1
TIOA2_2
TIOB2_1
TIOB2_2
Base timer ch.2 TIOB pin
7
61
7
47
6
-
-
TIOA3_0
TIOA3_1
Base timer ch.3 TIOA pin
23
14
-
-
-
TIOB3_0
TIOA4_1
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
24
15
-
-
-
TIOB4_1
TIOA5_1
Base timer ch.4 TIOB pin
9
16
-
-
-
Base timer ch.5 TIOB pin
56
10
42
-
29
-
-
TIOA6_1
TIOB6_1
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
63
62
-
-
-
TIOA7_1
TIOB7_0
Base timer ch.7 TIOA pin
46
55
34
41
22
28
-
47
53
35
40
23
27
-
55
41
28
-
TIOA5_2
TIOB5_1
TIOB7_1
SWCLK
Debugger
Base timer ch.2 TIOA pin
SWDIO
Document Number: 002-00233 Rev.*B
Base timer ch.5 TIOA pin
Base timer ch.7 TIOB pin
Serial wire debug interface clock input pin
Serial wire debug interface data input /
output pin
Page 21 of 107
S6E1C3 Series
Pin no.
Pin function
Pin name
INT00_0
INT00_1
INT01_0
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
External
Interrupt
GPIO
GPIO
GPIO
Function description
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
1
56
1
42
2
29
-
2
3
2
3
3
4
-
41
11
29
10
19
-
-
44
5
32
5
-
-
INT04_0
INT04_2
External interrupt request 04 input pin
8
6
8
6
7
5
-
INT05_1
INT05_2
External interrupt request 05 input pin
38
7
27
7
6
-
INT06_1
INT06_2
External interrupt request 06 input pin
51
26
39
18
26
-
-
INT07_2
INT08_1
External interrupt request 07 input pin
External interrupt request 08 input pin
4
10
4
-
-
-
INT12_1
INT13_1
External interrupt request 12 input pin
External interrupt request 13 input pin
20
21
-
-
-
INT15_1
NMIX
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
33
64
25
48
17
1
-
P00
P01
52
53
40
27
-
P02
P03
54
55
41
28
-
56
62
42
-
29
-
-
P0C
P0F
63
64
48
1
-
P10
P11
40
41
28
29
18
19
-
P12
P13
42
43
30
31
20
21
-
P14
P15
44
45
32
33
-
-
38
37
27
26
-
-
P1C
P1D
36
35
-
-
-
P1E
P1F
34
39
-
-
-
51
47
39
35
26
23
-
46
34
22
-
P05
P0B
P1A
P1B
P21
P22
P23
Document Number: 002-00233 Rev.*B
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
Page 22 of 107
S6E1C3 Series
Pin no.
Pin function
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Pin name
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
P30
P31
5
6
5
6
5
-
P32
P33
7
8
7
8
6
7
-
P34
P35
9
10
9
-
-
-
11
12
10
11
-
-
P3C
P3D
13
14
12
-
-
-
P3E
P3F
15
16
-
-
-
P40
P41
20
21
-
-
-
P42
P43
22
23
-
-
-
30
31
22
23
14
15
-
P4C
P4D
24
25
16
17
-
-
P4E
P50
26
1
18
1
2
-
2
3
2
3
3
4
-
4
33
4
25
17
-
61
58
47
44
30
-
59
18
45
14
31
9
-
19
55
15
41
10
28
-
44
32
-
-
53
40
27
-
45
33
-
-
46
34
22
-
P3A
P3B
P46
P47
P51
P52
P53
P60
P61
P80
P81
PE2
PE3
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
Multi-function
Serial 0
Function description
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
Document Number: 002-00233 Rev.*B
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
Multi-function serial interface ch.0 input
pin
Multi-function serial interface ch.0 output
pin. This pin operates as SOT0 when
used as a UART/CSIO/LIN pin (operation
mode 0 to 3) and as SDA0 when used as
an I2C pin (operation mode 4).
Multi-function serial interface ch.0 clock
I/O pin. This pin operates as SCK0 when
used as a CSIO pin (operation mode 2)
and as SCL0 when used as an I2C pin
(operation mode 4).
Page 23 of 107
S6E1C3 Series
Pin no.
Pin function
Pin name
SIN1_1
Multi-function
Serial 1
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
41
29
19
-
Multi-function serial interface ch.1 output
pin. This pin operates as SOT1 when
used as a UART/CSIO/LIN pin (operation
mode 0 to 3) and as SDA1 when used as
an I2C pin (operation mode 4).
42
30
20
-
SCK1_1
(SCL1_1)
Multi-function serial interface ch.1 clock
I/O pin. This pin operates as SCK1 when
used as a CSIO pin (operation mode 2)
and as SCL1 when used as an I2C pin
(operation mode 4).
43
31
21
-
SCS10_1
Multi-function serial interface ch.1 serial
chip select 0 input/output pin.
44
32
-
-
45
33
-
-
1
1
2
-
2
2
3
-
3
3
4
-
38
27
-
-
37
26
-
-
36
-
-
-
35
-
-
-
34
-
-
-
SIN3_1
SOT3_1
(SDA3_1)
SCK3_1
(SCL3_1)
SIN4_1
SOT4_1
(SDA4_1)
Multi-function
Serial 4
Multi-function serial interface ch.1 input
pin
LQFP-64
QFN-64
SOT1_1
(SDA1_1)
SCS11_1
Multi-function
Serial 3
Function description
SCK4_1
(SCL4_1)
CTS4_1
RTS4_1
Document Number: 002-00233 Rev.*B
Multi-function serial interface ch.1 serial
chip select 1 output pin.
Multi-function serial interface ch.3 input
pin
Multi-function serial interface ch.3 output
pin. This pin operates as SOT3 when
used as a UART/CSIO/LIN pin (operation
mode 0 to 3) and as SDA3 when used as
an I2C pin (operation mode 4).
Multi-function serial interface ch.3 clock
I/O pin. This pin operates as SCK3 when
used as a CSIO (operation mode 2) and
as SCL3 when used as an I2C pin
(operation mode 4).
Multi-function serial interface ch.4 input
pin
Multi-function serial interface ch.4 output
pin. This pin operates as SOT4 when
used as a UART/CSIO/LIN pin (operation
mode 0 to 3) and as SDA4 when used as
an I2C pin (operation mode 4).
Multi-function serial interface ch.4 clock
I/O pin. This pin operates as SCK4 when
used as a CSIO (operation mode 2) and
as SCL4 when used as an I2C pin
(operation mode 4).
Multi-function serial interface ch4 CTS
input pin
Multi-function serial interface ch4 RTS
output pin
Page 24 of 107
S6E1C3 Series
Pin no.
Pin function
Pin name
SIN6_1
SOT6_1
(SDA6_1)
Multi-function
Serial 6
SCK6_1
(SCL6_1)
SCS60_1
Multi-function serial interface ch.6 input
pin
Multi-function serial interface ch.6 output
pin. This pin operates as SOT6 when
used as a UART/CSIO/LIN pin (operation
mode 0 to 3) and as SDA6 when used as
an I2C pin (operation mode 4).
Multi-function serial interface ch.6 clock
I/O pin. This pin operates as SCK6 when
used as a CSIO (operation mode 2) and
as SCL6 when used as an I2C pin
(operation mode 4).
Multi-function serial interface ch.6 serial
chip select 0 input/output pin.
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
8
8
7
-
7
7
6
-
6
6
5
-
5
5
-
-
SCS61_1
Multi-function serial interface ch.6 serial
chip select 1 output pin.
9
9
-
-
SCS62_1
Multi-function serial interface ch.6 serial
chip select 2 output pin.
10
-
-
-
26
18
-
-
25
17
-
-
24
16
-
-
SIN7_1
Multi-function
Serial 7
Function description
SOT7_1
(SDA7_1)
SCK7_1
(SCL7_1)
Document Number: 002-00233 Rev.*B
Multi-function serial interface ch.7 input
pin
Multi-function serial interface ch.7 output
pin. This pin operates as SOT7 when
used as a UART/CSIO/LIN pin (operation
mode 0 to 3) and as SDA7 when used as
an I2C pin (operation mode 4).
Multi-function serial interface ch.7 clock
I/O pin. This pin operates as SCK7 when
used as a CSIO (operation mode 2) and
as SCL7 when used as an I2C pin
(operation mode 4).
Page 25 of 107
S6E1C3 Series
Pin no.
Pin function
Pin name
MI2SDI4_1
MI2SDO4_1
MI2SCK4_1
MI2SWS4_1
MI2SMCK4_1
I2S(MFS)
MI2SDI6_1
MI2SDO6_1
MI2SCK6_1
MI2SWS6_1
MI2SMCK6_1
IC1_CIN_0
USB
LQFP-32
QFN-32
WLCSP
(TBD)
38
-
-
-
37
-
-
-
36
-
-
-
35
-
-
-
I2S Master Clock Input/output pin
(operation mode 2).
34
-
-
-
I2S Serial Data Input pin (operation mode
2).
8
8
-
-
7
7
-
-
6
6
-
-
5
5
-
-
9
9
-
-
I2S Serial Data Input pin (operation mode
2).
I2S Serial Data Output pin (operation
mode 2).
I2S Serial Clock Output pin (operation
mode 2).
I2S Word Select Output pin (operation
mode 2).
I2S Serial Data Output pin (operation
mode 2).
I2S Serial Clock Output pin (operation
mode 2).
I2S Word Select Output pin (operation
mode 2).
I2S Master Clock Input/output pin
(operation mode 2).
-
-
-
16
-
-
-
IC1_DATA_0
12
-
-
-
IC1_RST_0
IC1_VCC_0
Smart Card reset output pin
Smart Card power enable output pin
13
15
-
-
-
IC1_VPEN_0
UDM0
Smart Card programming output pin
USB function/host D – pin
14
58
44
30
-
USB function/host D + pin
USB external pull-up control pin
59
61
45
47
31
-
-
64
43
48
31
1
21
-
11
64
10
48
1
-
43
11
31
10
21
-
-
UDP0
UHCONX0
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
HDMI-CEC/Re
mote Control
Reception
LQFP-48
QFN-48
11
RTCCO_0
RTCCO_1
Real-time
Clock
LQFP-64
QFN-64
Smart Card insert detection output pin
Smart Card serial interface clock output
pin
Smart Card serial interface data input pin
IC1_CLK_0
Smart Card
Interface
Function description
0.5 seconds pulse output pin of
real-time clock
Sub clock output pin
CEC0_0
HDMI-CEC/Remote Control Reception
ch.0 input/output pin
38
27
-
-
CEC1_0
HDMI-CEC/Remote Control Reception
ch.1 input/output pin
33
25
17
-
Document Number: 002-00233 Rev.*B
Page 26 of 107
S6E1C3 Series
Pin no.
Pin function
Pin name
WKUP0
WKUP1
WKUP2
Low Power
Consumption
Mode
WKUP3
WKUP4
WKUP5
WKUP6
WKUP7
Function description
Deep Standby mode return signal input
pin 0
Deep Standby mode return signal input
pin 1
Deep Standby mode return signal input
pin 2
Deep Standby mode return signal input
pin 3
Deep Standby mode return signal input
pin 4
Deep Standby mode return signal input
pin 5
Deep Standby mode return signal input
pin 6
Deep Standby mode return signal input
pin 7
I2C Clock Pin
I2C Data Pin
LQFP-64
QFN-64
LQFP-48
QFN-48
LQFP-32
QFN-32
WLCSP
(TBD)
64
48
1
-
41
29
19
-
51
39
26
-
56
42
29
-
52
-
-
-
54
-
-
-
62
-
-
-
63
-
-
-
6
7
6
7
5
6
-
I2C Slave
SI2CSCL6_1
SI2CSDA6_1
RESET
INITX
External Reset Input pin.
A reset is valid when INITX="L".
32
24
16
-
MD0
Mode 0 pin.
During normal operation, input MD0="L".
During serial programming to Flash
memory, input MD0="H".
17
13
8
-
56
42
29
-
18
30
14
22
9
14
-
MODE
X0
X0A
Mode 1 pin.
During normal operation, input is not
needed.
During serial programming to Flash
memory, MD1 = "L" must be input.
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
X1
X1A
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
19
31
15
23
10
15
-
Built-in high-speed CR oscillation clock
output port
64
48
1
-
27
48
19
36
11
24
-
57
29
43
21
13
-
60
46
32
-
49
37
-
-
50
38
25
-
28
20
12
-
MD1
CLOCK
CROUT_1
POWER
GND
VCC
VCC
VCC
VSS
VSS
Power supply pin
GND pin
A/D converter analog reference voltage
AVRH *
Analog
input pin
A/D converter analog reference voltage
Reference
AVRL
input pin
Power supply stabilization capacitance
C pin
C
pin
*: In case of 32-pin package, AVRH pin is internally connected to VCC pin.
Document Number: 002-00233 Rev.*B
Page 27 of 107
S6E1C3 Series
5. I/O Circuit Type
Type
Circuit
P-ch
P-ch
Digital output
N-ch
Digital output
Remarks
X1
R
Pull-up resistor control
Digital input
Standby mode Control
Clock input
It is possible to select the main
oscillation / GPIO function
When the main oscillation is
selected.
・Oscillation feedback resistor
: Approximately 1MΩ
・With standby mode control
A
Standby mode Control
Digital input
Standby mode Control
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
When the GPIO is selected.
・CMOS level output.
・CMOS level hysteresis input
・With pull-up resistor control
・With standby mode control
・Pull-up resistor
: Approximately 33kΩ
・IOH= -4mA, IOL= 4mA
Pull-up resistor control
B
Pull-up resistor
Digital input
Document Number: 002-00233 Rev.*B
CMOS level hysteresis input
Pull-up resistor
: Approximately 33kΩ
Page 28 of 107
S6E1C3 Series
Type
Circuit
P-ch
P-ch
Digital output
N-ch
Digital output
Remarks
X1A
R
Pull-up resistor control
Digital input
Standby mode Control
Clock input
C
Standby mode Control
Digital input
Standby mode Control
R
P-ch
P-ch
Digital output
N-ch
Digital output
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is selected.
Oscillation feedback resistor
: Approximately 5MΩ
With Standby mode control
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33kΩ
IOH= -4mA, IOL= 4mA
X0A
Pull-up resistor control
Document Number: 002-00233 Rev.*B
Page 29 of 107
S6E1C3 Series
Type
Circuit
P-ch
D
P-ch
Digital output
N-ch
Digital output
R
Pull-up resistor control
Digital input
Remarks
・ CMOS level output
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 33kΩ
・ IOH= -4mA, IOL= 4mA
・ When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Standby mode Control
P-ch
E
P-ch
Digital output
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
・ CMOS level output
・ CMOS level hysteresis input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 33kΩ
・ IOH= -4mA, IOL= 4mA
・ When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Wake up request
Wake up control
Document Number: 002-00233 Rev.*B
Page 30 of 107
S6E1C3 Series
Type
Circuit
P-ch
P-ch
Digital output
N-ch
Digital output
R
F
Pull-up resistor control
Digital input
Standby mode Control
Analog input
Remarks
・ CMOS level output
・ CMOS level hysteresis input
・ With input control
・ Analog input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 33kΩ
・ IOH= -4mA, IOL= 4mA
・ When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Input control
P-ch
P-ch
Digital output
N-ch
Digital output
R
G
Pull-up resistor control
Digital input
Standby mode Control
Wake up request
Wake up Control
・ CMOS level output
・ CMOS level hysteresis input
・ With input control
・ Analog input
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 33kΩ
・ IOH= -4mA, IOL= 4mA
・ When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
Analog input
Input control
Document Number: 002-00233 Rev.*B
Page 31 of 107
S6E1C3 Series
Type
Circuit
P-ch
H
Remarks
P-ch
Digital output
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
I
Mode input
・ CMOS level output
・ CMOS level hysteresis input
・ 5V tolerant
・ With pull-up resistor control
・ With standby mode control
・ Pull-up resistor
: Approximately 33kΩ
・ IOH= -4mA, IOL= 4mA
・ Available to control PZR
registers
・ When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
・ CMOS level hysteresis input
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP output
UDP0/P81
USB Full-speed/Low-speed control
UDP input
J
Differential
UDM0/P80
Differential input
USB/GPIO select
UDM input
UDM output
It is possible to select the USB I/O /
GPIO function.
When the USB I/O is selected.
Full-speed, Low-speed control
When the GPIO is selected.
CMOS level output
CMOS level hysteresis input
With standby mode control
USB Digital input/output direction
GPIO Digital input
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-00233 Rev.*B
Page 32 of 107
S6E1C3 Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Spansion semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Document Number: 002-00233 Rev.*B
Page 33 of 107
S6E1C3 Series
Latch-Up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Spansion's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Spansion
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Document Number: 002-00233 Rev.*B
Page 34 of 107
S6E1C3 Series
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Spansion ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 ˚C
and 30 ˚C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-00233 Rev.*B
Page 35 of 107
S6E1C3 Series
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-00233 Rev.*B
Page 36 of 107
S6E1C3 Series
7. Handling Devices
Power Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVRH pin and AVRL pin near this device.
Stabilizing Supply Voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub Crystal Oscillator
This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions
is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size: More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
Lead type
Load capacitance: Approximately 6 pF to 7 pF
Document Number: 002-00233 Rev.*B
Page 37 of 107
S6E1C3 Series
Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
However in the Deep Standby mode, an external clock as an input of the sub clock cannot be used.
Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
Set as
External clock
input
X1(PE3),
X1A (P47)
2
Handling when Using Multi-Function Serial Pin as I C Pin
2
2
If it is using the multi-function serial pin as I C pins, P-ch transistor of digital output is always disabled. However, I C pins need to
2
keep the electrical characteristic like other pins and not to connect to the external I C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
Incidentally, the C pin becomes floating in Deep standby mode.
C
Device
CS
VSS
GND
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Document Number: 002-00233 Rev.*B
Page 38 of 107
S6E1C3 Series
Notes on Power-on
Turn power on/off in the following order or at the same time.
Turning on : VCC →AVRH
Turning off : AVRH →VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise; perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in Features Among the Products with Different Memory Sizes and Between Flash Memory
Products and MASK Products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up Function of 5 V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Handling when Using Debug Pins
When debug pins (SWDIO/SWCLK) are set to GPIO or other peripheral functions, set them as output only; do not set them as input.
Document Number: 002-00233 Rev.*B
Page 39 of 107
S6E1C3 Series
8. Block Diagram
SWCLK
SWDIO
SW-DP
Fast
GPIO
Cortex-M0+Core
On-Chip SRAM
12/16Kbyte
Flash I/F
On-Chip FLASH
64/128Kbyte
Bit Band
Wrapper
NVIC
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
Security
Multi-layer AHB
AHB-APB Bridge
APB0
System ROM table
INITX
MTB
WatchDog Timer
(Hardware)
DSTC
64ch.
WatchDog Timer
(CVS)
Main
Osc
Sub
Osc
AHB-AHB
Bridge
Source Clock
X0
X1
X0A
X1A
PLL
CR
8MHz
CR
100KHz
CROUT
AVRH
AVRL
ANxx
ADTG
USB2.0
(Host/Device)
PHY
UDP0,
UDM0
UHCONX0
Power-On
LVD Ctrl
12-bit A/D Converter
IRQ-Monitor
Unit 0
LVD
Regulator
C
Watch Counter
Base Timer
16-bit 8 ch.
32-bit 4 ch.
CRC Accelarator
Real-Time Clock
AHB-APB Bridge : APB1
TIOAx
TIOBx
External Interrupt
Controller
12 pin(Max) + NMI
NMIX
MODE-Ctrl
MD0,
MD1
Deep Standby Ctrl
Peripheral Clock
Gating
GPIO
Smart Card I/F
PIN-Function-Ctrl
P0x,
P1x,
:
PEx
SCKx
SINx
SOTx
SCSx
MI2SCKx
MI2SDIx
MI2SDOx
MI2SMCKx
MI2SWSx
IC1_CLKx
IC1_VCCx
IC1_VPENx
IC1_CINx
IC1_DATAx
I2C Slave
Document Number: 002-00233 Rev.*B
INTx
Low-Speed CR
Multi-function Serial
I/F
6 ch. (Max)
WKUPx
RTCCO
SI2CSCLx
SI2CSDAx
Page 40 of 107
S6E1C3 Series
9. Memory Map
Memory Map (1)
See "Memory map (2)" for the memory size details.
Document Number: 002-00233 Rev.*B
Page 41 of 107
S6E1C3 Series
Memory Map (2)
S6E1C31B0A
S6E1C31C0A
S6E1C31D0A
0x2008_0000
S6E1C32B0A
S6E1C32C0A
S6E1C32D0A
0x2008_0000
Reserved
0x2000_4000
0x2000_3000
0x2000_1000
Reserved
0x2000_4000
SRAM
4K byte
0x2000_3000
SRAM
8K byte
SRAM
4K byte
SRAM
12K byte
0x2000_0000
Reserved
0x0010_0004
0x0010_0000
CR trimming
Security
Reserved
0x0010_0004
0x0010_0000
CR trimming
Security
Reserved
Reserved
0x0001_FFF0
0x0000_FFF0
Flash
131056 Byte
(128Kbyte - 16Byte)*
Flash
65520 Byte
(64Kbyte - 16Byte) *
0x0000_0000
0x0000_0000
*: See "S6E1C1/C3 Series Flash Programming Manual" to check details of the Flash memory.
Document Number: 002-00233 Rev.*B
Page 42 of 107
S6E1C3 Series
Peripheral Address Map
Start address
0x4000_0000
End address
0x4000_0FFF
Bus
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog Timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Reserved
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
Reserved
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
Reserved
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_5000
0x4003_6000
0x4003_7000
0x4003_4FFF
0x4003_5FFF
0x4003_6FFF
0x4003_77FF
0x4003_7800
0x4003_79FF
I2C Slave
0x4003_7A00
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function Serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
AHB
APB0
APB1
Peripheral
Flash memory I/F register
Reserved
Software Watchdog Timer
Reserved
HDMI-CEC/Remote Control Receiver
Low-Voltage Detection / DS mode / Vref Calibration
USB Clock Generator
Reserved
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_C0FF
Low-speed CR Prescaler
0x4003_C100
0x4003_C800
0x4003_C900
0x4003_CA00
0x4003_CB00
0x4004_0000
0x4005_0000
0x4006_1000
0x4006_2000
0x4003_C7FF
0x4003_C8FF
0x4003_C9FF
0x4003_CAFF
0x4003_FFFF
0x4004_FFFF
0x4006_0FFF
0x4006_1FFF
0x41FF_FFFF
Peripheral Clock Gating
Reserved
Smart Card Interface
MFS-I2S Clock Generator
Reserved
USB ch.0
Reserved
DSTC
Reserved
Document Number: 002-00233 Rev.*B
AHB
Page 43 of 107
S6E1C3 Series
10. Pin Status in Each CPU State
The following table shows pin status in each CPU state.
CPU state
Type Selected Pin function
Main osillation circuit
Main osillation circuit
selected *1
selected
A
Main clock external
Digital I/O slected *2
input selected
GPIO selected
B
Main osillation circuit
Main osillation circuit
selected *1
selected
Digital I/O slected *2
GPIO selected
Sub osillation circuit
Sub osillation circuit
selected *1
selected
C
Sub clock external
Digital I/O slected *2
input selected
GPIO selected
D
Sub osillation circuit
Sub osillation circuit
selected *1
selected
Digital I/O slected *2
GPIO selected
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
OS
OS
OE
OE
OE
OS
OS
OS
-
-
IE/IS
IE/IS
IE/IS
IS
IS
IS
-
-
PC
HC
IS
HS
IS
HS
OS
OS
OE
OE
OE
OS
OS
OS
-
-
PC
HC
IS
GS
IS
GS
OS
OE
OE
OE
OE
OE
OE
OE
-
-
IE/IS
IE/IS
IE/IS
IS
IS
IS
-
-
PC
HC
IS
HS
IS
HS
OS
OE
OE
OE
OE
OE
OE
OE
-
-
PC
HC
IS
HS
IS
HS
This pin is digital input pin, pull up register is on, and digital
E
Digital I/O slected
INITX input
F
Digital I/O slected
MD0 input
USB I/O selected *7
USB port selected
-
-
UE
US
US
US
US
US
Digital I/O slected *6
GPIO selected
IS
IE
CP
HC
IS
HS
IS
HS
PC
IP
IP
IP
IP
IP
G
H
I
Digital I/O slected
Digital I/O slected
-
-
PC
HC
IS
HS
IS
HS
NMI selected
-
-
IP
IP
IP
-
-
-
-
-
IP
IP
IP
IP
IP
IP
IS
IE
PC
HC
IS
-
-
-
WKUP0 enable and
input selected
Analog input
selected
Exterrnal interrupt enable
and input selected
GPIO selected
Resource other than
above selected
CEC pin selected
WKUP enable and
input selected
I2CSLAVE enable selected
K
Digital I/O slected
IP
GPIO selected
input selected
Digital I/O slected *4
input is not shut off in all CPU state..
IS
WKUP enable and
J
This pin is digital input pin, pull up register is none, digital
SW selected
GPIO selected
Analog input selected *3
input is not shut off in all CPU state..
Exterrnal interrupt enable
and input selected
GPIO selected
Resource other than
above selected
Document Number: 002-00233 Rev.*B
*5
Analog input is enalbe in all CPU state
-
-
IP
IP
IP
IP
IP
IP
-
-
IP
IP
IP
GS
IS
GS
-
-
PC
HC
IS
HS
IS
HS
-
-
PC
HC
IS
GS
IS
GS
-
-
CP
CP
CP
CP
CP
CP
-
-
IP
IP
IP
IP
IP
IP
-
-
PC
HC
IP
GS
IS
GS
-
-
PC
HC
IP
GS
IS
GS
IS
IE
PC
HC
IS
HS
IS
HS
-
-
PC
HC
IS
GS
IS
GS
Page 44 of 107
S6E1C3 Series
Each term in above table have the following meanings.
Type
This indicates a pin status type that is shown in “pin list table” in “4. List of Pin Functions”
Selected Pin function
This indicates a pin function that is selected by user program.
CPU state
This indicates a state of the CPU that is shown below.
(1)
Reset state. CPU is initialized by Power-on reset or a reset due to low Power voltage supply.
(2)
Reset state. CPU is initialized by INITX input signal or system initialization after power on reset.
(3)
Run mode or SLEEP mode state.
(4)
(5)
(6)
(7)
(8)
Timer mode, RTC mode or STOP mode state.
The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "0".
Timer mode, RTC mode or STOP mode state.
The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "1".
Deep standby STOP mode or Deep standby RTC mode state,
The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "0"
Deep standby STOP mode or Deep standby RTC mode state,
The standby pin level setting bit (SPL) in the Standby Mode Control Register (STB_CTL) is set to "1"
Run mode state after returning from Deep Standby mode.
(I/O state hold function(CONTX) is fixed at 1)
Document Number: 002-00233 Rev.*B
Page 45 of 107
S6E1C3 Series
Each pin status
The meaning of the symbols in the pin status table is as follows.
IS
Digital output is disabled. (Hi-Z) Pull up register is off. Digital input is shut off by fixed 0.
IE
Digital output is disabled. (Hi-Z) Pull up register is off. Digital input is not shut off.
IP
Digital output is disabled. (Hi-Z) Pull up register is defined by the value of the PCR register. Digital
input is not shut off.
IE/IS
Digital output is disabled. (Hi-Z) Pull up register is off. Digital input is shut off in case of the OSC
stop. Digital input is not shut off in case of the OSC operation.
OE
The OSC is in operation state. However, it may be stopped in some operation mode of the CPU.
For detail, see chapter “Low Power Consumption Mode” in peripheral manual.
OS
The OSC is in stop state. (Hi-Z)
UE
USB I/O function is controlled by USB controller.
US
USB I/O function is disabled(Hi-Z)
PC
Digital output and pull up register is controlled by the register in the GPIO or peripheral function.
Digital input is not shut off
CP
Digital output is controlled by the register in the GPIO or peripheral function. Pull up register is off．
Digital input is not shut off.
HC
Digital output and pull up register is maintained the status that is immediately prior to entering the
current CPU state. Digital input is not shut off
HS
Digital output and pull up register is maintained the status that is immediately prior to entering the
current CPU state. Digital input is shut off
GS
Digital output and pull up register is copied the GPIO status that is immediately prior to entering the
current CPU state and the status is maintained. Digital input is shut off
Additional note
Additional note is described below.
*1
In this type, when internal oscillation function is selected, digital output is disabled. (Hi-Z) pull up
register is off, digital input is shut off by fixed 0.
*2
In this type, when Digital I/O function is selected, internal oscillation function is disabled.
*3
In this type, when analog input function is selected, digital output is disabled, (Hi-Z). pull up register
is off, digital input is shut off by fixed 0.
*4
In this type, when Digital I/O function is selected, analog input function is not available.
*5
In this case, PCR register is initialized to “1”. Pull up register is on.
*6
*7
In this type, when Digital I/O function is selected, USB I/O function is disabled.
This pin does not have pull up register.
In this type, when USB I/O function is selected, digital output is disabled. (Hi-Z), digital input is shut
off by fixed 0.
Document Number: 002-00233 Rev.*B
Page 46 of 107
S6E1C3 Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage* *
1, 3
Analog reference voltage* *
1, 2
VCC
AVRH
1
VI
Input voltage*
1
Analog pin input voltage*
1
Output voltage*
Min
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
VIA
VSS - 0.5
VO
VSS - 0.5
4
L level maximum output current*
IOL
5
L level average output current*
IOLAV
L level total maximum output current
∑IOL
6
L level total average output current*
∑IOLAV
4
H level maximum output current*
IOH
5
H level average output current*
IOHAV
H level total maximum output current
∑IOH
6
H level total average output current*
∑IOHAV
Power consumption
PD
Storage temperature
TSTG
*1: These parameters are based on the condition that VSS= 0 V.
Rating
- 55
Max
VSS + 4.6
VSS + 4.6
VCC + 0.5
(≤ 4.6 V)
VSS + 6.5
VCC + 0.5
(≤ 4.6 V)
Vcc + 0.5
(≤ 4.6 V)
10
4
100
50
- 10
-4
- 100
- 50
200
+ 150
Unit
Remarks
V
V
V
V
5 V tolerant
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
4 mA type
4 mA type
4 mA type
4 mA type
*2: VCC must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not to exceed VCC + 0.5 V at power-on.
*4: The maximum output current is the peak value for a single pin.
*5: The average output is the average current for a single pin over a period of 100 ms.
*6: The total average output current is the average current for all pins over a period of 100 ms.
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
−
Document Number: 002-00233 Rev.*B
Page 47 of 107
S6E1C3 Series
11.2 Recommended Operating Conditions
(VSS= 0.0 V)
Parameter
Power supply voltage
Analog reference voltage
Symbol
Conditions
VCC
-
AVRH
-
Min
3
1.65 *
Value
3.0
2.7
VCC
AVRL
VSS
Smoothing capacitor
CS
1
Operating temperature
Ta
- 40
*1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
Max
3.6
Unit
Remarks
V
3.6
V
*1
VCC
V
VCC ≥ 2.7 V
VCC
VSS
10
+ 105
V
V
μF
°C
VCC < 2.7 V
2
For regulator*
*2: See "C Pin" in "7. Handling Devices" for the connection of the smoothing capacitor.
*3: In between less than the minimum power supply voltage reset / interrupt detection voltage or more, instruction execution and low
voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate
only.
<WARNING>
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated within these ranges.
2.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure.
3.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
4.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-00233 Rev.*B
Page 48 of 107
S6E1C3 Series
11.3 DC Characteristics
11.3.1 Current Rating
Symbol
*8
Run mode,
code executed
from Flash
Run mode,
Icc
(VCC)
code executed
from RAM
Run mode,
code executed
from Flash
Run mode,
code executed
from Flash
Iccs
(VCC)
Sleep
operation
Value
HCLK
Conditions
(Pin Name)
8 MHz external clock input, PLL ON
NOP code executed
Built-in high speed CR stopped
All peripheral clock stopped by CKENx
8 MHz external clock input, PLL ON*8
Benchmark code executed
Built-in high speed CR stopped
PCLK1 stopped
8 MHz crystal oscillation, PLL ON*8
NOP code executed
Built-in high speed CR stopped
All peripheral clock stopped by CKENx
8 MHz external clock input, PLL ON*8
NOP code executed
Built-in high speed CR stopped
All peripheral clock stopped by CKENx
8 MHz external clock input, PLL ON
NOP code executed
Built-in high speed CR stopped
PCLK1 stopped
Built-in high speed CR*5
NOP code executed
All peripheral clock stopped by CKENx
32 kHz crystal oscillation
NOP code executed
All peripheral clock stopped by CKENx
Built-in low speed CR
NOP code executed
All peripheral clock stopped by CKENx
Frequency*4
8 MHZ
Typ*1
Max*2
1.4
2.7
20 MHZ
2.6
4.1
40 MHZ
3.9
5.6
8 MHZ
1.3
2.6
20 MHZ
2.3
3.8
40 MHZ
3.4
5.1
Unit
Remarks
mA
*3
mA
*3
mA
*3, *9
mA
*3
8 MHZ
1.6
3.0
20 MHZ
2.8
4.4
40 MHZ
4.1
5.9
8 MHZ
1.0
1.7
2.1
20 MHZ
40 MHZ
2.7
4.0
40 MHZ
1.6
3.1
mA
*3,*6,*7
8 MHZ
1.1
2.4
mA
*3
32 kHZ
240
1264
μA
*3
100 kHZ
246
1271
μA
*3
8 MHZ
mA
*3
2.9
8 MHz external clock input, PLL ON*8
All peripheral clock stopped by CKENx
0.8
1.3
1.9
20 MHZ
40 MHZ
1.8
3.0
Built-in high speed CR*5
All peripheral clock stopped by CKENx
8 MHZ
0.6
1.7
mA
*3
32 kHz crystal oscillation
All peripheral clock stopped by CKENx
32 kHZ
237
1261
μA
*3
Built-in low speed CR
All peripheral clock stopped by CKENx
100 kHZ
238
1262
μA
*3
2.4
*1 : TA=+25°C,VCC=3.3 V
*2 : TA=+105°C,VCC=3.6 V
*3 : All ports are fixed
*4 : PCLK0 is set to divided rate 8
*5 : The frequency is set to 8 MHz by trimming
*6 : Flash sync down is set to FRWTR.RWT=111 and FSYNDN.SD=1111
*7 : VCC=1.65 V
*8 : When HCLK=8 MHz, PLL OFF
*9 : When IMAINSEL bit(MOSC_CTL:IMAINSEL) is “10” (default).
Document Number: 002-00233 Rev.*B
Page 49 of 107
S6E1C3 Series
Parameter
Symbol
(Pin
Name)
Conditions
ICCH
(VCC)
Power
supply
current
ICCT
(VCC)
Stop mode
Sub timer mode
ICCR
(VCC)
RTC mode
Value
Unit
Remarks
Typ
Max
Ta=25℃
Vcc=3.3 V
12.4
52.4
μA
*1, *2
Ta=25℃
Vcc=1.65 V
12.0
52.0
μA
*1, *2
Ta= 105℃
Vcc=3.6 V
-
597
μA
*1, *2
15.6
55.6
μA
*1, *2
15.0
55.0
μA
*1, *2
-
601
μA
*1, *2
13.2
53.2
μA
*1, *2
12.7
52.7
μA
*1, *2
-
598
μA
*1, *2
Ta=25℃
Vcc=3.3 V
32 kHz Crystal
oscillation
Ta=25℃
Vcc=1.65 V
32 kHz Crystal
oscillation
Ta= 105℃
Vcc=3.6 V
32 kHz Crystal
oscillation
Ta=25℃
Vcc=3.3 V
32 kHz Crystal
oscillation
Ta=25℃
Vcc=1.65 V
32 kHz Crystal
oscillation
Ta= 105℃
Vcc=3.6 V
32 kHz Crystal
oscillation
*1: All ports are fixed. LVD off. Flash off.
*2: When CALDONE bit(CAL_CTL:CALDONE) is “1”. In case of “0”, Bipolar Vref current is added.
Document Number: 002-00233 Rev.*B
Page 50 of 107
S6E1C3 Series
Parameter
Symbol
(Pin
Name)
RAM off
ICCHD
(VCC)
Deep standby
Stop mode
RAM on
Power
supply
current
RAM off
ICCRD
(VCC)
Value
Conditions
Deep standby
RTC mode
RAM on
Ta=25°C
Vcc=3.3 V
Ta=25°C
Vcc=1.65 V
Ta= 105°C
Vcc=3.6 V
Ta=25°C
Vcc=3.3 V
Ta=25°C
Vcc=1.65 V
Ta= 105°C
Vcc=3.6 V
Ta=25°C
Vcc=3.3 V
Ta=25°C
Vcc=1.65 V
Ta= 105°C
Vcc=3.6 V
Ta=25°C
Vcc=3.3 V
Ta=25°C
Vcc=1.65 V
Ta= 105°C
Vcc=3.6 V
Unit
Remarks
1.85
μA
*1, *2
0.56
1.83
μA
*1, *2
-
46
μA
*1, *2
0.78
6.6
μA
*1, *2
0.76
6.6
μA
*1, *2
-
88
μA
*1, *2
1.16
2.4
μA
*1, *2
1.15
2.4
μA
*1, *2
-
46
μA
*1, *2
1.37
7.2
μA
*1, *2
1.35
7.2
μA
*1, *2
-
88
μA
*1, *2
Typ
Max
0.58
*1: All ports are fixed. LVD off.
*2: When CALDONE bit(CAL_CTL:CALDONE) is “1”. In case of “0”, Bipolar Vref current is added.
Document Number: 002-00233 Rev.*B
Page 51 of 107
S6E1C3 Series
LVD Current
Parameter
Low-Voltage
detection circuit
(LVD) power
supply current
(VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
ICCLVD
Pin
Name
Conditions
VCC
At operation
Typ
0.15
0.10
Bipolar Vref Current
Parameter
Bipolar Vref
Current
Flash
memory
write/erase
current
Max
0.3
0.3
Unit
Symbol
Pin
Name
Conditions
ICCBGR
VCC
At operation
Typ
Value
100
μA
For occurrence of reset
μA
For occurrence of
interrupt
Max
200
Unit
Symbol
Conditions
ICCFLASH
VCC
At Write/Erase
μA
Typ
Value
4.4
Max
5.6
Unit
Remarks
mA
(VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Value
Symbol
Conditions
Power supply
current
Pin
Name
ICCAD
VCC
At operation
0.5
0.75
mA
Reference
power supply
current
(AVRH)
At operation
0.69
1.3
mA
ICCAVRH
AVRH
At stop
0.1
1.3
μA
Document Number: 002-00233 Rev.*B
Remarks
(VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Pin
Name
A/D converter Current
Parameter
Remarks
(VCC=1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Flash Memory Current
Parameter
Value
Typ
Max
Unit
Remarks
AVRH=3.6 V
Page 52 of 107
S6E1C3 Series
Peripheral Current Dissipation
Clock
System
HCLK
PCLK1
(VCC=1.65 V to 3.6 V, VSS=0 V, TA=- 40°C to +105°C)
Frequency (MHz)
20
Peripheral
Conditions
GPIO
At all ports
operation
0.05
0.12
0.23
DSTC
At 2ch
operation
0.02
0.06
0.10
USB
At 1ch
operation
0.13
0.13
0.13
Base timer
At 4ch
operation
0.02
0.05
0.10
ADC
At 1 unit
operation
0.04
0.10
0.21
Multi-function serial
At 1ch
operation
0.01
0.03
0.06
MFS-I2S
At 1ch
operation
0.02
0.05
0.08
Smart Card I/F
At 1ch
operation
0.04
0.08
0.18
*1 USB itself uses 48MHz clock
Document Number: 002-00233 Rev.*B
8
40
Unit
Remarks
mA
mA
*1
mA
Page 53 of 107
S6E1C3 Series
11.3.2 Pin Characteristics
Parameter
H level input
voltage
(hysteresis
input)
L level input
voltage
(hysteresis
input)
H level
output voltage
L level
output voltage
Input leak
current
Pull-up
resistance
value
Input
capacitance
(VCC = 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Value
Typ
Max
-
VCC +0.3
V
VCC × 0.8
VCC × 0.7
-
VSS +5.5
V
VSS - 0.3
-
Symbol
Pin Name
Conditions
VCC ≥ 2.7 V
VIHS
CMOS
hysteresis
input pin,
MD0
VCC < 2.7 V
VCC × 0.7
5 V tolerant
input pin
VCC ≥ 2.7 V
VCC < 2.7 V
CMOS
hysteresis
input pin,
MD0
VCC ≥ 2.7 V
VILS
5 V tolerant
input pin
VOH
4 mA type
Min
VCC < 2.7 V
VCC × 0.2
V
VCC × 0.3
VSS - 0.3
-
VCC × 0.2
-
VCC × 0.3
-
VCC
V
V
VCC ≥ 2.7 V,
IOH = - 4 mA
VCC - 0.5
VCC < 2.7 V,
IOH = - 2 mA
VCC - 0.45
VSS
-
0.4
V
μA
VOL
4 mA type
VCC ≥ 2.7 V,
IOL 4 mA
VCC < 2.7 V,
IOL=2 mA
IIL
-
-
-5
-
+5
RPU
Pull-up pin
VCC ≥ 2.7 V
21
33
48
VCC < 2.7 V
-
-
88
CIN
Other than
VCC, VSS,
AVRH
-
-
5
15
Document Number: 002-00233 Rev.*B
Remarks
VCC × 0.8
VCC < 2.7 V
VCC ≥ 2.7 V
Unit
kΩ
pF
Page 54 of 107
S6E1C3 Series
11.4 AC Characteristics
11.4.1 Main Clock Input Characteristics
Parameter
Symbol
Input frequency
FCH
Input clock cycle
tCYLH
Input clock pulse
width
Input clock rising
time and falling time
Internal operating
*1
clock frequency
Pin
name
X0,
X1
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Conditions
Value
Unit
Remarks
Min
Max
VCC ≥ 2.7V
VCC < 2.7V
8
8
48
20
MHz
When the crystal
oscillator is connected
-
8
48
MHz
When the external
clock is used
-
20.83
125
ns
PWH/tCYLH,
PWL/tCYLH
45
55
%
-
-
5
ns
tCF,
tCR
FCM
-
-
-
40.8
MHz
When the external
clock is used
When the external
clock is used
When the external
clock is used
Master clock
FCC
FCP0
FCP1
-
-
-
40.8
40.8
40.8
MHz
MHz
MHz
Base clock (HCLK/FCLK)
2
APB0 bus clock*
2
APB1 bus clock*
tCYCCM
tCYCC
tCYCP0
tCYCP1
-
-
24.5
-
ns
-
Master clock
24.5
ns
Base clock (HCLK/FCLK)
Internal operating
*1
2
clock cycle time
24.5
ns
APB0 bus clock*
2
24.5
ns
APB1 bus clock*
*1: For details of each internal operating clock, refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual".
*2: For details of the APB bus to which a peripheral is connected, see "8. Block Diagram".
tCYLH
X0
0.8 × Vcc
0.8 × Vcc
0.2 × Vcc
PWH
PWL
tCF
Document Number: 002-00233 Rev.*B
0.8 × Vcc
0.2 × Vcc
tCR
Page 55 of 107
S6E1C3 Series
11.4.2 Sub Clock Input Characteristics
Parameter
Input frequency
Input clock cycle
Symbol
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Pin
Name
fCL
tCYLL
X0A,
X1A
Conditions
Value
Unit
Min
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
-
10
-
31.25
μs
55
%
Input clock pulse
PWH/tCYLL,
45
width
PWL/tCYLL
*: See "Sub crystal oscillator" in "7. Handling Devices" for the crystal oscillator used.
Remarks
When the crystal
oscillator is
connected
When the external
clock is used
When the external
clock is used
When the external
clock is used
tCYLL
0.8 × Vcc
0.8 × Vcc
0.2 × Vcc
X0A
PWH
Document Number: 002-00233 Rev.*B
0.8 × Vcc
0.2 × Vcc
PWL
Page 56 of 107
S6E1C3 Series
11.4.3 Built-in CR Oscillation Characteristics
Built-in High-Speed CR
Parameter
(VCC= 1.65 V to 3.6 V, VSS = 0 V, TA=- 40°C to +105°C)
Symbol
Clock frequency
Value
Conditions
Unit
Min
Typ
Max
Ta = - 10°C to + 105°C,
7.92
8
8.08
MHz
Ta = - 40°C to + 105°C,
7.84
8
8.16
MHz
FCRH
Remarks
After trimming *1
Frequency
tCRWT
300
μs
stabilization time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency
trimming/temperature trimming.
*2
*2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock.
After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source
clock.
Built-in Low-Speed CR
Parameter
Clock frequency
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Conditions
fCRL
-
Document Number: 002-00233 Rev.*B
Value
Min
Typ
Max
50
100
150
Unit
Remarks
kHz
Page 57 of 107
S6E1C3 Series
11.4.4 Operating Conditions of Main PLL
(In the Case of Using the Main Clock as the Input Clock of the PLL)
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Parameter
Symbol
1
PLL oscillation stabilization wait time*
(LOCK UP time)
tLOCK
Value
Unit
Min
Typ
Max
50
-
-
μs
-
16
18
150
40
48
MHz
multiple
MHz
MHz
MHz
PLL input clock frequency
FPLLI
8
PLL multiple rate
5
PLL macro oscillation clock frequency
FPLLO
75
2
Main PLL clock frequency*
FCLKPLL
3
USB clock frequency*
FCLKSPLL
*1: The wait time is the time it takes for PLL oscillation to stabilize.
Remarks
*2: For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual".
*3: For more information about USB clock, see "Chapter: USB Clock Generation" in "FM0+ Family Peripheral Manual
Communication Macro Part”.
Main PLL connection
Main clock (CLKMO)
K
divider
High-speed CR clock (CLKHC)
PLL input
clock
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
USB
clock
divider
USB clock
11.4.5 Operating Conditions of Main PLL
(In the Case of Using the Built-in High-Speed CR Clock as the Input Clock of the Main PLL)
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Parameter
Symbol
1
PLL oscillation stabilization wait time*
(LOCK UP time)
tLOCK
Value
Unit
Min
Typ
Max
50
-
-
μs
8
-
8.16
18
150
40.8
MHz
multiple
MHz
MHz
PLL input clock frequency
FPLLI
7.84
PLL multiple rate
9
PLL macro oscillation clock frequency
FPLLO
75
2
Main PLL clock frequency*
FCLKPLL
*1: The wait time is the time it takes for PLL oscillation to stabilize.
Remarks
*2: For details of the main PLL clock (CLKPLL), refer to "Chapter: Clock" in "FM0+ Family Peripheral Manual".
Note:
Document Number: 002-00233 Rev.*B
Page 58 of 107
S6E1C3 Series
−
For the main PLL source clock, input the high-speed CR clock (CLKHC) whose frequency and temperature have been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
11.4.6 Reset Input Characteristics
Parameter
(VCC = 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Pin
Name
Conditions
tINITX
INITX
-
Reset input time
11.4.7 Power-on Reset Timing
Parameter
Value
Min
Max
500
-
Unit
Remarks
ns
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Power supply rising time
tVCCR
Power supply shut down time
Time until releasing
Power-on reset
tOFF
Pin
Name
VCC
tPRT
Value
Unit
Min
Max
0
-
ms
1
-
ms
0.43
3.4
ms
Remarks
VCC < 0.2V
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
tVCCR
tOFF
tPRT
Internal reset
CPU Operation
Reset active
0.2V
Release
start
Glossary
VCC_minimum : Minimum VCC of recommended operating conditions.
VDH_minimum : Minimum detection voltage of Low-Voltage detection reset.
See "11.7 Low-Voltage Detection Characteristics".
Document Number: 002-00233 Rev.*B
Page 59 of 107
S6E1C3 Series
11.4.8 Base Timer Input Timing
Timer Input Timing
Parameter
Input pulse width
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Pin Name
Conditions
tTIWH, tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
Min
Value
2 tCYCP
Max
-
Unit
Remarks
ns
tTIWL
tTIWH
ECK
VIHS
VIHS
TIN
VILS
VILS
Trigger Input Timing
Parameter
Input pulse width
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Pin Name
Conditions
tTRGH, tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
VIHS
Value
2 tCYCP
Max
-
Unit
Remarks
ns
tTRGL
tTRGH
TGIN
Min
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
For the number of the APB bus to which the Base Timer has been connected, see "8. Block Diagram".
Document Number: 002-00233 Rev.*B
Page 60 of 107
S6E1C3 Series
11.4.9 CSIO/SPI/UART Timing
CSIO (SPI=0, SCINV=0)
Parameter
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
Pin
name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
Conditions
VCC < 2.7 V
Min
Max
4 tCYCP
-
VCC ≥ 2.7 V
Min
Max
4 tCYCP
-
Unit
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
SCKx
2 tCYCP 10
-
-
ns
SCKx
tCYCP + 10
-
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Master mode
Slave mode
2 tCYCP 10
tCYCP +
10
Notes:
−
The above AC characteristics are for clock synchronous mode.
−
tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram".
−
The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
−
External load capacitance CL=30 pF
Document Number: 002-00233 Rev.*B
Page 61 of 107
S6E1C3 Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
SOT
VOL
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
Master mode
tSLSH
SCK
VIH
tF
tSHSL
VIL
VIL
tSLOVE
SOT
VIH
tR
VOH
VOL
tIVSHE
SIN
VIH
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-00233 Rev.*B
Page 62 of 107
S6E1C3 Series
CSIO (SPI=0, SCINV=1)
Parameter
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Pin
name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCK falling time
SCK rising time
tF
tR
Conditions
Master mode
VCC < 2.7V
Min
Max
4 tCYCP
-
Unit
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
-
ns
-
ns
2 tCYCP 10
tCYCP + 10
Slave mode
VCC ≥ 2.7V
Min
Max
4 tCYCP
-
-
2 tCYCP 10
tCYCP + 10
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
-
Notes:
−
The above AC characteristics are for clock synchronous mode.
−
tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram".
−
The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
−
External load capacitance CL=30 pF
Document Number: 002-00233 Rev.*B
Page 63 of 107
S6E1C3 Series
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
SOT
VOL
tIVSLI
VIH
SIN
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
tF
tSHOVE
SOT
VOH
VOL
tIVSLE
SIN
VIL
VIL
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-00233 Rev.*B
Page 64 of 107
S6E1C3 Series
SPI (SPI=1, SCINV=0)
Parameter
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Pin
name
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCK falling time
SCK rising time
tF
tR
Conditions
Master mode
VCC < 2.7 V
Min
Max
4 tCYCP
-
Unit
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
2 tCYCP 30
2 tCYCP 10
tCYCP + 10
Slave mode
VCC ≥ 2.7 V
Min
Max
4 tCYCP
-
-
2 tCYCP 30
2 tCYCP 10
tCYCP + 10
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
-
Notes:
−
The above AC characteristics are for clock synchronous mode.
−
tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram".
−
The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
−
External load capacitance CL=30 pF
Document Number: 002-00233 Rev.*B
Page 65 of 107
S6E1C3 Series
tSCYC
SCK
tSOVLI
SOT
VOH
VOL
VOH
VOL
VOH
VOL
VIH
VIL
SIN
VOL
tSHOVI
tIVSLI
tSLIXI
VIH
VIL
Master mode
tSLSH
VIH
SCK
*
SOT
VIL
tSHSL
VIL
tF
tR
VOH
VOL
SIN
VIH
VIL
tIVSLE
*: Changes when writing to TDR register
Document Number: 002-00233 Rev.*B
tSLIXE
VIH
VIH
tSHOVE
VOH
VOL
VIH
VIL
Slave mode
Page 66 of 107
S6E1C3 Series
SPI (SPI=1, SCINV=1)
Parameter
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Pin
name
SCKx
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCK falling time
SCK rising time
tF
tR
Conditions
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
Master mode
VCC < 2.7 V
Min
Max
4 tCYCP
-
Unit
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
2 tCYCP 30
2 tCYCP 10
tCYCP + 10
Slave mode
VCC ≥ 2.7 V
Min
Max
4 tCYCP
-
-
2 tCYCP 30
2 tCYCP 10
tCYCP + 10
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
-
Notes:
−
The above AC characteristics are for clock synchronous mode.
−
tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram".
−
The characteristics are only applicable when the relocate port numbers are the same.
For instance, they are not applicable for the combination of SCKx_0 and SOTx_1.
−
External load capacitance CL=30 pF
Document Number: 002-00233 Rev.*B
Page 67 of 107
S6E1C3 Series
tSCYC
VOH
SCK
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tR
SCK
SOT
VIL
VIH
VIH
tSLSH
VIL
tSLOVE
VOH
VOL
tIVSHE
SIN
tF
tSHSL
VIL
VOH
VOL
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-00233 Rev.*B
Page 68 of 107
S6E1C3 Series
When Using CSIO/SPI Chip Select (SCINV=0, CSLVL=1)
Parameter
Symbol
Conditions
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
VCC < 2.7 V
Min
VCC ≥ 2.7 V
Max
Unit
Max
Min
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
(*3)+50
(*3)-50
(*3)+50
ns
SCS↓→SCK↓ setup time
tCSSI
SCK↑→SCS↑ hold time
tCSHI
SCS deselect time
tCSDI
(*3)-50
SCS↓→SCK↓ setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↑→SCS↑ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↓→SOT delay time
tDSE
-
55
-
40
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
Master mode
Slave mode
*1: CSSU bit value × serial chip select timing operating clock cycle.
*2: CSHD bit value × serial chip select timing operating clock cycle.
*3: CSDS bit value × serial chip select timing operating clock cycle.
Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes
inactive to the time when the serial chip select pin becomes active again.
Notes:
−
tCYCP indicates the APB bus clock cycle time.
For information about the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram".
−
−
For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual".
−
When the external load capacitance CL=30 pF.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed.
Document Number: 002-00233 Rev.*B
Page 69 of 107
S6E1C3 Series
SCSO
tCSSI
tCSHI
tCSDI
tCSHE
tCSDE
SCK
SOT
(SPI=0)
SOT
(SPI=1)
Master mode
SCSI
tCSSE
SCK
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
Slave mode
Document Number: 002-00233 Rev.*B
Page 70 of 107
S6E1C3 Series
When Using CSIO/SPI Chip Select (SCINV=1, CSLVL=1)
Parameter
Symbol
SCS↓→SCK↑ setup time
tCSSI
SCK↓→SCS↑ hold time
tCSHI
Conditions
Master mode
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
VCC < 2.7 V
VCC ≥ 2.7 V
Unit
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
ns
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50
(*3)+50
(*3)-50
(*3)+50
ns
SCS↓→SCK↑ setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↓→SCS↑ hold time
tCSHE
0
-
0
-
ns
SCS deselect time
tCSDE
3tCYCP+30
-
3tCYCP+30
-
ns
SCS↓→SOT delay time
tDSE
-
55
-
40
ns
SCS↑→SOT delay time
tDEE
0
-
0
-
ns
Slave mode
*1: CSSU bit value × serial chip select timing operating clock cycle.
*2: CSHD bit value × serial chip select timing operating clock cycle.
*3: CSDS bit value × serial chip select timing operating clock cycle.
Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes
inactive to the time when the serial chip select pin becomes active again.
Notes:
−
tCYCP indicates the APB bus clock cycle time.
For information about the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram".
−
−
For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual".
−
When the external load capacitance CL=30 pF.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed.
Document Number: 002-00233 Rev.*B
Page 71 of 107
S6E1C3 Series
SCSO
tCSSI
tCSHI
tCSDI
tCSHE
tCSDE
SCK
SOT
(SPI=0)
SOT
(SPI=1)
Master mode
SCSI
tCSSE
SCK
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
Slave mode
Document Number: 002-00233 Rev.*B
Page 72 of 107
S6E1C3 Series
When Using CSIO/SPI Chip Select (SCINV=0, CSLVL=0)
Parameter
SCS↑→SCK↓ setup time
Symbol
Conditions
tCSSI
Master mode
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
VCC < 2.7 V
VCC ≥ 2.7 V
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
Unit
ns
SCK↑→SCS↓ hold time
tCSHI
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50
(*3)+50
(*3)-50
(*3)+50
ns
SCS↑→SCK↓ setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↑→SCS↓ hold time
tCSHE
SCS deselect time
tCSDE
SCS↑→SOT delay time
SCS↓→SOT delay time
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
tDSE
-
55
-
40
ns
tDEE
0
-
0
-
ns
Slave mode
*1: CSSU bit value × serial chip select timing operating clock cycle.
*2: CSHD bit value × serial chip select timing operating clock cycle.
*3: CSDS bit value × serial chip select timing operating clock cycle.
Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes
inactive to the time when the serial chip select pin becomes active again.
Notes:
−
tCYCP indicates the APB bus clock cycle time.
For information about the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram".
−
For information About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual".
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed.
−
When the external load capacitance CL=30 pF.
Document Number: 002-00233 Rev.*B
Page 73 of 107
S6E1C3 Series
tCSDI
SCSO
tCSSI
tCSHI
SCK
SOT
(SPI=0)
SOT
(SPI=1)
Master mode
tCSDE
SCSI
tCSSE
tCSHE
SCK
tDEE
SOT
(SPI=0)
SOT
tDSE
(SPI=1)
Slave mode
Document Number: 002-00233 Rev.*B
Page 74 of 107
S6E1C3 Series
When Using CSIO/SPI Chip Select (SCINV=1, CSLVL=0)
Parameter
SCS↑→SCK↑ setup time
Symbol
Conditions
tCSSI
Master mode
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
VCC < 2.7 V
VCC ≥ 2.7 V
Min
Max
Min
Max
(*1)-50
(*1)+0
(*1)-50
(*1)+0
Unit
ns
SCK↓→SCS↓ hold time
tCSHI
(*2)+0
(*2)+50
(*2)+0
(*2)+50
ns
SCS deselect time
tCSDI
(*3)-50
(*3)+50
(*3)-50
(*3)+50
ns
SCS↑→SCK↑ setup time
tCSSE
3tCYCP+30
-
3tCYCP+30
-
ns
SCK↓→SCS↓ hold time
tCSHE
SCS deselect time
tCSDE
SCS↑→SOT delay time
SCS↓→SOT delay time
0
-
0
-
ns
3tCYCP+30
-
3tCYCP+30
-
ns
tDSE
-
55
-
40
ns
tDEE
0
-
0
-
ns
Slave mode
*1: CSSU bit value × serial chip select timing operating clock cycle.
*2: CSHD bit value × serial chip select timing operating clock cycle.
*3: CSDS bit value × serial chip select timing operating clock cycle.
Irrespective of CSDS bit setting, 5tCYCP or more are required for the period the time when the serial chip select pin becomes
inactive to the time when the serial chip select pin becomes active again.
Notes:
−
tCYCP indicates the APB bus clock cycle time.
For information about the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram".
−
For information about CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family Peripheral Manual".
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SCSIx_1 is not guaranteed.
−
When the external load capacitance CL=30 pF.
Document Number: 002-00233 Rev.*B
Page 75 of 107
S6E1C3 Series
tCSDI
SCSO
tCSSI
tCSHI
SCK
SOT
(SPI=0)
SOT
(SPI=1)
Master mode
tCSDE
SCSI
tCSSE
tCSHE
SCK
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
Slave mode
Document Number: 002-00233 Rev.*B
Page 76 of 107
S6E1C3 Series
UART external clock input (EXT=1)
Parameter
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
SCK rising time
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
tSLSH
tSHSL
tF
tR
Document Number: 002-00233 Rev.*B
VIL
Min
tCYCP +10
tCYCP +10
-
CL=30 pF
tR
SCK
Value
Conditions
tF
tSHSL
VIH
VIH
VIL
Max
5
5
Unit
Remarks
ns
ns
ns
ns
tSLSH
VIL
Page 77 of 107
S6E1C3 Series
11.4.10 External Input Timing
Parameter
Input pulse width
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Value
Min
Pin Name
Conditions
ADTGx
-
2 tCYCP*
INT00 to INT08,
INT12, INT13,
INT15, NMIX
*2
WKUPx
1
Max
Unit
-
ns
2 tCYCP +100*
-
ns
*3
500
-
ns
*4
500
-
ns
Remarks
A/D converter
trigger input
tINH, tINL
1
External
interrupt, NMI
Deep standby
wake up
*1: tCYCP represents the APB bus clock cycle time.
For the number of the APB bus to which the Multi-function Timer is connected and that of the APB bus to which the External
Interrupt Controller is connected, see "8. Block Diagram".
*2: In Run mode and Sleep mode
*3: In Timer mode, RTC mode and Stop mode
*4: In Deep Standby RTC mode and Deep Standby Stop mode
tINH
VILS
Document Number: 002-00233 Rev.*B
tINL
VILS
VIHS
VIHS
Page 78 of 107
S6E1C3 Series
2
11.4.11 I C Timing / I2C Slave Timing
Parameter
SCL(SI2CSCL) clock frequency
(Repeated) Start condition hold time
SDA(SI2CSDA) ↓ → SCL(SI2CSCL)
↓
SCL(SI2CSCL) clock L width
SCL(SI2CSCL) clock H width
(Repeated) Start setup time
SCL(SI2CSCL) ↑ → SDA
(SI2CSDA) ↓
Data hold time
SCL(SI2CSCL) ↓ → SDA(SI2CSDA)
↓↑
Data setup time
SDA (SI2CSDA)↓ ↑ → SCL
(SI2CSCL)↑
Stop condition setup time
SCL(SI2CSCL) ↑ → SDA(SI2CSDA)
↑
Bus free time between
Stop condition and
Start condition
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbo
l
FSCL
Conditions
Standard-Mode
Min
Max
0
100
Fast-Mode
Min
Max
0
400
Unit
kHz
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
0
3.45*
0
0.9*
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
tHDDAT
CL=30 pF,
1
R=(Vp/IOL)*
2
3
Remarks
except I2C
2
2
ns
4
4
tCYCP*
tCYCP*
Slave
*1: R represents the pull-up resistance of the SCL and SDA lines, and CL the load capacitance of the SCL and SDA lines. VP
represents the power supply voltage of the pull-up resistance, and IOL the VOL guaranteed current.
Noise filter
tSP
-
*2: The maximum tHDDAT must satisfy at least the condition that the period during which the device is holding the SCL signal at L
(tLOW) does not extend.
2
2
*3: A Fast-mode I C bus device can be used in a Standard-mode I C bus system, provided that the condition of tSUDAT ≥ 250 ns is
fulfilled.
*4: tCYCP represents the APB bus clock cycle time.
2
For the number of the APB bus to which the I C is connected, see "8. Block Diagram".
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
tSUDAT
tLOW
tSUSTA
tBUF
SCL
tHDSTA
Document Number: 002-00233 Rev.*B
tHDDAT
tHIGH
tHDSTA
tSP
tSUSTO
Page 79 of 107
S6E1C3 Series
2
11.4.12 I S Timing (MFS-I2S Timing)
Master Mode Timing
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Parameter
MI2SCK max frequency (*1)
2
I S clock cycle time (*1)
2
I S clock Duty cycle
Symbo
l
FMI2SCK
tICYC
∆
MI2SCK↓ → MI2SWS delay
time
tSWDT
MI2SCK↓ → MI2SDO delay
time
tSDDT
MI2SDI → MI2SCK ↑ setup
time
tDSST
MI2SCK ↑ → MI2SDI hold
time
tSDHT
MI2SCK falling time
MI2SCK rising time
tF
tR
Pin
Name
MI2SCKx
MI2SCKx
MI2SCKx
MI2SCKx
,
MI2SWS
x
MI2SCKx
,
MI2SDO
x
MI2SCKx
,
MI2SDIx
MI2SCKx
,
MI2SDIx
MI2SCKx
MI2SCKx
Conditions
CL=30 pF
VCC < 2.7 V
Min
Max
6.144
4 tCYCP
45%
55%
VCC ≥ 2.7 V
Min
Max
6.144
4 tCYCP
45%
55%
Unit
MHz
ns
-30
+30
-20
+20
ns
-30
+30
-20
+20
ns
50
-
36
-
ns
0
-
0
-
ns
-
5
5
-
5
5
ns
ns
*1: I2S clock should meet the multiple of PCLK(tICYC) and the frequency less than FMI2SCK meantime. The detail information please
refer to Chapter I2S of Communication Macro Part of Peripheral Manual.
VIH
MI2SCK
tF
VIH
VIL
VIL
tSWDT,
tSDDT
MI2SWS
and
MI2SDO
MI2SDI
Document Number: 002-00233 Rev.*B
tR
VOH
VOL
tDSST
tSDHT
VIH
VIH
VIL
VIL
Page 80 of 107
S6E1C3 Series
MI2SMCK Input Characteristics
Parameter
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Value
Unit
Symbol
Pin Name
Conditions
Input frequency
fCHS
MI2SMCK
-
-
12.288
MHz
Input clock cycle
tCYLHS
-
81.3
-
ns
-
-
45
55
%
tCFS
tCRS
PWHS/tCYLHS
PWLS/tCYLHS
-
-
-
5
ns
Input clock pulse width
Input clock rise time and
fall time
MI2SMCK Output Characteristics
Parameter
Output frequency
Max
Remarks
When using
external clock
When using
external clock
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Symbol
Pin Name
Conditions
fCHS
MI2SMCK
-
Document Number: 002-00233 Rev.*B
Min
Min
Value
Max
Unit
Remarks
-
25
MHz
VCC ≥ 2.7 V
-
20
MHz
VCC < 2.7 V
Page 81 of 107
S6E1C3 Series
11.4.13 Smart Card Interface Characteristics
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Parameter
Symbol
Output rising time
tR
Output falling time
tF
Output clock frequency
Duty cycle
fCLK
∆
Pin Name
Conditions
ICx_VCC,
ICx_RST,
ICx_CLK,
ICx_DATA
ICx_CLK
CL=30 pF
Value
Unit
Min
Max
4
20
ns
4
20
ns
-
20
MHz
45%
55%
Remarks
External pull-up resistor (20 kΩ to 50 kΩ) must be applied to ICx_CIN pin when it’s used as smart card reader function.
Document Number: 002-00233 Rev.*B
Page 82 of 107
S6E1C3 Series
11.4.14 SW-DP Timing
Parameter
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
Value
Unit
Symbol
Pin Name
Conditions
SWDIO setup time
tSWS
SWCLK,
SWDIO
-
15
-
ns
SWDIO hold time
tSWH
SWCLK,
SWDIO
-
15
-
ns
SWDIO delay time
tSWD
SWCLK,
SWDIO
-
-
45
ns
Min
Max
Remarks
Note:
−
External load capacitance CL=30 pF
SWCLK
VOH
VOL
tJTAGS
VOH
VOL
SWDIO
(When input)
tJTAGH
VOH
VOL
tSWD
JTAGD
SWDIO
(When output)
Document Number: 002-00233 Rev.*B
VOH
VOL
Page 83 of 107
S6E1C3 Series
11.5 12-bit A/D Converter
Electrical Characteristics of A/D Converter (Preliminary Values)
Parameter
ANxx
Min
- 4.5
- 2.5
- 15
Value
Typ
-
Max
12
4.5
+ 2.5
+ 15
ANxx
AVRH - 15
-
AVRH + 15
1.0
-
-
4.0
-
-
10
-
-
0.3
-
1.2
-
3.0
-
1.65 ≤ VCC < 1.8 V
50
-
VCC ≥ 2.7 V
200
-
500
-
Symbol
Pin Name
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
VZT
Full-scale transition voltage
VFST
1
Conversion time*
Sampling time
-
*2
Ts
3
Compare clock cycle *
Tcck
(VCC= 1.65 V to 3.6 V, VSS= 0 V, TA=- 40°C to +105°C)
-
-
-
Unit
bit
LSB
LSB
mV
mV
VCC ≥ 2.7 V
μs
1.8 ≤ VCC < 2.7 V
1.65 ≤ VCC < 1.8 V
VCC ≥ 2.7 V
10
1000
μs
ns
1.8 ≤ VCC < 2.7 V
1.8 ≤ VCC < 2.7 V
1.65 ≤ VCC < 1.8 V
State transition time to
operation permission
Analog input capacity
Tstt
-
-
-
1.0
μs
CAIN
-
-
-
pF
Analog input resistance
RAIN
-
-
-
-
-
-
-
7.5
2.2
5.5
10.5
4
LSB
-
ANxx
-
-
5
μA
-
ANxx
Interchannel disparity
Analog port input leak
current
Analog input voltage
Remarks
kΩ
VCC ≥ 2.7 V
1.8 ≤ VCC < 2.7 V
1.65 ≤ VCC < 1.8 V
VSS
AVRH
V
2.7
VCC ≥ 2.7V
VCC
V
AVRH
Reference voltage
VCC
VCC < 2.7V
AVRL
VSS
VSS
V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The minimum conversion time is computed according to the following conditions:
sampling time=0.3 μs, compare time=0.7 μs
VCC ≥ 2.7 V
sampling time=1.2 μs, compare time=2.8 μs
1.8 ≤ VCC < 2.7 V
sampling time=3.0 μs, compare time=7.0 μs
1.65 ≤ VCC < 1.8 V
Ensure that the conversion time satisfies the specifications of the sampling time (tS) and compare clock cycle (tCCK).
For details of the settings of the sampling time and compare clock cycle, refer to "Chapter: A/D Converter" in "FM0+ Family
Peripheral Manual Analog Macro Part".
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see "8. Block Diagram".
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: The required sampling time varies according to the external impedance.
Set a sampling time that satisfies (Equation 1).
*3: The compare time (tC) is the result of (Equation 2).
Document Number: 002-00233 Rev.*B
Page 84 of 107
S6E1C3 Series
ANxx
Analog input pins
Analog signal
source
REXT
Comparator
RAIN
CAIN
(Equation 1) tS ≥ (RAIN + REXT ) × CAIN × 9
tS:
Sampling time
RAIN:
Input resistance of A/D Converter = 2.2 kΩ with 2.7 < VCC < 3.6
Input resistance of A/D Converter = 5.5 kΩ with 1.8 < VCC < 2.7
Input resistance of A/D Converter = 10.5 kΩ with 1.65 < VCC < 1.8
CAIN:
REXT:
Input capacitance of A/D Converter = 7.5 pF with 1.65 < VCC < 3.6
Output impedance of external circuit
(Equation 2) tC=tCCK × 14
tC:
Compare time
tCCK :
Compare clock cycle
Document Number: 002-00233 Rev.*B
Page 85 of 107
S6E1C3 Series
Definitions of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity:
Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the
full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.
Integral Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
0x(N+1)
{1 LSB(N-1) + VZT}
0xFFD
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
Differential Nonlinearity
0x001
Analog input
:
:
:
:
(Actually-measured
value)
0x(N-2)
AVRH
Differential Nonlinearity of digital output N =
N
VZT
VFST
VNT
(Actually-measured
value)
Actual conversion characteristics
Integral Nonlinearity of digital output N =
1LSB =
V(N+1)T
VNT
VZT (Actually-measured value)
VSS
Ideal characteristics
0x(N-1)
Actual conversion
characteristics
Ideal characteristics
0x002
0xN
Actual conversion
characteristics
VSS
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST – VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-00233 Rev.*B
Page 86 of 107
S6E1C3 Series
11.6 USB Characteristics
(VCC=3.0 V to 3.6 V, VSS=0 V, TA=- 40°C to +105°C)
Parameter
Input
characteristics
Symbol
Pin
Name
Conditions
Input H level voltage
VIH
-
Input L level voltage
VIL
-
Differential input sensitivity
VDI
-
Differential common mode range
VCM
-
Value
Min
2.0
VSS –
VCC +
0.3
Unit
V
Remarks
*1
*1
0.8
V
0.2
-
V
*2
0.8
2.5
V
*2
2.8
3.6
V
0.0
0.3
V
0.3
External pull-down
Max
*3
Output H level voltage
VOH
Output L level voltage
VOL
Crossover voltage
VCRS
-
1.3
2.0
V
*4
resistance = 15 kΩ
UDP0,
External pull-up
UDM0
resistance = 1.5 kΩ
*3
Output
Rising time
tFR
Full-speed
4
20
ns
*5
characteristic
Falling time
tFF
Full-speed
4
20
ns
*5
Rising/Falling time matching
tFRFM
Full-speed
90
111.11
%
*5
Output impedance
ZDRV
Full-speed
28
44
Ω
*6
tLR
Low-speed
75
300
ns
*7
tLF
Low-speed
75
300
ns
*7
tLRFM
Low-speed
80
125
%
*7
Rising time
Falling time
Rising/Falling time matching
*1 :
Minimum differential input sensitivity [V]
*2 :
The switching threshold voltage of single-end-receiver of USB I/O buffer is set as within VIL(Max)=0.8 V, VIH(Min)=2.0 V
(TTL input standard).
There are some hysteresis to lower noise sensitivity.
Use differential-receiver to receive USB differential data signal.
Differential-receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to
the local ground reference level.
Above voltage range is the common mode input voltage range.
*3 :
1.0
0.2
0.8
2.5
Common mode input voltage [V]
The output drive capability of the driver is below 0.3 V at Low-state (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above
Document Number: 002-00233 Rev.*B
Page 87 of 107
S6E1C3 Series
*4 :
(to the VSS and 1.5 kΩ load) at high-state (VOH)
The cross voltage of the external differential output signal (D+ / D-) of USB I/O buffer is within 1.3 V to 2.0 V.
D+
Max 2.0V
VCRS specified range
Min 1.3V
D-
*5 :
The indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ±10% to minimize RFI emission.
D+
90%
90%
10%
10%
DTrise
Rising time
Tfall
Falling time
Full-speed buffer
Rs=27 Ω
TxD+
CL=50 pF
Rs=27 Ω
TxDCL=50 pF
3-state enable
*6 :
USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential
Mode).
USB standard defines that output impedance of USB driver must be in range from 28Ω to 44Ω. So, discrete series resistor
(Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 33 Ω (recommendation value : 27 Ω) series resistor Rs.
Document Number: 002-00233 Rev.*B
Page 88 of 107
S6E1C3 Series
Full-speed buffer
Rs
TxD+
28 Ω to 44 Ω equivalent impedance
Rs
TxD-
28 Ω to 44 Ω equivalent impedance
Mount it as external resistance.
3-state enable
Rs series resistor 25 Ω to 30 Ω
Series resistor of 27 Ω (recommendation value) must be added.
And, use “resistance with an uncertainty of 5% by E24 sequence”.
*7 :
They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
D+
90%
90%
10%
10%
DTrise
Rising time
Tfall
Falling time
See “Low-speed load (Compliance Load)” for condition of external load.
Document Number: 002-00233 Rev.*B
Page 89 of 107
S6E1C3 Series
・ Low-Speed Load (Upstream Port Load) – Reference 1
Low-speed buffer
Rs=27 Ω
TxD+
Rpd
CL=50 pF to 150 pF
Rs=27 Ω
TxDRpd
3-state enable
CL=50 pF to 150 pF
Rpd=15 kΩ
・ Low-Speed Load (Downstream Port Load) – Reference 2
Low-speed buffer
Rs=27 Ω
VTERM
TxD+
CL=200 pF to
600 pF
Rs=27 Ω
TxD-
CL=50 pF to 150 pF
3-state enable
Document Number: 002-00233 Rev.*B
Rpu=1.5 kΩ
VTERM=3.6 V
Page 90 of 107
S6E1C3 Series
・ Low-Speed Load (Compliance Load)
Low-speed buffer
Rs=27 Ω
TxD+
CL=200 pF to 450 pF
Rs=27 Ω
TxDCL=200 pF to 450 pF
3-state enable
Document Number: 002-00233 Rev.*B
Page 91 of 107
S6E1C3 Series
11.7 Low-Voltage Detection Characteristics
11.7.1 Low-Voltage Detection Reset
Parameter
Symbol
(TA=-40°C to +105°C)
Conditions
Min
1.38
1.43
Value
Typ
1.50
1.55
Max
1.60
1.65
Unit
Detected voltage
Released voltage
VDL
VDH
LVD stabilization wait
time
TLVDW
-
-
-
8160×
*2
tCYCP
μs
LVD detection delay
time
TLVDDL
-
-
-
200
μs
Fixed
*1
V
V
Remarks
When voltage drops
When voltage rises
*1: The value of low voltage detection reset is always fixed.
*2: tCYCP indicates the APB1 bus clock cycle time.
Document Number: 002-00233 Rev.*B
Page 92 of 107
S6E1C3 Series
11.7.2 Low-Voltage Detection Interrupt
(TA=-40°C to +105°C)
Min
1.56
1.61
1.61
1.66
1.66
1.70
1.70
1.75
1.75
1.79
1.79
1.84
1.84
1.89
1.89
1.93
2.30
2.39
2.39
2.48
2.48
2.58
2.58
2.67
2.67
2.76
2.76
2.85
2.85
2.94
2.94
3.04
Value
Typ
1.70
1.75
1.75
1.80
1.80
1.85
1.85
1.90
1.90
1.95
1.95
2.00
2.00
2.05
2.05
2.10
2.50
2.60
2.60
2.70
2.70
2.80
2.80
2.90
2.90
3.00
3.00
3.10
3.10
3.20
3.20
3.30
-
-
-
-
-
-
Symbo
l
Conditions
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
SVHI=00100
LVD stabilization wait
time
TLVDW
LVD detection delay
time
TLVDDL
Parameter
*:
SVHI=00101
SVHI=00110
SVHI=00111
SVHI=01000
SVHI=01001
SVHI=01010
SVHI=01011
SVHI=01100
SVHI=01101
SVHI=01110
SVHI=01111
SVHI=10000
SVHI=10001
SVHI=10010
SVHI=10011
Max
1.84
1.89
1.89
1.94
1.94
2.00
2.00
2.05
2.05
2.11
2.11
2.16
2.16
2.21
2.21
2.27
2.70
2.81
2.81
2.92
2.92
3.02
3.02
3.13
3.13
3.24
3.24
3.35
3.35
3.46
3.46
3.56
8160
×
tCYCP*
200
Uni
t
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
μs
μs
tCYCP represents the APB1 bus clock cycle time.
Document Number: 002-00233 Rev.*B
Page 93 of 107
S6E1C3 Series
11.8 Flash Memory Write/Erase Characteristics
Parameter
Sector erase time
Large
sector
Small
sector
(VCC=1.65 V to 3.6 V, TA=- 40°C to +105°C)
Min
Value
Typ
Max
-
1.1
2.7
-
0.3
0.9
Unit
s
Remarks
The sector erase time includes the time of
writing prior to internal erase.
The halfword (16-bit) write time excludes the
system-level overhead.
The chip erase time includes the time of
Chip erase time
4.5
11.7
s
writing prior to internal erase.
*: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.
Halfword (16-bit) write time
-
30
528
μs
Write/Erase Cycle and Data Hold Time
Write/Erase Cycle
Data Hold Time (Year)
1,000
20*
Remarks
10,000
10*
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test
result into average temperature value at + 85°C).
Document Number: 002-00233 Rev.*B
Page 94 of 107
S6E1C3 Series
11.9 Return Time from Low-Power Consumption Mode
11.9.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
Current Mode
(VCC=1.65 V to 3.6 V, TA=-40°C to +105°C)
Parameter
Sleep mode
Mode to return
Symbol
each Run Modes
High-speed CR Run mode
Main Run mode
PLL Run mode
Low-speed CR Run mode
Sub Run mode
High-speed CR Run mode
Low-speed CR Run mode
Main Run mode
Sub Run mode
PLL Run mode
High-speed CR Run mode
Low-speed CR Run mode
Sub Run mode
Main Run mode
PLL Run mode
Timer mode
Stop Mode
RTC mode
Value
Typ
Max
*1
4*HCLK
tICNT
Deep Standby RTC mode
High-speed CR Run mode
Deep Standby Stop mode
*1: The maximum value depends on the condition of environment.
Unit
Remarks
When
High-speed CR
is enabled
When
High-speed CR
is enabled
μs
12*HCLK
13*HCLK
μs
34+12*HCLK
72+13*HCLK
μs
34+12*HCLK
72+13*HCLK
μs
34+12*HCLK
+tOSCWT
72+13*HCLK
+tOSCWT
μs
34+12*HCLK
72+13*HCLK
μs
34+12*HCLK
+tOSCWT
72+13*HCLK
+tOSCWT
μs
43
281
μs
*2
*2
*2: tOSCWT : Oscillator stabilization time.
Operation Example of Return from Low-Power Consumption Mode (by External Interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-00233 Rev.*B
Page 95 of 107
S6E1C3 Series
Operation Example of Return from Low-Power Consumption Mode (by Internal Resource Interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "Chapter: Low Power Consumption Mode" in "FM0+ Family Peripheral Manual".
Document Number: 002-00233 Rev.*B
Page 96 of 107
S6E1C3 Series
11.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC=1.65 V to 3.6 V, TA=-40°C to +105°C)
Parameter
Current Mode
High-speed CR Sleep mode
Main Sleep mode
PLL Sleep mode
Mode to return
Symbol
Typ
Value
Max*
Unit
20
22
μs
Low-speed CR Sleep mode
50
106
μs
Sub Sleep mode
112
137
μs
20
22
μs
Low-speed CR Timer mode
87
159
μs
Sub Timer mode
148
209
μs
45
68
μs
43
281
μs
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
High-speed CR Run mode
Stop mode
RTC mode
Deep Standby RTC mode
Deep Standby Stop mode
*: The maximum value depends on the accuracy of built-in CR.
tRCNT
Remarks
When
High-speed CR
is enabled
When
High-speed CR
is enabled
When
High-speed CR
is enabled
When
High-speed CR
is enabled
Operation Example of Return from Low-Power Consumption Mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Document Number: 002-00233 Rev.*B
Start
Page 97 of 107
S6E1C3 Series
Operation Example of Return from Low Power Consumption Mode (by Internal Resource Reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "Chapter: Low Power Consumption Mode" in "FM0+ Family Peripheral Manual".
−
The time during the power-on reset/low-voltage detection reset is excluded. See "11.4.7 Power-on Reset Timing in 11.4 AC
Characteristics in 11. Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection
reset.
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
−
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-00233 Rev.*B
Page 98 of 107
S6E1C3 Series
12. Ordering Information
Part number
S6E1C32D0AGV20000
S6E1C31D0AGV20000
S6E1C32C0AGV20000
S6E1C31C0AGV20000
S6E1C32B0AGP20000
S6E1C31B0AGP20000
S6E1C32D0AGN20000
S6E1C31D0AGN20000
S6E1C32C0AGN20000
S6E1C31C0AGN20000
S6E1C32B0AGN20000
S6E1C31B0AGN20000
(TBD)
On-chip
Flash
memory
[Kbyte]
128
64
128
64
128
64
128
64
128
64
128
64
128
Document Number: 002-00233 Rev.*B
On-Chip
SRAM
[Kbyte]
16
12
16
12
16
12
16
12
16
12
16
12
16
Package
Plastic LQFP (0.50 mm pitch), 64 pins
(LQD064-02)
Plastic LQFP (0.50 mm pitch), 48 pins
(LQA048-02)
Plastic LQFP (0.80 mm pitch), 32 pins
(LQB032)
Plastic QFN64 (0.50 mm pitch), 64 pins
(WNS064)
Plastic QFN48 (0.50 mm pitch), 48 pins
(WNY048)
Plastic QFN32 (0.50 mm pitch), 32 pins
(WNU032)
WLCSP (TBD)
Packing
Tray
Tray
Tray
Tray
Tray
Tray
(TBD)
Page 99 of 107
S6E1C3 Series
13. Package Dimensions
Document Number: 002-00233 Rev.*B
Page 100 of 107
S6E1C3 Series
Document Number: 002-00233 Rev.*B
Page 101 of 107
S6E1C3 Series
Document Number: 002-00233 Rev.*B
Page 102 of 107
S6E1C3 Series
Document Number: 002-00233 Rev.*B
Page 103 of 107
S6E1C3 Series
Document Number: 002-00233 Rev.*B
Page 104 of 107
S6E1C3 Series
Document Number: 002-00233 Rev.*B
Page 105 of 107
S6E1C3 Series
Document History
Document Title: S6E1C3 Series 32-bit ARM® Cortex®-M0+ FM0+ Microcontroller
Document Number: 002-00233
Revision
ECN
Orig. of
Submission
Change
Date
Description of Change
**
4896074
TEKA
08/31/2015
New Spec.
*A
4955136
TEKA
10/9/2015
AC/DC characteristics updated. Typo fixed in “List of Pin Functions”.
Added the frequency value of “Ta = - 10°C to + 105°C” on “11.4.3
CR Oscillation Characteristics”.
Added the remark of “VCC < 0.2V” on “11.4.7
*B
5158709
YUKT
03/04/2016
Built-in
Power-on Reset Timing”.
Added the measure condition(*9) of ICC on “11.3.1 Current Rating”.
Changed the package outlines to cypress format on “13. Package
Dimensions”.
Changed the package codes to cypress codes on “3. Pin Assignment” and
“12. Ordering Information”.
Document Number: 002-00233 Rev.*B
Page 106 of 107
S6E1C3 Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
Products
®
®
ARM Cortex Microcontrollers
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
PSoC® Solutions
cypress.com/psoc
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
cypress.com/usb
cypress.com/wireless
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
© Cypress Semiconductor Corporation 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then
Cypress hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form,
to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end
users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license
(without the right to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software
solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or
compilation of the Software is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in
whole or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall
indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of
Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the
United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-00233 Rev.*B
March 4, 2016
Page 107 of 107