CY22388, CY22389, CY22391:Factory Programmable Quad PLL Clock Generator with VCXO

CY22388
CY22389
CY22391
Factory Programmable Quad PLL
Clock Generator with VCXO
Factory Programmable Quad PLL Clock Generator with VCXO
Features
Benefits
■
Fully integrated phase-locked loops (PLLs)
■
■
Small quad flat no-leads (QFN) package option
❐ 40% smaller than 20-pin TSSOP
❐ 22% smaller than 16-pin TSSOP
Meets most digital set top box, DVD recorder, and DTV
application requirements
■
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
■
Selectable output frequency
■
■
Programmable output frequencies
Integration eliminates the need for external loop filter
components
■
Output frequency range:
❐ 1 MHz to 166 MHz
■
Meets critical timing requirements in complex system designs
■
Enables application compatibility
■
Input frequency range:
❐ Crystal: 10 MHz to 30 MHz
❐ External reference: 1 MHz to 100 MHz
■
Complete VCXO solution with ±120 ppm (typical pull range)
For a complete list of related documentation, click here.
■
Analog voltage-control crystal oscillator (VCXO)
■
16-/20-pin TSSOP and 32-pin QFN packages
■
3.3-V operation with 2.5-V output buffer option
Logic Block Diagram
FS0
FS1
FS2
Select
Logic
CLKA
PLL1
CLKB
CLKC
PLL2
XIN
VCXO
Dividers
&
Multiplexers
XOUT
VIN
CLKD
CLKE
PLL3
PLL4
CLKF
(CY22389 &
CY22391 only)
CLKG
(CY22389 &
CY22391 only)
CLKH
(CY22389 &
CY22391 only)
OE/PD#
(CY22389 &
CY22391 only)
Cypress Semiconductor Corporation
Document Number: 38-07734 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 10, 2014
CY22388
CY22389
CY22391
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 4
General Description ......................................................... 5
Factory-Programmable CY22388/89/91 ...................... 5
PLLs ................................................................................... 5
Frequency Select Pin Operation ..................................... 5
Analog VCXO .................................................................... 6
VCXO Profile ..................................................................... 6
Absolute Maximum Conditions ....................................... 7
Pullable Crystal Specifications ....................................... 7
Operating Conditions ....................................................... 7
DC Parameters .................................................................. 8
AC Parameters .................................................................. 9
Test and Measurement ..................................................... 9
Voltage and Timing Definitions ..................................... 10
Document Number: 38-07734 Rev. *H
Ordering Information ...................................................... 11
Possible Configurations ............................................. 11
Ordering Code Definitions ......................................... 11
Package Drawing and Dimensions ............................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Page 2 of 16
CY22388
CY22389
CY22391
Pinouts
Figure 1. 16-pin TSSOP pinout
16-Pin TSSOP
XIN
1
16
XOUT
FS0
2
15
VDD
FS1
3
14
FS2
VIN
4
13
VDD
VDD
5
12
VSS
VSS
6
11
CLKE
CLKA
7
10
CLKD
CLKB
8
9
CLKC
CY22388
Figure 2. 20-pin TSSOP pinout
Figure 3. 32-pin QFN pinout
25 VDD
NC
28
26 VDD
NC
29
30 XIN
32 FS1
31 FS0
27 XOUT
32-Pin QFN
20- Pin TSSOP
XIN
1
20
XOUT
FS0
2
19
VDD
VIN
1
24 OE/PD#
FS1
3
18
OE/PD#
VDD
2
23
FS2
CLKH
4
17
FS2
VDD
3
22
VDD
VIN
VSS
4
21
VDD
VSS
5
20
VSS
VSS
6
19
VSS
VSS
7
18
CLKG
CLKH
8
17
CLKF
Document Number: 38-07734 Rev. *H
VDD
CLKE
15
11
16
10
14
CLKC
13
CLKF
12
CLKG
12
11
13
9
9
8
CLKA
10
CLKB
CLKE
VDD
VSS
NC
14
CLKC
7
CY22391
NC
16
CY22389
15
6
CLKA
CLKD
5
CLKB
VSS
CLKD
VDD
Page 3 of 16
CY22388
CY22389
CY22391
Pin Definitions
Pin Name
Pin Number
Pin Description
16-pin TSSOP
20-pin TSSOP
32-pin QFN
XIN
1
1
30
XOUT
16
20
27
Crystal output (No connect if external clock is used)
CLKA
7
9
11
Clock output
CLKB
8
8
10
Clock output
CLKC
9
10
14
Clock output
CLKD
10
7
9
Clock output
CLKE
11
11
15
Clock output
CLKF
n/a
12
17
Clock output
CLKG
n/a
13
18
Clock output
CLKH
n/a
4
8
Clock output
2
2
31
Frequency select 0
FS0
Crystal input or reference clock input
FS1
3
3
32
Frequency select 1
FS2
14
17
23
Frequency select 2
OE/PD#
n/a
18
24
Programmable control pin: Output enable (active-high)
or power-down (active-low)
1
Analog control input for VCXO
VIN
4
16
VDD
5, 13, 15
5, 15, 19
VSS
6, 12
6, 14
NC
N/A
N/A
Document Number: 38-07734 Rev. *H
2, 3, 16, 21, 22, Voltage supply
25, 26
4, 5, 6, 7, 19, 20 Ground
12, 13, 28, 29
No connect.
Page 4 of 16
CY22388
CY22389
CY22391
General Description
CLKC and CLKE have related frequencies. Related frequencies
come from the same PLL but can have different divider values.
The CY22388 family of devices has an analog VCXO, four PLLs,
up to eight clock outputs and frequency selection capabilities.
The frequency selects do not modify any PLL frequency. Instead
they allow the user to choose among eight different output divider
selections depending on the clock and package configuration.
This is illustrated in the Frequency Select Pin Operation tables
and on page 1.
To minimize parts per million (PPM) error on the clock outputs,
you must choose a crystal reference frequency that is a common
multiple of the desired PLL frequencies. While this is the ideal
situation, this is not always the case and the PLLs have
high-resolution counters internally to help minimize frequency
deviation from the desired frequency.
There is one programmable OE/PD#. The OE/PD# pin can be
programmed as either an output enable pin or a power-down pin.
The OE function can be programmed to disable a selected set of
outputs when low, leaving the remaining outputs running.
Full-chip power-down disables all outputs and the PLLs and
most of the active circuitry when low.
where FREF is the reference input frequency, P is the PLL
feedback divider, and Q is the reference input divider.
Factory-Programmable CY22388/89/91
Factory programming is available for high- or low-volume
manufacturing by Cypress. All requests must be submitted to the
local Cypress field application engineer (FAE) or sales
representative. After the request is processed, you receive a new
part number, samples, and datasheet with the programmed
values. This part number is used for additional sample requests
and production orders.
PLL VCO frequencies are generated by the following equation:
FVCO = FREF * (P / Q)
A PLL is a feedback system where the VCO frequency divided
by P and reference frequency divided by Q are constantly being
compared and the VCO frequency is adjusted to achieve a
locked state. Figure 4 is a simplified drawing of a PLL.
Figure 4. PLL system
F
R E F
/Q
V C O
a nd
F
V C O
O th e r
c o m p o n e n ts
/P
PLLs
The advantage of having four PLLs is that a single device can
generate up to four independent frequencies from a single
crystal. Generally a design may require up to four oscillators to
accomplish what could be done with a single CY22388.
Frequency Select Pin Operation
Each PLL is independent and can be configured to generate a
voltage-controlled oscillator (VCO) frequency between
62.5 MHz and 250 MHz. Each PLL can then, in turn, be divided
down with post dividers to generate the clock output frequency
of the user’s choice. The output divider allows each clock output
to be divided by 1, 2, 3, 4, 5, 6, 8, 9, 10, 12 or 15. The PLL
maximum is reduced to 166 MHz in ‘divide by 1’ mode due to
output buffer limitations.
CLK A
Outputs that allow frequency switching perform a glitch-free
transition. A glitch is defined as a high- or low-time shorter than
half the smaller of the two periods being switched between.
Extended low time (even many cycles in duration) is acceptable.
Selected clock outputs are capable of being powered off a
separate 2.5-V supply. This allows for driving lower voltage swing
inputs. The CY22388/89/91 device still requires 3.3 V to power
the oscillator and all other internal PLL circuitry. For the 2.5-V
output option, refer to the CY22388 application note. Selected
clocks and pinout diagrams are explained in this application
note.
Clock D can obtain its output from either the reference source or
PLL1/N1 with N1 being defined as the output divider for PLL1.
Clock H is defined as a copy of clock D. Clock D is only available
from PLL1/N1 on the 16-pin package.
For CY22388, CLKB and CLKC have related frequencies. For
CY22389 and CY22391, CLKD and CLKF have related
frequencies, CLKA and CLKB have related frequencies, and
Document Number: 38-07734 Rev. *H
Table 1. CY22388 16-pin TSSOP
Output Signal
Frequency Selection Lines
FS2, FS1, FS0
CLK B
FS1, FS0
CLK C & CLK D
S0
CLK E
FIXED
Table 2. CY22389 20-pin TSSOP
Output Signal
Frequency Selection Lines
CLK A
FS2, FS1, FS0
CLK B & CLK C
FS1, FS0
CLK D, CLK E, & CLK F
FS0
CLK G
FIXED
CLK H
COPY OF CLK D
Table 3. CY22391 32-pin QFN
Output Signal
Frequency Selection Lines
CLK A
FS2, FS1, FS0
CLK B & CLK C
FS1, FS0
CLK D, CLK E, & CLK F
FS0
CLK G
FIXED
CLK H
COPY OF CLK D
Page 5 of 16
CY22388
CY22389
CY22391
There are three programmable reference operating modes for
the CY22388, CY22389, and CY22391 family of devices. The
first mode uses an external pullable crystal and incorporates an
internal analog VCXO.
The second mode configures the internal crystal oscillator to
accept an external driven reference source from 1 to 100 MHz.
The input capacitance on the XIN PIN when driven in this mode
is 15 pF.
The third mode disables the VCXO input control and sets the
internal oscillator to a fixed frequency operation. The load
capacitance seen by the external crystal when connected to
PINS XIN and XOUT is equal to 12 pF.
One of the key components in the CY22388, CY22389, and
CY22391 family of devices is the analog VCXO. The VCXO is
used to ‘pull’ the reference crystal higher or lower to lock the
system frequency to an external source. This is ideal for
applications where the output frequency needs to track along
with an external reference frequency that is constantly shifting.
The VCXO is completely analog, so there is infinite resolution on
the VCXO pull curve. The analog to digital converter steps that
are normally associated with a digital VCXO input is not present
in this device. A special pullable crystal must be used in order to
have adequate VCXO pull range. Pullable crystal specifications
are included in this datasheet.
Document Number: 38-07734 Rev. *H
Refer to the application note, Layout Recommendations for the
CY22388, CY22389, and CY22391 Devices - ANC0001, for
pullable crystal recommendations outside of the standard
industry frequencies given in the Pullable Crystal specifications.
VCXO Profile
Figure 5 shows an example of what a VCXO profile looks like.
The analog voltage input is on the X-axis and the PPM range is
on the Y-axis. An increase in the VCXO input voltage results in a
corresponding increase in the output frequency. This has the
effect of moving the PPM from a negative to positive offset.
Figure 5. VCXO Profile
200
150
100
Tuning [ppm
Analog VCXO
50
0
-50
0
0.5
1
1.5
2
2.5
3
3.5
-100
-150
-200
VCXO input [V]
Page 6 of 16
CY22388
CY22389
CY22391
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
–0.5
4.6
V
VDD/AVDD/VDDL
Core supply voltage
VIN
Input voltage
Relative to VSS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-Functional
–65
125
°C
ESDHBM
Electrostatic discharge (ESD)
protection (human body model)
MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability rating
V-0 at 1/8 in.
–
10
ppm
MSL
Moisture sensitivity level
All packages
3
–
Pullable Crystal Specifications
Parameter [1, 2]
Description
Comments
FNOM
13.5-MHz and 27-MHz crystal
AT-Cut
Parallel resonance, fundamental
mode
CLNOM
Nominal load capacitance
Order crystal at one specific
CLNOM 0 ppm
R1
Equivalent series resistance
(ESR)
DL
Crystal drive level
C0[3]
C1[3]
F3SEPHI[2]
Third overtone separation from
3 × FNOM
F3SEPLO[2]
Third overtone separation from
3 × FNOM
Min
Typ
Max
Unit
See Note 2
11.4
12
12.6
pF
Fundamental mode (CL = Series)
–
–
40

Nominal VDD at 25 °C over
±120 ppm pull range
–
–
300
W
Crystal shunt capacitance
1.5
3
4.0
pF
Crystal motional capacitance
12
14
16.8
fF
Mechanical third (high side of
3 × FNOM)
240
–
–
ppm
Mechanical third (low side of
3 × FNOM)
–
–
–120
ppm
Operating Conditions
Min
Typ
Max
Unit
VDD/AVDD/VDDL
Parameter
Operating voltage
Description
3.0
3.3
3.6
V
TA
Ambient temperature
–10
–
70
°C
CLOAD
Maximum load capacitance
–
–
15
pF
tPU
Power-up time for all VDDs reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
500
ms
Notes
1. Device operates to the following specs, which are guaranteed by design.
2. Refer to CY22388 Application Note and online software for a list of approved crystal specifications.
3. Increased tolerance available from pull range less than ±120 ppm.
Document Number: 38-07734 Rev. *H
Page 7 of 16
CY22388
CY22389
CY22391
DC Parameters
Parameter [4]
[5]
Description
Conditions
Min
Typ
Max
Unit
Output high current
VOH = VDD – 0.5, VDD = 3.3 V
12
–
–
mA
IOL[5]
Output low current
VOL = 0.5, VDD = 3.3 V
12
–
–
mA
IIH
Input high current
VIH = VDD, excluding Vin, Xin
–
5
10
µA
IIL
Input low current
VIL = 0 V, excluding Vin, Xin
–
5
10
µA
VIH
Input high voltage
FS0/1/2 OE input CMOS levels
0.7 × AVDD
–
–
V
VIL
Input low voltage
FS0/1/2 OE input CMOS levels
–
–
0.3 × AVDD
V
VVCXO
VIN input range
0
–
AVDD
V
CIN
Input capacitance
FS0/1/2 and OE pins only
–
–
7
pF
IVDD
Supply current
VDD/AVDD/VDDL current
–
60
–
mA
CINXIN
Input capacitance at XIN
VCXO disabled external reference
–
15
–
pF
CINXTAL
Input capacitance at crystal
VCXO disabled fixed frequency
oscillator
–
12
–
pF
IOH
Notes
4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
5. Custom drive level is available upon request.
Document Number: 38-07734 Rev. *H
Page 8 of 16
CY22388
CY22389
CY22391
AC Parameters
Parameter [4]
Min
Typ
Max
Units
1/t1
Output frequency
PLL minmax/Dividermaximum
Conditions
4.2
–
166
MHz
DC1
Output duty cycle
(excluding REFOUT
Duty cycle is defined in Figure 7;
t2/t1, 50% of VDD
External reference duty cycle
between 40% and 60% measured at
VDD/2 (Clock output is 125 MHz)
45
50
55
%
DC2
Output duty cycle
Duty cycle is defined in Figure 7;
t2/t1, 50% of VDD
External reference duty cycle
between 40% and 60% measured at
VDD/2 (Clock output is 125 MHz)
40
50
60
%
DCREFOUT
Output duty cycle
Duty cycle is defined in Figure 7;
t2/t1, 50% of VDD
(XIN Duty Cycle = 45/55%)
40
50
60
%
ER
Rising edge rate
Output clock edge rate. Measured
from 20% to 80% of VDD.
CLOAD = 15 pF. See Figure 8.
0.75
1.2
–
V/ns
EF
Falling edge rate
Output clock edge rate. Measured
from 80% to 20% of VDD.
CLOAD = 15 pF. See Figure 8.
0.75
1.2
–
V/ns
T9
Clock jitter
Period jitter
–
±250
–
ps
T10
PLL lock time
fXO
VCXO crystal pull range
Description
–
1
5
ms
Using non-SMD-49 crystal specified
in CY22388 application note,
ANC0002”
Nominal crystal frequency input
assumed (0 ppm) at 25 °C and 3.3 V
±110
±120
–
ppm
Using SMD-49 crystal specified in
CY22388 application note,
ANC0002”
Nominal crystal frequency input
assumed (0 ppm) at 25 °C and 3.3 V
±105
±120
–
ppm
Test and Measurement
Figure 6. Test and Measurement
V DDs
O utputs
DUT
0.1F
C LO A D
GND
Document Number: 38-07734 Rev. *H
Page 9 of 16
CY22388
CY22389
CY22391
Voltage and Timing Definitions
Figure 7. Duty Cycle Definition
t1
t2
V DD
50% of V DD
Clock
Output
0V
Figure 8. ER = (0.6 VDD)/t3, EF = (0.6 VDD)/t4
t3
t4
V DD
80% of V DD
20% of V DD
Clock
Output
0V
Figure 9. FS Controlled Clock Output
Finish Cycle
Start at Full Cycle
FS
TWAIT
Document Number: 38-07734 Rev. *H
Page 10 of 16
CY22388
CY22389
CY22391
Ordering Information
All product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible Configurations
table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales representative for
more information.
Part Number
Type
Package
Production Flow
Pb-free
CY22388FZXC
ZZ16
16-pin TSSOP
Commercial, 0 °C to +70 °C
CY22388FZXCT
ZZ16
16-pin TSSOP – Tape and Reel
Commercial, 0 °C to +70 °C
Possible Configurations
Part Number [6]
Type
Package
Production Flow
Pb-free
CY22388ZXC-xxx
ZZ16
16-pin TSSOP
Commercial, 0 °C to +70 °C
CY22388ZXC-xxxT
ZZ16
16-pin TSSOP – Tape and Reel
Commercial, 0 °C to +70 °C
CY22389ZXC-xxx
ZZ20
20-pin TSSOP
Commercial, 0 °C to +70 °C
CY22389ZXC-xxxT
ZZ20
20-pin TSSOP – Tape and Reel
Commercial, 0 °C to +70 °C
CY22391LTXC-xxx
LT32
32-pin QFN (Sawn)
Commercial, 0 °C to +70 °C
CY22391LTXC-xxxT
LT32
32-pin QFN (Sawn) – Tape and Reel
Commercial, 0 °C to +70 °C
Ordering Code Definitions
CY
223XX
XX X C - xxx
X
X = blank or T
blank = tube; T = Tape and Reel
Custom Configuration Code
Temperature Range: C = Commercial
Pb-free
Package: XX = Z or LT
Z = 16-pin TSSOP or 20-pin TSSOP
LT = 32-pin QFN
Part Identifier: 223XX = 22388 or 22389 or 22391
Company Code: CY = Cypress
Notes
6. The CY22388ZXC-xxx, CY22389ZXC-xxx, and CY22391LTXC-xxx are factory-programmed configurations. For more details, contact your local Cypress FAE
or sales representative.
Document Number: 38-07734 Rev. *H
Page 11 of 16
CY22388
CY22389
CY22391
Package Drawing and Dimensions
Figure 10. 16-pin TSSOP (4.40 mm Body) Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Figure 11. 20-pin TSSOP (4.40 mm Body) Z20.173/ZZ20.173 Package Outline, 51-85118
51-85118 *E
Document Number: 38-07734 Rev. *H
Page 12 of 16
CY22388
CY22389
CY22391
Package Drawing and Dimensions (continued)
Figure 12. 32-pin QFN (5 × 5 × 1.0 mm) LT32B 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-30999
001-30999 *D
Document Number: 38-07734 Rev. *H
Page 13 of 16
CY22388
CY22389
CY22391
Acronyms
Acronym
Document Conventions
Description
Units of Measure
ESD
Electrostatic Discharge
ESR
Equivalent Series Resistance
°C
degree Celsius
FAE
Field Application Engineer
fF
femtofarad
FS
Frequency Select
K
kilohm
PJ
Period Jitter
MHz
megahertz
PLL
Phase-Locked Loop
µA
microampere
QFN
Quad Flat No-leads
µF
microfarad
TSSOP
Thin Shrunk Small Outline Package
µs
microsecond
VCO
Voltage-Controlled Oscillator
µW
microwatt
VCXO
Voltage-Controlled Crystal Oscillator
mA
milliampere
ms
millisecond
mV
millivolt
ns
nanosecond
Document Number: 38-07734 Rev. *H
Symbol
Unit of Measure

ohm
PPM
parts per million
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 14 of 16
CY22388
CY22389
CY22391
Document History Page
Document Title: CY22388/CY22389/CY22391, Factory Programmable Quad PLL Clock Generator with VCXO
Document Number: 38-07734
Revision
ECN
Orig. of
Change
Submission
Date
**
320458
RGL
03/07/05
New data sheet Internal setting in VCXO are XOB/A=110, Offset=1110,
Gain=101
*A
389649
RGL
08/02/05
Changed R1 value to max. 40
Changed DL comments and max. value to 300W
Changed fXO min. value to ±110ppm and typ. value to ±120ppm
*B
523597
RGL
11/12/06
Specified a non-SMD-49 and SMD-49 crystal specs in the VCXO Pull Range
Parameter
*C
2632357
KVM
01/13/09
Updated template.
Updated Ordering Information table to add tape & reel part numbers.
Added LT32 (saw) QFN package for CY22391, including package drawing.
LY32 (punch) QFN package “not recommended for new designs”
Added Package column to Ordering Information table and cleaned up package
references in captions of the package drawings.
Changed document title to spell out each part number in full.
Clarified that Power Down (PD#) is active-low: in block diagram, CY22389
pinout and in pin description table. Replaced PDWN and PD with PD#.
Changed package diagram 51-85188*A to 51-85188*B.
*D
2897246
KVM
03/22/10
Added note regarding Possible Configurations in Possible Configurations
section. Updated package diagrams. Removed LY32 package drawing.
Updated Note 6 and removed Note 7.
*E
3030336
CXQ
09/14/10
Fixed formatting in Features on page 1.
Fixed various typos.
Changes all packages to MSL 3.
Removed “Recommended” from Operating Conditions heading.
Added Ordering Code Definitions.
Added Acronyms, and Units of Measure.
Updated Figure 10 and Figure 11.
Updated Sales, Solutions, and Legal Information
*F
3786734
PURU
10/29/2012
Modified Figure 3 caption.
Added two part numbers (CY22388FZXC and CY22388FZXCT).
Updated Package Drawing and Dimensions for 51-85091 (*C to *D), 51-85118
(*C to *D), and 001-30999 (*C to *D).
*G
4142797
CINM
10/01/2013
Updated in new template.
Completing Sunset Review.
*H
4576237
CINM
11/21/2014
Added related documentation hyperlink in page 1.
Updated output frequency range as 1 MHz to 166 MHz in Features.
Updated the following figures in Package Drawing and Dimensions:
Figure 10 (spec 51-85091 *D to *E) and Figure 11 (spec 51-85118 *D to *E).
Document Number: 38-07734 Rev. *H
Description of Change
Page 15 of 16
CY22388
CY22389
CY22391
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/support
cypress.com/go/touch
USB Controllers
Wireless/RF
Technical Support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2005-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07734 Rev. *H
Revised December 10, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
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