RT9603 Preliminary Synchronous-Rectified Buck MOSFET Drivers General Description Features The RT9603 is a high frequency, dual MOSFET drivers specifically designed to drive two power N-Channel MOSFETs in a synchronous-rectified buck converter topology. The device combined with the RT924x series of multi-phase PWM controllers and MOSFETs form a complete core voltage regulator solution for advanced microprocessors. l The output drivers in the RT9603 can efficiently switch power MOSFETs at frequencies up to 500kHz. It shall be taken into account the thermal consideration when the switching frequency above 500kHz. Each driver is capable of driving a 3nF load in 30/40ns rise/fall time with fast propagation delay from input transition to the gate of the power MOSFET. The device implements bootstrapping on the upper gate with only an external capacitor and a diode required. This reduces implementation complexity and allows the use of higher performance, cost effective N-Channel MOSFETs. Both drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. An unique feature of the RT9603 driver is the addition of over-voltage protection in the event of upper MOSFET direct shorted before power-on. The RT9603 detects the fault condition during initial start-up, the internal poweron OVP sense circuitry will rapidly drive the output lower MOSFET on before the multi-phase PWM controller takes control. As a result, the input supply will latch into the shutdown state, thereby prevent the processor from damaged. l l l l l l l Drives Two N-Channel MOSFETs Adaptive Shoot-Through Protection Supports High Switching Frequency - Fast Output Rise Time - Propagation Delay 40ns Tri-State Input for Bridge Shutdown Supply Over-Voltage Protection above Maximum Voltage Rating Supply Under-Voltage Protection Upper MOSFET Direct Shorted Protection Small SOP-8 Package Applications l l l l Core Voltage Supplies for Intel Pentium 4, AMD AthlonTM Microprocessors High Frequency Low Profile DC-DC Converters High Current Low Voltage DC-DC Converters IA Equipments Pin Configurations (TOP VIEW) BST 8 DRVH IN 2 7 SW NC 3 6 PGND VCC 4 5 DRVL SOP-8 Ordering Information RT9603 Package Type S : SOP-8 Operating Temperature Range C : Commercial Standard DS9603-00 November 2003 www.richtek.com 1 RT9603 Preliminary Typical Application Circuit +12V +12V R1 10 D1 1N4148 C3 1uF 1 PWM INPUT 3 2 VCC NC C2 1uF RT9603 4 C1 1uF BST DRVH SW DRVL IN C4 1000uF/16V 8 7 Q1 PHB83N03LT L1 2uH 5 PGND 6 Q2 PHB95N03LT R2 C5 x1500uF VCORE C6 x1500uF ISPx 2.4K R3 ISNx 2.4K Note: The traces that run from the controller ISPx and ISNx pins, should be run together next to each other and Kelvin connected to the Q2. Place both R2 and R3 as close to the PWM Controller as possible. Functional Pin Description Pin No. Pin Name Pin Function Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor 1 BST between this pin and the SW pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. 2 IN Accepts a logic control signal. Connect this pin to the PWM output of the controller. If the PWM signal enters and remains within the shutdown window, the output drivers are disabled and both MOSFET gates are pulled and held low. 3 NC No Internal Connection. 4 VCC Supply Input. Connect to +12V supply. Place a bypass capacitor from this pin to PGND. 5 DRVL Lower gate drive output. Should be connected to the lower MOSFET gate. 6 PGND Common Ground. 7 SW 8 DRVH www.richtek.com 2 Upper driver return. Should be connected to the common node of upper and lower MOSFETs. The SW voltage is monitored for adaptive shoot-through protection. Upper gate drive output. Should be connected to the upper MOSFET gate. DS9603-00 November 2003 RT9603 Preliminary Function Block Diagram VCC BST Internal 5V Shoot-Through Protection DRVH R SW Control Logic IN Power-On OVP R VCC Shoot-Through Protection DRVL PGND Timing Diagram IN TPDDRVH TRDRVH TFDRVH DRVH DRVL TFDRVL TRDRVL TPDDRVL DS9603-00 November 2003 www.richtek.com 3 RT9603 Preliminary Absolute Maximum Ratings (Note 1) l l l l l l l l l l Supply Voltage (VCC) ------------------------------------------------------------------------------------ 15V BST to SW ------------------------------------------------------------------------------------------------ 15V SW to GND ----------------------------------------------------------------------------------------------- −4V to 15V PWM Input Voltage ------------------------------------------------------------------------------------- GND - 0.3V to 7V DRVH ------------------------------------------------------------------------------------------------------ VSW - 0.3V to VBST + 0.3V DRVL ------------------------------------------------------------------------------------------------------- GND - 0.3V to V VCC + 0.3V Package Thermal Resistance SOP-8, θJA ------------------------------------------------------------------------------------------------ 67°C/W Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------ 260°C Storage Temperature Range ------------------------------------------------------------------------- −40° C to 150° C ESD Susceptibility (Note 2) HBM -------------------------------------------------------------------------------------------------------- 2kV Recommended Operating Conditions l l l (Note 3) Supply Voltage, VCC ------------------------------------------------------------------------------------------------- 12V ±10% Ambient Temperature Range ------------------------------------------------------------------------------------- 0° C to 70° C Junction Temperature Range ------------------------------------------------------------------------------------ 0° C to 125°C Electrical Characteristics (Recommended Operating Conditions, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ M ax Units -- 5 7 mA 8.6 9.9 10.7 V -- 1.35 -- V V CC Supply Current Power Supply Current IVCC V BST = 12V, V PW M _ IN = 0V POR Threshold V VCCRTH V CC Rising Hysteresis V VCCHYS Power-On Reset PWM Input Input Current IPW M _ IN V PW M _ IN = 0V or 5V 80 127 150 µA Floating Voltage V PW MFL V CC = 12V 1.1 2.1 3.7 V V PW MRTH PW M_IN Rising 3.3 3.7 4.3 V V PW MFTH PW M_IN Falling 1.0 1.26 1.5 V DRVH Rise Tim e T RDRVH V VCC = 12V, 3nF load -- 30 -- ns DRVH Fall Time T FDRVH V VCC= 12V, 3nF load -- 40 -- ns DRVL Rise Tim e T RDRVL V VCC= 12V, 3nF load -- 30 -- ns DRVL Fall Time T FDRVL V VCC = 12V, 3nF load -- 30 -- ns DRVH Turn-Off Propagation Delay T PDDRVH V VCC = 12V, 3nF load -- 40 -- ns DRVL Turn-Off Propagation Delay T PDDRVL V VCC = 12V, 3nF load -- 35 -- ns 1.0 -- 4.3 V PW M_IN Threshold Shutdown W indow To be continued www.richtek.com 4 DS9603-00 November 2003 RT9603 Preliminary Parameter Symbol Test Conditions Min Typ Max Units V VCC = 12V -- 2 -- Ω 2.8 -- Ω Output Upper Drive Source R D RVH Upper Drive Sink R D RVH V VCC = 12V -- Lower Drive Source R D RVL V VCC = 12V -- 1.9 -- Ω Lower Drive Sink R D RVL V VCC = 12V -- 1.6 -- Ω Note 1. Stresses beyond those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Note 3. The device is not guaranteed to function outside its operating conditions. DS9603-00 November 2003 www.richtek.com 5 RT9603 Preliminary Applications Information The RT9603 is designed to drive both high side and low side N-Channel MOSFET through externally input PWM control signal. It has power-on protection function which held DRVH and DRVL low before VCC up across the rising threshold voltage. After the initialization, the PWM signal takes the control. The rising PWM signal first forces the DRVL signal turns low then DRVH signal is allowed to go high just after a non-overlapping time to avoid shootthrough current. The falling of PWM signal first forces DRVH to go low. When DRVH and SW signal reach a predetermined low level, DRVL signal is allowed to turn high. The non-overlapping function is also presented between DRVH and DRVL signal transient. The PWM signal is acted as "High" if above the rising threshold and acted as "Low" if below the falling threshold. Any signal level enters and remains within the shutdown window is considered as "tri-state", the output drivers are disabled and both MOSFET gates are pulled and held low. If left the PWM signal (IN) floating, the pin will be kept at 2.1V by the internal divider and provide the PWM controller with a recognizable level. The RT9603 typically operates at frequency of 200kHz to 250kHz. It shall be noted that to place a 1N4148 or schottky diode between the VCC and BST pin as shown in the typical application circuit. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When Vgs at 12V (or 5V), the gate draws the current only few nano-amperes. Thus once the gate has been driven up to "ON" level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. www.richtek.com 6 D1 L s1 d1 VOUT VIN Cgs1 Cgd1 Cgd2 d2 Igs1 Igd1 Ig1 Ig2 Igd2 g1 g2 D2 Igs2 Cgs2 s2 GND Vg1 VSW +12V t Vg2 12V t Figure 1. Equivalent Circuit and Associated Waveforms In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V. The operation consists of charging Cgd and Cgs. Cgs1 and Cgs2 are the capacitances from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs is referred as "Crss" which is the input capacitance. Cgd1 and Cgd2 are the capacitances from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as "Crss" the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2 are showed , below: l gs1 = C gs1 dVg1 C gs1 × 12 = dt t r1 (1) l gs2 = C gs2 dVg2 C gs2 × 12 = dt t r2 (2) DS9603-00 November 2003 RT9603 Preliminary (3) 2200 × 10 − 12 × 12 − 9 30 × 10 lgs1 = I gd2 = 380 × 10 14 × 10 × 12 − 9 VCORE CB 1uF 8 7 C3 1500uF 2uH Q2 PHB83N03LT PHB95N03LT 5 1 BST DRVH SW DRVL 4 VCC IN PGND 2 12V PWM 6 Figure 2. Two-Phase Synch. Buck Converter Circuit = 1.428 (A) (5) = 0.88 (A) (6) = 0.326 (A) 500 × 10 -12 × (12 + 12) = 0.4(A) 30 × 10 − 9 (7) (8) the total current required from the gate driving source is I g1 = I gs1 + I gd1 = (1.428 + 0.326) = 1.745(A) I g2 = I gs2 + I gd2 = (0.88 + 0.4) = 1.28(A) When layout the PC board, it should be very careful. The power-circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 should be very close. Next, the trace from DRVH, and DRVL should also be short to decrease the noise of the driver output signals. SW signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C4 should be connected to PGND directly. Furthermore, the bootstrap capacitors (CB) should always be placed as close to the pins of the IC as possible. Select the Bootstrap Capacitor from equation. (3) and (4) − 12 Q1 L2 + l gs2 = × 12 − 9 14 × 10 C2 1uF R1 C4 10 1uF (4 ) It is helpful to calculate these currents in a typical case. Assume a synchronous rectified buck converter, input voltage VIN = 12V, Vg1 = Vg2 = 12V. The high side MOSFET is PHB83N03LT whose Ciss = 1660pF, Crss = 380pF, and tr = 14ns. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and t r = 30ns, from the equation (1) and (2) we can obtain − 12 1.2uH C1 1000uF dV Vi + 12V = C gd 2 dt t r2 1660 × 10 D1 + VIN 12V Before the low side MOSFET is turned on, the Cgd2 have been charged to VIN. Thus, as Cgd2 reverses its polarity and g2 is charged up to 12V, the required current is l gs1 = Figure 2 shows the schematic circuit of a two-phase synchronous buck converter to implement the RT9603. The converter operates from 5V to 12V of VIN. L1 dV 1 2V l g d1 = C g1 = C gd 1 dt t r1 l gd 2 = C gd 2 Layout Consideration RT9603 Before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET is turned off before the low side is turned on. From Figure 1, the body diode "D2" had been turned on before high side MOSFETs turned on. Figure 3 shows part of the bootstrap circuit of RT9603. The VCB (the voltage difference between BST and SW on RT9603) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CB has to be selected properly. It is determined by following constraints. (9) (10) By a similar calculation, we can also get the sink current required from the turned off MOSFET. DS9603-00 November 2003 www.richtek.com 7 RT9603 Preliminary Figure 5 shows the power dissipation of the RT9603 as a function of frequency and load capacitance. The value of the CU and CL are the same and the frequency is varied from 100kHz to 1MHz. VIN 1N4148 VCC BST DRVH + VCB - CB SW Power Dissipation vs. Frequency 1000 VCC PGND Figure 3. Part of Bootstrap Circuit of RT9603 In practice, a low value capacitor CB will lead the overcharging that could damage the IC. Therefore to minimize the risk of overcharging and reducing the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1µF, and the larger the better. In general design, using 1µF can provide better performance. At least one low-ESR capacitor should be used to provide good local decoupling. Here, to adopt either a ceramic or tantalum capacitor is suitable. Power Dissipation For not exceeding the maximum allowable power dissipation to drive the IC beyond the maximum recommended operating junction temperature of 125°C, it is necessary to calculate power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 4 shows the power dissipation test circuit. CL and CU are the DRVH and DRVL load capacitors, respectively. The bootstrap capacitor value is 0.01µF. 10 1uF 1N4148 Power Dissipation (mW) DRVL +12V CU=CL=3nF 900 800 700 600 500 CU=CL=2nF 400 300 CU=CL=1nF 200 100 0 0 200 400 600 800 1000 Frequency (kHz) Figure 5. Power Dissipation vs. Frequency The operating junction temperature can be calculated from the power dissipation curves (Figure 5). Assume VCC=12V, operating frequency is 200kHz and the CU=CL=1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 5, the power dissipation is 100mW. For RT9603, the package thermal resistance θJA is 67° C/W, the operating junction temperature is calculated as: TJ = (67°C/W x 100mW) + 25°C = 31.7°C (11) where the ambient temperature is 25°C. The method to improve the thermal transfer is to increase the PC board copper area around the RT9603 firstly. Then, adding a ground pad under IC to transfer the heat to the peripheral of the board. +12V CBST BST VCC 2N7002 DRVH 1uF CU 3nF RT9603 SW 2N7002 PWM IN DRVL PGND 20 CL 3nF Figure 4. Test Circuit www.richtek.com 8 DS9603-00 November 2003 Preliminary RT9603 Over-Voltage Protection Function at Power-On An unique feature of the RT9603 driver is the addition of over-voltage protection in the event of upper MOSFET direct shorted before power-on. The RT9603 detects the fault condition during initial start-up, the internal poweron OVP sense circuitry will rapidly drive the output lower MOSFET on before the multi-phase PWM controller takes control. Figure 6 shows the measured waveforms with the high side MOSFET directly shorted to 12V. VCC SW DRVL VCORE Figure 6. Waveforms at High Side MOSFET Shorted Please note that the VCC trigger point to RT9603 is at 3V, and the clamped level on SW pin is at about 2.4V. Obviously since the SW pin voltage increases during initial start-up, the VCORE increases correspondingly, but it would quickly drop-off followed by DRVL and VCC decreased. DS9603-00 November 2003 www.richtek.com 9 RT9603 Preliminary Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 8-Lead SOP Plastic Package RICHTEK TECHNOLOGY CORP. RICHTEK TECHNOLOGY CORP. Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected] www.richtek.com 10 DS9603-00 November 2003