FAIRCHILD SPT9101

SPT9101
125 MSPS SAMPLE-AND-HOLD AMPLIFIER
FEATURES
APPLICATIONS
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Second Source of AD9101
350 MHz Sampling Bandwidth
125 MHz Sampling Rate
Excellent Hold Mode Distortion
-75 dB at 50 MSPS (23 MHz VIN)
-62 dB at 100 MSPS (48 MHz VIN)
7 ns Acquisition Time to 0.1%
<1 ps Aperture Jitter
66 dB Feedthrough Rejection at 50 MHz
Low Spectral Noise Density
Test Instrumentation Equipment
RF Demodulation Systems
High Performance CCD Capture
Digital Sampling Oscilloscopes
Commercial and Military Radar
High-Speed DAC Deglitching
The performance of this device makes it an excellent front
end driver for a wide range of ADCs on the market today.
Significant improvements in dynamic performance can be
achieved by using this device ahead of virtually all ADCs that
do not have an internal track-and-hold.
GENERAL DESCRIPTION
The SPT9101 is a high-speed track-and-hold amplifier designed for a wide range of use. The SPT9101 is capable of
sampling at speeds up to 125 MSPS with resolutions ranging
from 8 to 12 bits. Trim programmable internal hold and
compensation capacitors provide for optimized input bandwidth and slew rate versus noise performance.
The SPT9101 is offered in 20-lead SOIC and LCC packages
over the industrial temperature range and in die form. Contact
the factory for military and /833 package options.
BLOCK DIAGRAM
VIn
Sampler
+
+ 4X
Amp
-
CHOLD
3R
R
CLK NCLK
RTN
VOUT
ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)1
Supply Voltages
Supply Voltage (+VS) ................................ -0.5 V to +6 V
Supply Voltage (-VS) ................................. -6 V to +0.5 V
Output Currents
Continuous Output Current ................................... 70 mA
Temperature
Operating Temperature .............................. -40 to +85 °C
Junction Temperature ......................................... +150 °C
Lead, Soldering (10 seconds) ............................. +220 °C
Storage ..................................................... -65 to +150 °C
Input Voltages
Analog Input Voltage ................................................ ±5 V
CLK, NCLK Input ....................................... -5 V to +0.5 V
Note 1: Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal
applied conditions in typical application.
ELECTRICAL SPECIFICATIONS
+VS=+5.0 V, -VS=-5.2 V, RLOAD=100 Ω, unless otherwise specified.
PARAMETERS
DC Performance
Gain ∆VIN = 0.5 V
TEST
CONDITIONS
TEST
LEVEL
+25 °C
Full Temp.
+25 °C
Full Temp.
+25 °C
Full Temp.
+25 °C
Full Temp.
I
VI
I
VI
V
V
VI
V
Full Temp.
V
Input Capacitance
Input Resistance
Full Temp.
+25 °C
Full Temp.
+25 °C
Full Temp.
VI
I
VI
V
VI
Clock Inputs
Input Bias Current
Input Low Voltage
Input High Voltage
+25 °C
Full Temp.
Full Temp.
VI
VI
VI
Offset ∆VIN = 0 V
Output Resistance
Output Short Circuit Current
PSRR ∆VS = 0.5 V p-p
Pedestal Sensitivity to Pos. Supply
∆VS = 0.5 V p-p
Pedestal Sensitivity to Neg. Supply
∆VS = 0.5 V p-p
Analog Input/Output
Maximum Output Voltage Range6
Input Bias Current
MIN
3.93
3.9
SPT9101
TYP
MAX
UNITS
4.07
4.1
±10
±30
0.5
±60
43
4
V/V
V/V
mV
mV
Ω
mA
dB
mV/V
8
mV/V
4.0
±3
37
±2.4
±2.7
±15
100
2
450
-1.0
3
-1.8
-0.8
±30
±35
30
-1.5
V
µA
µA
pF
kΩ
µA
V
V
Track Mode Dynamics
Bandwidth (-3 dB) VOut = 1.0 V p-p Full Temp.
Slew Rate 4 V Output Step
Full Temp.
Overdrive Recovery Time1
To 0.1%
Integrated Output Noise
BW = 5 to 200 MHz
IV
IV
V
V
Input RMS Spectral Noise
V
10 MHz
150
1100
180
1400
55
270
3.9
MHz
V/µs
ns
µV
nV
Hz
SPT9101
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ELECTRICAL SPECIFICATIONS
+VS=+5.0 V, -VS=-5.2 V, RLOAD=100 Ω, unless otherwise specified.
PARAMETERS
Hold Mode Dynamics
Worst Harmonic
VOut = 2 V p-p
Worst Harmonic
VOut = 2 V p-p
Worst Harmonic
VOut = 2 V p-p
Worst Harmonic
VOut = 2 V p-p
Sampling Bandwidth2
VIN = 0.5 V p-p
Hold Noise3 (RMS)
Droop Rate
Feedthrough Rejection (50 MHz)
VOut = 2 V p-p
Maximum Hold Time, VIN=0 V
Track-and-Hold Switching
Aperture Delay
Aperture Jitter
Pedestal Offset, VIN=0 V
Transient Amplitude
Settling Time to 4 mV
Glitch Product4
VIN = 0 V
Hold-to-Track Switching
Acquisition Time to 0.1%
2 V Output Step
Acquisition Time to 0.01%
2 V Output Step
Power Supply5
+VS Voltage
-VS Voltage
Power Dissipation
TEST
CONDITIONS
TEST
LEVEL
23 MHz, 50 MSPS
+25 °C
48 MHz, 100 MSPS
+25 °C
48 MHz, 100 MSPS
Full Temp.
48 MHz, 125 MSPS
+25 °C
-3 dB, +25 ˚C
MIN
SPT9101
TYP
V
-75
IV
-62
IV
MAX
UNITS
dB FS
-57
dB FS
-53
dB FS
V
-57
dB FS
V
350
MHz
+25 °C
VIN=0.0 V, +25 °C
Full Temp.
V
V
V
150 x tH
-40
-66
Full Temp.
IV
+25 °C
+25 °C
+25 °C
Full Temp.
VIN = 0 V, Full Temp.
Full Temp.
+25 °C
V
V
I
VI
V
V
V
-250
<1
±10
+25 °C
V
7
+25 °C
Full Temp.
IV
IV
11
14
16
Full Temp, Track Mode
Full Temp, Clocked Mode
Full Temp, Track Mode
Full Temp, Clocked Mode
Full Temp, Track Mode
Full Temp, Clocked Mode
VI
VI
VI
VI
VI
VI
54
44
54
44
551
449
65
55
65
55
663
561
100
mV/s
mV/µs
dB
200
ns
±25
±35
8
4
20
ps
ps rms
mV
mV
mV
ns
pV-s
ns
ns
ns
mA
mA
mA
mA
mW
mW
1 Time to recover within rated error band from 160% overdrive.
2 Sampling bandwidth is defined as the -3 dB frequency response of the input sampler to the hold capacitor when operating in the
sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier.
3 Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (tH) is 20 ns, the accumulated
noise is typically 3 µV (150 mV/s x 20 ns). This value must be combined with the track mode noise to obtain total noise.
4 Total energy of worst case track-to-hold or hold-to-track glitch.
ΘJC (LCC) = +6 °C/W
ΘJA (SOIC) = +85 °C/W in still air at +25 °C ambient.
5Clocked mode is specified with a 50% clock duty cycle.
6Analog input voltage should be limited ≤0.8 volts to maintain device in linear range.
Typical thermal impedances:
SPT9101
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12/30/99
TEST LEVEL CODES
TEST LEVEL
All electrical characteristics are subject to the
following conditions: All parameters having min/
max specifications are guaranteed. The Test
Level column indicates the specific device testing actually performed during production and
Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
Aperature
Delay
Figure 1 - Timing Diagram
Input
Acquisition
Time
Observed at
Hold Capacitor
Output
Observed at
Amplifier Output
CLK
Hold
Track
Track-to-Hold
Settling
Hold
NCLK
TIMING SPECIFICATION DEFINITIONS
TRACK-TO-HOLD SETTLING TIME
ACQUISITION TIME
The time required for the output to settle to within 4 mV of its
final value.
This is the time it takes the SPT9101 to acquire the analog
signal at the internal hold capacitor when it makes a transition
from hold mode to track mode. (See figure 1.) The acquisition
time is measured from the 50% input clock transition point to
the point when the signal is within a specified error band at the
internal hold capacitor (ahead of the output amplifier). It does
not include the delay and settling time of the output amplifier.
Because the signal is internally acquired and settled at the
hold capacitor before the output voltage has settled, the
sampler can be put in hold mode before the output has settled.
APERTURE DELAY
The aperture delay time is the interval between the leading
edge transition of the clock input and the instant when the
input signal was equal to the held value. It is the difference
in time between the digital hold switch delay and the analog
signal propagation time. Because the analog propagation
time is longer than the digital delay in the SPT9101, the
aperture delay is a negative value.
SPT9101
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Figure 2 - Typical Interface Circuit
+
+ 2.2 µF
2.2 µF
-A5.2
NOTES:
+A5
1) Vt = Threshold voltage:
a) For TTL or CMOS Clock input
15
VIN
RTN
10
-A5.2
11
IN+
X
4
Vt
18
+VS
Vt
b) For ECL Clock input
VOUT
-A5.2
3k
1k
Vt
6,7,16
2) Unless otherwise specified, all capacitors
are 0.01 or 0.1 µF, surface mount.
3) X = Termination (if required).
330
220
2
CLK IN
1k
3k
GND
330
-A5.2
VCC
+A5
9
VOUT
CLK NCLK
1,2
3
8
SPT9101
VIN
+A5
5
+VS
4
+VS
18
+VS
-VS
17
-VS
13
-VS
-VS
12
-A5.2
CLKIN
220
96850
R
8
VEE
4) CLKIN
a) TTL/CMOS
11
R
SPT, HCMP96850
IN-
LE
6
GND
1,16
b) ECL: Direct Input
12
THEORY OF OPERATION
CLOCK DRIVER CIRCUIT (CLK, NCLK PINS)
The SPT9101 is a monolithic 125 MSPS track and hold
amplifier built on a very high-speed complementary bipolar
process. It is pin and functionally compatible with the AD9101.
It is a two stage design with a sampler driving a hold capacitor
followed by a noninverting output buffer amplifier with gain of
4. The first stage sampler is based on a current amplifier in
noninverting gain of one configuration with inverting input
connected to the output. The hold switch is integrated into this
closed-loop first stage amplifier.
Fairchild highly recommends that a differential ECL clock be
used to drive the SPT9101. Both the 10KH and 100KH family
of ECL logic can be used. The typical interface diagram,
figure 2, shows the use of a SPT HCMP96850 high-speed
comparator. The comparator has a typical propagation delay
of 2.4 ns, very low offset of 3 mV, and a minimum tracking
bandwidth of 300 MHz. The comparator shown has been set
up in a feedthrough operation mode with latch enable connected to a logic high.
The output buffer amplifier is in a noninverting gain of 4
configuration with inverting input connected to a resistor
divider driven from the output. The noninverting input from the
hold capacitor employs input bias current cancellation which
results in excellent droop rate performance. The sampler and
amplifier stages both employ complementary current amplifiers for high-speed, low-distortion performance.
The threshold voltage (Vt) can be set using a resistor divider
as shown in note 1 of figure 2. The configuration shown in
note 1a is for a TTL/CMOS clock input and the configuration
shown in note 1b is for an ECL clock input. The differential
output of the comparator is directly fed to the SPT9101 clock
input. The comparator can also be driven with a sinewave
input, with the threshold voltage (Vt) adjusted to produce the
desired track/hold duty cycle ratio.
TYPICAL INTERFACE CIRCUIT
Note 4a shows the resistor divider configuration for a TTL/
CMOS clock input. If an ECL clock is used it can be directly
fed into the comparator.
BOOTSTRAP CAPACITOR
The SPT9101 does not require the bootstrap capacitor that is
required on the AD9101 between pins 3 and 19. Because
pins 3 and 19 are No Connects on the SPT9101, it will work
well in existing AD9101 sockets.
OUTPUT LEVEL SHIFTING (RTN PIN)
The RTN pin is tied to the output buffer amplifier internal
feedback resistor network as shown in the block diagram.
Normally this pin is tied to ground for a 4x gain output amplifier
configuration. However, this pin may be configured in other
ways as long as certain guidelines are met.
SPT9101
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12/30/99
The RTN pin may be tied to an external voltage to generate
an offset at the output. VOut must be kept to less than ±2.7 V
typical output swing. VOut, with an external reference voltage
at the RTN pin, is represented by the following formula:
SAMPLER FOR 12-BIT ADC APPLICATION
The SPT9101 was specifically designed for applications
where improved bandwidth performance is required. Figure 3
shows as simple block diagram of the SPT9101 as a sampler
ahead of the SPT7922 12-bit, 30 MSPS ADC.
VOut = 4 VIN - 3 VRef
where VRef = voltage at RTN pin and | VOut | ≤ 2.7 V
Figure 3 - Sampler for 12-Bit ADC
The following options are generally not recommended due to
the possibility of degraded noise performance of the device:
the RTN pin can also be tied to an external resistor to reduce
the gain but performance may degrade due to increased
noise from the external resistor. Also RTN can be left open for
unity gain mode, however, noise will increase.
VIN
In all cases, VIN must be kept to -0.5 V≤ VIN ≤ +0.5 V for rated
performance.
SPT9101
SPT7922
Clock 1
12
Clock 2
The graph below entitled Improved Dynamic Performance
Using the SPT9101 shows the performance with and without
the SPT9101. The SPT9101 significantly extends the dynamic performance range of the converter.
PERFORMANCE CHARACTERISTICS
SPT9101 Hold Mode Distortion vs. Temperature
Droop Rate vs Temperature
-65
Input Frequency = 50 MHz
Clock Frequency = 100 MHz
Hold = 4 ns
Track = 6 ns
40
dB
0
mV/us
-40
Worst Harmonic
-80
-120
-20
0
20
40
60
-60
-50
80
-25
0
50
75
100
Temperature (°C)
Temperature (°C)
SPT9101 Hold Mode Distortion vs Input Frequency
Improved Dynamic Performance Using the SPT9101
-75
70
-70
Worst Harmonic
SPT9101 & SPT7922
TDE (dB)
dB
25
-65
Clock Frequency = 100 MHz
Track = 6 ns
Hold = 4 ns
-60
60
SPT7922
50
(FS = 28 MSPS)
-55
1
10
40
100
Input Frequency (MHz)
5
10
15
20
FIN (MHz)
SPT9101
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PACKAGE OUTLINES
20-Lead LCC
A
H
SYMBOL
G
Bottom
View
B
C
Pin 1
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
A
.040 typ
1.02
B
C
.050 typ
0.055
1.27
1.40
0.045
1.14
D
E
F
0.345
0.054
0.360
0.066
.020 typ
8.76
1.37
9.14
1.68
0.51
G
H
0.022
0.028
0.075
0.56
0.71
1.91
F
D
E
20-Lead SOIC
SYMBOL
20
A B
1
INCHES
MIN
MAX
A
B
C
D
E
0.291
0.394
0.496
0.050 typ
0.014
0.299
0.419
0.512
F
0.004
G
H
I
0.093
0.009
0.016 .
MILLIMETERS
MIN
MAX
7.60
10.65
13.00
0.019
7.40
10.00
12.60
1.27 typ
0.35
0.012
0.10
0.30
0.104
0.013
0.050
2.35
0.23
0.40
2.65
0.32
1.27
0.49
C
G
F
H
D
I
E
SPT9101
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12/30/99
PIN ASSIGNMENTS
PIN FUNCTIONS
Name
RTN
+VS
GND
CLK
NCLK
-VS
N/C
VIN
VOUT
RTN
1
20
VOut
RTN
2
19
N/C
N/C
3
18
-VS
+VS
4
17
-VS
+VS
5
16
GND
GND
6
15
VIn
GND
7
14
N/C
+VS
8
13
-VS
+VS
9
12
-VS
CLK
10
11
NCLK
SOIC
RTN
RTN
N/C
1
2
3
VIN
N/C
20
16
VOut
GND
17
19
18
N/C
-VS
-VS
4
LCC
(Bottom View)
5
I/O
I
I
I
I
I
I
I
O
Function
Gain Set Resistor Return
+5 V Power Supply
Ground
True ECL T/H Clock
Complement ECL T/H Clock
-5.2 V Power Supply
No Connection
Analog Signal Input
Analog Signal Output
+VS
+VS
6
GND
15
7
GND
14
8
+VS
12
11
10
9
-VS
-VS
NCLK
CLK
+VS
13
ORDERING INFORMATION
PART NUMBER
SPT9101SIS
SPT9101SIC
SPT9101SCU
PACKAGE TYPE
20L SOIC
20L LCC
Die*
TEMPERATURE RANGE
-40 to +85 °C
-40 to +85 °C
+25 °C
*Please see die specification for guranteed electrical performance.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF
ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF
OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system
whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
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SPT9101
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12/30/99