www.fairchildsemi.com KH232 Low Distortion Wideband Op Amp Features ■ ■ ■ ■ ■ ■ ■ General Description -69dBc 2nd and 3rd harmonics at 20MHz -3dB bandwidth of 270MHz 0.05% settling in 15ns 3000V/µs slew rate 1mV input offset voltage, 10µV/°C drift ±10V, 100mA max output Direct replacement for CLC232 Applications ■ ■ ■ ■ ■ ■ ■ Flash A/D drivers DAC current-to-voltage conversion Wide dynamic range IF amps VCO drivers DDS postamps Radar/communication receivers Precision line drivers The KH232 is a wideband low distortion operational amplifier designed specifically for high speed, low gain applications requiring wide dynamic range. Utilizing a current feedback architecture, the KH232 offers high speed performance while maintaining DC precision. The KH232 offers precise gains from ±1 to ±5 with a true 0.1% linearity and provides stable, oscillationfree operation across the entire gain range without external compensation. The KH232, a pin compatible enhanced version of the KH231, reduces 2nd and 3rd harmonic distortion to an extremely low -69dBc at 20MHz (2Vpp, RL = 100Ω). Additional features provided by the KH232 include a small signal bandwidth of 270MHz, a large signal bandwidth of 95MHz and a 3000V/µs slew rate. The input offset voltage is typically 1mV with an input offset drift of 10µV/°C. The KH232 combines these high performance features with its 0.05% settling time of 15ns and its 100mA drive capability to provide high speed, high resolution A/D and D/A converter systems with an attractive solution for driving and buffering. Wide dynamic range systems such as radar and communication receivers requiring low harmonic distortion and low noise will find the KH232 to be an excellent choice. As a line driver, the KH232 set at a gain of 2 cancels matched line losses. The KH232 is constructed using thin film resistor/bipolar transistor technology, and is available in the following versions: Bottom View ICC Adjust Case ground GND 7 Adjust -VCC 8 Supply Voltage V+ 6 Inverting Input V- 5 Not Connected NC 4 10 + 4 - 4 GND 2 Collector Supply 11 Vo Output 12 Collector Supply +VCC 3 Case ground -25°C to +85°C -55°C to +125°C KH232AM -55°C to +125°C KH232HXC KH232HXA -55°C to +125°C -55°C to +125°C 9 -VCC Non-Inverting Input KH232AI KH232AK 1 Adjust +VCC Supply Voltage Typical Performance ICC Adjust Gain Setting Parameter Pins 2 and 8 are used to adjust the supply current or to adjust the offset voltage (see text). These pins are normally left unconnected. 12-pin TO-8 can 12-pin TO-8 can, features burn-in & hermetic testing 12-pin TO-8 can, environmentally screened and electrically tested to MIL-STD-883 SMD#: 5962-9166501HXC SMD#: 5962-9166501HXA 1 2 5 -1 -2 -5 -3dB bandwidth 430 270 135 220 175 110 rise time (2V) 1.8 2.0 2.5 2.0 2.2 2.9 slew rate 2.5 3.0 3.0 3.0 3.0 3.0 settling time (to 0.1%) 12 12 12 12 12 15 Units MHz ns V/ns ns REV. 1A February 2001 DATA SHEET KH232 KH232 Electrical Characteristics (TA = +25°C, Av = +2V, VCC = ±15V, RL = 100Ω, Rf = 250Ω; unless specified) PARAMETERS CONDITIONS Ambient Temperature KH232AI +25°C -25°C +25°C +85°C Ambient Temperature KH232AK/AM/HXC/HXA +25°C -55°C +25°C +125°C 270 165 95 >200 >145 >80 >200 >145 >80 0.1 0.1 0.4 3.5 ± 0.5 0.5 <0.6 <1.5 <0.6 – <2.0 53 36 FREQUENCY DOMAIN RESPONSE ✝ -3dB bandwidth (note 2) ✝ ✝ ✝ large-signal bandwidth gain flatness (note 2) peaking peaking rolloff group delay linear phase deviation reverse isolation non-inverting inverting TIME DOMAIN RESPONSE rise and fall time settling time to 0.05% to 0.1% overshoot slew rate (overdriven input) overload recovery <50ns pulse, 200% overdrive NOISE AND DISTORTION RESPONSE ✝ 2nd harmonic distortion ✝ 3rd harmonic distortion equivalent input noise voltage inverting current non-inverting current noise floor integrated noise integrated noise STATIC, DC PERFORMANCE * input offset voltage average temperature coefficient * input bias current average temperature coefficient * input bias current average temperature coefficient * power supply rejection ratio common mode rejection ratio * supply current MISCELLANEOUS PERFORMANCE non-inverting input resistance non-inverting input capacitance output impedance output voltage range UNITS SYM >200 >120 >60 MHz MHz MHz SSBW SSBW FPBW <0.3 <0.3 <0.6 – <2.0 <0.6 <0.8 <1.0 – <2.0 dB dB dB ns ° GFPL GFPH GFR GD LPD >43 >26 >43 >26 >43 >26 dB dB RINI RIIN 2.0 5.0 15 12 5 3.0 <2.4 <7.0 – <22 <15 >2.5 <2.3 <6.5 – <17 <10 >2.5 <2.7 <6.5 – <22 <15 >1.8 ns ns ns ns % V/ns TRS TRL TS TSP OS SR 120 – – – ns OR 2Vpp, 20MHz 2Vpp, 20MHz -69 -69 <-64 <-64 <-64 <-64 <-56 <-64 dBc dBc HD2 HD3 >100kHz >100kHz >100kHz >100kHz 1kHz to 200MHz 5MHz to 200MHz 2.8 20 2.3 -155 57 57 <3.2 <23 <2.6 <-154 <64 <64 <3.2 <23 <2.6 <-154 <64 <64 <3.5 <25 <2.9 <-153 <72 <72 1 10 5.0 50 10 125 50 46 25 <4.0 <25 <29 <125 <31 <200 >45 >40 <27 <2.0 <25 <21 <125 <15 <200 >45 >40 <27 <4.5 <25 <31 <125 < 35 <200 >45 >40 <29 mV µV/°C µA nA/°C µA nA/°C dB dB mA VIO DVIO IBN DIBN IBI DIBI PSRR CMRR ICC 400 1.3 5, 37 ±12 >100 <2.5 – >±11 >200 <2.5 – >±11 >400 <2.5 – >±11 kΩ pF Ω, nH V RIN CIN RO VO Vo ≤0.63Vpp Vo ≤2Vpp Vo ≤10Vpp Vo ≤0.63Vpp 0.1 to 50MHz >50MHz at 100MHz to 100MHz to 100MHz 2V step 10V step 5V step 2.5V step 5V step TYP MIN & MAX RATINGS <1% error non-inverting inverting no load DC @ 100MHz no load VN nV/√Hz ICN pA/√Hz pA/√Hz NCN dBm(1Hz) SNF µVrms INV µVrms INV Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings Recommended Operating Conditions VCC Io common mode input voltage, Vo VCC Io common mode input voltage gain range differential input voltage thermal resistance junction temperature operating temperature storage temperature lead temperature (soldering 10s) 2 ±20V ±100mA |VCC| >15V ±(30-|VCC|)V |VCC| ≤15V ±|VCC|V ±3V (see thermal model) +175°C AI: -25°C to +85°C AK/AM/HXC/HXA: -55°C to +125°C -65°C to +150°C +300°C note 1: note 2: ±5V to ±15V ±75mA ±(|VCC| -5)V ±1 to ±5 * ✝ AI/AK/AM/HXC/HXA 100% tested at +25°C AK/AM/HXC/HXA 100% tested at +25°C and sample tested at -55°C and +125°C ✝ AI sample tested at +25°C The output amplitude used in testing is 0.63Vpp. Performance is guaranteed for conditions listed. REV. 1A February 2001 KH232 DATA SHEET KH232 Typical Performance Characteristics (T A Inverting Frequency Response Av = 5 Av = 5 Av = 2 Av = 1 0 150 30 Av = -2 Phase (45 deg/div) Av = 2 Phase 70 Rs Phase Av = -5 Av = -5 Av = -1 Av = -1 Av = -2 Settling Time (ns) Av = 1 Settling Time vs. CL 35 Gain CL 25 60 1k 50 Av = +2 RS 40 20 TS 15 30 10 20 10 5 0 300 150 Frequency (MHz) Frequency (MHz) Bandwidth vs. VCC 1000 100 0 300 RS (Ω) Normalized Magnitude (1dB/div) Gain Phase (45 deg/div) Normalized Magnitude (1dB/div) Non-Inverting Frequency Response = +25°C, Av = +2, VCC = ±15V, RL = 100Ω, Rf = 250Ω; unless specified) CL (pF) Frequency Response vs. RL Large Signal Non-Inverting Gain & Phase 1.2 Av = 2 Vo = 10Vpp RL = 500 (1dB/div) Pins 1 and 2 Shorted Pins 8 and 9 shorted 0.8 (1dB/div) 1.0 RL = 100 RL = 50 Phase (45 deg/div) Relative Bandwidth Gain RL = 200 Phase 0.6 Av = 2 0.4 4 6 8 10 12 14 16 0 150 ±VCC (V) 0 300 150 Frequency (MHz) 2nd Harmonic Distortion 2nd and 3rd Harmonic Distortion 3rd Harmonic Distortion -20 -20 -30 -30 300 Frequency (MHz) -40 Vo = 2Vpp -45 8Vpp -50 4Vpp -60 -70 Distortion (dBc) -40 Distortion (dBc) -40 8Vpp -50 4Vpp -60 -70 2Vpp 2Vpp -80 -80 1Vpp 100 10 Interdept Point (dBm) CMRR and PSRR 40 35 30 25 20 15 PSRR Inverting Current 20pA/√Hz 10 10 Voltage 2.8nV/√Hz Non-Inverting Current 2.3pA/√Hz 1 40 50 60 70 80 90 100 100 1k 10k 100k 1M 10M Noise Current (pA/√Hz) 50Ω 100 100 Pout Noise Voltage (nV/√Hz) 50Ω 30 10 Frequency (MHz) 100 20 3rd 1 Equivalent Input Noise 2-Tone, 3rd Order Intermod. Intercept 10 -75 Frequency (Hz) 50 0 -70 100 10 1 Frequency (Hz) 45 -65 -90 -90 1 -60 -85 1Vpp -90 2nd -55 -80 50 PSRR/CMRR (dB) Distortion (dBc) -50 CMRR 40 30 20 10 1 100M 1 Small Signal Pulse Response 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Frequency (MHz) Settling Time Large Signal Pulse Response Av = -2 0.15 Av = 2 Av = -2 Settling Error (%) Av = 2 Output Voltage (2V/div) Output Voltage (400mV/div) 0.20 0.10 5ns/div 0.05 0 -0.05 50ns/div -0.10 -0.15 -0.20 Time (5ns/div) REV. 1A February 2001 Time (5ns/div) Time (ns) 3 DATA SHEET KH232 Operation The KH232 is based on the current feedback op amp topology, a design that uses current feedback instead of the usual voltage feedback. The use of the KH232 is basically the same as that of the conventional op amp (see Figures 1 and 2). Since the device is designed specifically for low gain applications, the best performance is obtained when the circuit is used at gains between ±1 and ±5. Additionally, performance is optimum when a 250Ω feedback resistor is used. 33Ω +15V 3.9 0.1 .01 Capactance in µF 6 Vin + 12 KH232 Rg Ri 49.9Ω 1 5 11 Vo 10 - 3,7 250Ω 9 RL 100Ω 33Ω -15V 3.9 0.1 A v = 1+ .01 Rf Rg Rf = 250Ω Figure 1: Recommended non-inverting gain circuit +15V 3.9 33Ω 0.1 .01 Capactance in µF 100Ω Rg Vin 6 1 + 12 KH232 5 - 3,7 9 Ri 11 Vo 10 250Ω 33Ω -15V 3.9 0.1 .01 RL 100Ω Rf Av = − Rg Rf = 250Ω For Zin = 50Ω, select Rg || Ri = 50Ω Figure 2: Recommended inverting gain circuit 4 Layout Considerations To assure optimum performance the user should follow good layout practices which minimize the unwanted coupling of signals between nodes. During initial breadboarding of the circuit use direct point to point wiring, keeping the lead lengths to less than 0.25”. The use of solid, unbroken ground plane is helpful. Avoid wire-wrap type pc boards and methods. Sockets with small, short pin receptacles may be used with minimal performance degradation although their use is not recommended. During pc board layout keep all traces short and direct The resistive body of Rg should be as close as possible to pin 5 to minimize capacitance at that point. For the same reason, remove ground plane from the vicinity of pins 5 and 6. In other areas, use as much ground plane as possible on one side of the board. It is especially important to provide a ground return path for current from the load resistor to the power supply bypass capacitors. Ceramic capacitors of 0.01 to 0.1µf (with short leads) should be less than 0.15 inches from pins 1 and 9. Larger tantalum capacitors should be placed within one inch of these pins. VCC connections to pins 10 and 12 can be made directly from pins 9 and 1, but better supply rejection and settling time are obtained if they are separately bypassed as in figures 1 and 2. To prevent signal distortion caused by reflections from impedance mismatches, use terminated microstrip or coaxial cable when the signal must traverse more than a few inches. Since the pc board forms such an important part of the circuit, much time can be saved if prototype boards of any high frequency sections are built and tested early in the design phase. Evaluation boards designed for either inverting or non-inverting gains are available. Offset Voltage Adjustment If trimming of the input offset voltage (Vos = Vni -Vin) is desired, a resistor value of 10kΩ to 1MΩ placed between pins 8 and 9 will cause Vos to become more negative by 8mV to 0.2mV respectively. Similarly, a resistor placed between pins 1 and 2 will cause Vos, to become more positive. Thermal Considerations At high ambient temperatures or large internal power dissipations, heat sinking is required to maintain acceptable junction temperatures. Use the thermal model on the previous page to determine junction temperatures. Many styles of heat sinks are available for TO-8 packages; the Thermalloy 2240 and 2268 are good examples. Some heat sinks are the radial fin type which cover the pc board and may interfere with external components. An excellent solution to this problem is to use surface mounted resistors and capacitors. They have a very low profile and actually improve high frequency performance. For use of these heat sinks with conventional components, a 0.1” high spacer can be inserted under the TO-8 package to allow sufficient clearance. REV. 1A February 2001 KH232 DATA SHEET Tcase 100°C/W Tj(pnp) Ppnp 100°C/W Tj(npn) Pnpn 48°C/W θca Tj(circuit) Pcircuit + Tambient P(circuit) = (ICC)((+VCC) – (VCC)) where ICC = 14mA at ±15V P(xxx) = [(±VCC) – Vout – (Icol) (Rcol + 4)] (Icol) (%Duty) For positive Vo and VCC, this is the power in the npn device. For negative Vo and VCC, this is the power in the pnp device. Icol = Vo/RL or 12mA, whichever is greater. (Include feedback R in RL.) Other methods of heat sinking may be used, but for best results, make contact with the base of the KH232 package, use a large thermal capacity heat sink and use forced air convection. Low VCC Operation: Supply Current Adjustment The KH232 is designed to operate on supplies as low as ±5V. In order to improve full bandwidth at reduced supply voltages, the supply current (ICC) must be increased. The plot of Bandwidth vs. VCC, shows the effect of shorting pins 1 and 2 and pins 8 and 9; this will increase both bandwidth and supply current. Care should be taken to not exceed the maximum junction temperatures; for this reason this technique should not be used with supplies exceeding ±10V. For intermediate values of VCC, external resistors between pins 1 and 2 and pins 8 and 9 can be used. Rcol is a resistor (33Ω recommended) between the xxx collector and ±VCC. The limiting factor for output current and voltage is junction temperature. Of secondary importance is I(out), which should not exceed 150mA. Tj(pnp) = P(pnp) (100 + θca) + (P(cir) + P(npn))(θca) + Ta, similar for Tj(npn). Tj(cir) = P(cir)(48 + θca) + (P(pnp) + P(npn))(θca) + Ta. θca = 65°C/W for the KH232 without heat sink in still air. 35°C/W for the KH232 with a Thermalloy 2268A heat sink in still air. 15°C/W for the KH232 with a Thermalloy 2268A heat sink at 300 ft/min air. (Thermalloy 2240A works equally as well.) For example, with the KH232 operating at ±15V while driving a 100Ω load at 15Vpp output (50% duty cycle pulse waveform, DC = 0), P(npn) = P(pnp) = 190mW (Rcol = 33) and P(cir) = 0.42W. Then with the Thermalloy 2268 heat sink and air flow of 300 ft/min the output transistors’ Tj is 31°C above ambient and worst case Tj in the rest of the circuit is 32°C above ambient. In still air, however, the rise in Tj is 47°C and 48°C, respectively. With no heat sink, the rise in Tj is 71°C and 72°C, respectively! Under most conditions, HEAT SINKING IS REQUIRED. REV. 1A February 2001 5 DATA SHEET KH232 KH232 Package Dimensions L A e1 e2 7 φD e D1 8 9 6 10 5 11 4 12 k φb 3 2 1 α F k1 TO-8 SYMBOL INCHES Minimun Maximum MILIMETERS Minimum Maximum A 0.142 0.181 3.61 4.60 φb 0.016 0.019 0.41 0.48 φD 0.595 0.605 15.11 15.37 φD1 0.543 0.555 13.79 14.10 e 0.400 BSC 10.16 BSC e1 0.200 BSC 5.08 BSC e2 0.100 BSC 2.54 BSC F 0.016 0.030 0.41 0.76 k 0.026 0.036 0.66 0.91 k1 0.026 0.036 0.66 0.91 L 0.310 0.340 7.87 8.64 α 45° BSC NOTES: Seal: cap weld Lead finish: gold per MIL-M-38510 Package composition: Package: metal Lid: Type A per MIL-M-38510 45° BSC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2001 Fairchild Semiconductor Corporation