OPA699 OPA 699 SBOS261B – NOVEMBER 2002 – REVISED OCTOBER 2003 Wideband, High Gain VOLTAGE LIMITING AMPLIFIER FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● TRANSIMPEDANCE WITH FAST OVERDRIVE RECOVERY ● FAST LIMITING ADC INPUT DRIVER ● LOW PROP DELAY COMPARATOR ● NONLINEAR ANALOG SIGNAL PROCESSING ● DIFFERENCE AMPLIFIER ● IF LIMITING AMPLIFIER ● OPA689 UPGRADE HIGH LINEARITY NEAR LIMITING FAST RECOVERY FROM OVERDRIVE: 1ns LIMITING VOLTAGE ACCURACY: ±10mV –3dB BANDWIDTH (G = +6): 260MHz GAIN BANDWIDTH PRODUCT: 1000MHz STABLE FOR G ≥ +4V/V SLEW RATE: 1400V/µs ±5V AND +5V SUPPLY OPERATION LOW GAIN VERSION: OPA698 DESCRIPTION the signal channel. Implementing the limiting function at the output, as opposed to the input, gives the specified limiting accuracy for any gain, and allows the OPA699 to be used in all standard op amp applications. The OPA699 is a wideband, voltage-feedback op amp that offers bipolar output voltage limiting, and is stable for gains ≥ +4. Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new output limiting architecture holds the limiter offset error to ±10mV. The op amp operates linearly to within 20mV of the limits. Nonlinear analog signal processing circuits will benefit from the OPA699 sharp transition from linear operation to output limiting. The quick recovery time supports high-speed applications. The OPA699 is available in an industry-standard pinout in an SO-8 package. For lower gain applications requiring output limiting with fast recovery, consider the OPA698. The combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within 100mV of the desired linear output range. A fast 1ns recovery from limiting ensures that overdrive signals will be transparent to +5V VH OPA699 VOUT VL VOUT = –2VIN –5V RG 374Ω RF 750Ω VIN CS 18pF CF 4pF Low Gain, Improved SFDR Amplifier with Output Limiting Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2002-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage ................................................................................. ±6.5V Internal Power Dissipation ........................... See Thermal Characteristics Input Voltage Range ............................................................................ ±VS Differential Input Voltage ..................................................................... ±VS Limiter Voltage Range ........................................................... ±(VS – 0.7V) Storage Temperature Range: D ..................................... –40°C to +125°C Lead Temperature (SO-8, soldering, 3s) ...................................... +260°C Junction Temperature .................................................................... +150°C ESD Resistance: HBM .................................................................... 2000V MM ........................................................................ 200V CDM ................................................................... 1000V This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. RELATED PRODUCTS SINGLES DUALS DESCRIPTION Output Limiting OPA698 Unity Gain Stable, Wideband Voltage Feedback OPA690 OPA2690 High Slew, Unity Gain Stable PACKAGE/ORDERING INFORMATION PRODUCT OPA699 " PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY SO-8 D –40°C to +85°C OPA699ID " " " " OPA699ID OPA699IDR Rails, 100 Tape and Reel, 2500 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATION Top View SO NC 1 8 VH Inverting Input 2 7 +VS Noninverting Input 3 6 Output –VS 4 5 VL NC = No Connection 2 OPA699 www.ti.com SBOS261B ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. G = +6, RF = 750Ω, RL = 500Ω, and VH = –VL = 2V, (see Figure 1 for AC performance only), unless otherwise noted. OPA699ID TYP PARAMETER AC PERFORMANCE (see Figure 1) Small Signal Bandwidth (VO < 0.5VPP) Gain Bandwidth Product (G ≥ +20) Gain Peaking 0.1dB Gain Flatness Bandwidth Large-Signal Bandwidth Step Response Slew Rate Rise-and-Fall Time Settling Time: 0.05% Spurious-Free Dynamic Range, Even Odd Differential Gain Differential Phase Input Noise Density Voltage Noise Current Noise DC PERFORMANCE (VCM = 0V) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(4) Average Drift Input Offset Current Average Drift INPUT Common-Mode Rejection Ratio Common-Mode Input Range(5) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power-Supply Rejection Ratio +PSRR (Input Referred) MIN/MAX OVER TEMPERATURE CONDITIONS +25°C +25°C(1) 0°C to 70°C(2) –40°C to +85°C(2) G = +6 G = +12 G = –6 VO < 0.5VPP, G = +6 VO < 0.5VPP, G = +4 VO < 0.5VPP VO = 4VPP 260 86 269 1000 7.5 30 290 220 215 210 820 800 750 190 180 170 4V Step 0.5V Step 2V Step f = 5MHz, VO = 2VPP f = 5MHz, VO = 2VPP NTSC, PAL, RL = 500Ω NTSC, PAL, RL = 500Ω 1400 1.6 8 67 87 0.012 0.008 1300 1.65 1200 1.8 1100 2 64 85 62 84 60 80 f ≥ 1MHz f ≥ 1MHz 4.1 2.0 4.6 2.5 5.2 2.7 VO = ±0.5V 66 ±1.5 — +3 — ±0.3 — 58 Input Referred, VCM = ±0.5V 61 ±3.3 ±5.0 ±10 ±2 55 ±3.2 G = +4, f < 100kHz VS = ±5V VS = ±5V +VS = 4.5V to 5.5V ±4.1 +120 –120 0.8 ±3.9 +90 –90 min typ typ min typ typ min B C C B C C B V/µs ns ns dB dB % ° min max typ min min typ typ B B C B B C C 5.5 2.9 nV/√Hz pA/√Hz max max B B 56 ±6 ±15 ±11 ±15 ±2.5 ±10 55 ±7 ±20 ±12 ±20 ±3 ±10 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B 54 ±3.2 52 ±3.1 dB V min min A A MΩ || pF MΩ || pF typ typ C C V mA mA Ω min min min typ A A A C ±3.9 +85 –85 ±3.8 +80 –80 ±6 16.6 14.6 V V mA mA typ max max min C A A A 66 dB min A ±5 — 15.5 15.5 15.9 15.2 ±6 16.3 14.9 75 68 67 ±6 MIN/ TEST MAX LEVEL(3) MHz MHz MHz MHz dB MHz MHz 0.32 || 1 3.5 || 1 VH = –VL = 4.3V RL ≥ 500Ω UNITS NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambient temperature + 23°C at high temperature limit Test Level A specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperature tested specifications. (3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (4) Current is considered positive out-of-node. (5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (6) IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3 and Figures 1 and 12. (7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or V L) when VIN = 0. OPA699 SBOS261B www.ti.com 3 ELECTRICAL CHARACTERISTICS: VS = ±5V (Cont.) Boldface limits are tested at +25°C. G = +6, RF = 750Ω, RL = 500Ω, VH = –VL = 2V, (Figure 1 for AC performance only), unless otherwise noted. OPA699ID TYP PARAMETER OUTPUT VOLTAGE LIMITERS Output Voltage Limited Range Default Limit Voltage, Upper Lower Minimum Limiter Separation (VH – VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude(6) Maximum Minimum Average Drift Limiter Input Impedance Limiter Feedthrough(7) DC Performance in Limit Mode Limiter Offset Voltage Op Amp Input Bias Current Shift(4) AC Performance in Limit Mode Limiter Small-Signal Bandwidth Limiter Slew Rate(8) Limited Step Response Overshoot Recovery Time Linearity Guardband(9) THERMAL CHARACTERISTICS Temperature Range Thermal Resistance D SO-8 CONDITIONS MIN/MAX OVER TEMPERATURE +25°C +25°C(1) 0°C to 70°C(2) –40°C to +85°C(2) UNITS ±3.8 +3.5 –3.5 400 — +3.3 –3.3 400 ±4.3 +3.2 –3.2 400 ±4.3 +3.1 –3.1 400 ±4.3 V V mV V typ min max min max C A A B B 50 50 — 3.4 || 1 –60 60 40 62 38 30 64 36 35 µA µA nA/°C MΩ || pF dB max min max typ typ A A B C C ±10 3 ±30 ±35 ±40 mV µA max typ A C MHz V/µs typ typ C C mV ns mV typ max typ C B C MIN/ TEST MAX LEVEL(3) Pins 5 and 8 Limiter Pins Open VO = 0 f = 5MHz VIN = ±0.7V (VO – VH) or (VO – VL) Linear ↔ Limited Operation VIN = ±0.7V, VO < 0.02VPP 600 125 VIN = 0V to ±0.7V Step VIN = ±0.7V to 0V Step f = 5MHz, VO = 2VPP 250 1 30 Specification, I Junction-to-Ambient –40 to +85 °C typ C 125 °C/W typ C 1.9 2 2.1 NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambient temperature +23°C at high temperature limit Test Level A specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperature tested specifications. (3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (4) Current is considered positive out-of-node. (5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (6) IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3 and Figures 1 and 12. (7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0. (8) VH slew rate conditions are: VIN = +0.7V, G = +6, VL = –2V, VH = step between 2V and 0V. VL slew rate conditions are similar. (9) Linearity Guardband is defined for an output sinusoid (f = 1MHz, VO = 2VPP) centered between the limiter levels (VH and V L). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8). 4 OPA699 www.ti.com SBOS261B ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. G = +6, RF = 750Ω, RL = 500Ω tied to VCM = +2.5V, VL = VCM –1.2V, and VH = VCM +1.2V, (see Figure 2 for AC performance only), unless otherwise noted. OPA699ID TYP PARAMETER AC PERFORMANCE (see Figure 2) Small Signal Bandwidth (VO < 0.5VPP) Gain Bandwidth Product (G ≥ +20) Gain Peaking 0.1dB Gain Flatness Bandwidth Large-Signal Bandwidth Step Response Slew Rate Rise-and-Fall Time Settling Time: 0.05% Spurious-Free Dynamic Range, Even Odd Input Noise Voltage Noise Density Current Noise Density DC PERFORMANCE Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(4) Average Drift Input Offset Current Average Drift INPUT Common-Mode Rejection Ratio Common-Mode Input Range(5) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power-Supply Rejection Ratio +PSRR (Input Referred) MIN/MAX OVER TEMPERATURE CONDITIONS +25°C +25°C(1) 0°C to 70°C(2) –40°C to +85°C(2) G = +6 G = +12 G = –6 VO < 0.5VPP VO < 0.5VPP, G = +4 VO < 0.5VPP, G = +6 VO = 2VPP 234 83 242 880 8 30 250 200 190 180 700 650 600 200 190 180 2V Step 0.5V Step 2V Step f = 5MHz, VO = 2VPP f = 5MHz, VO = 2VPP 1050 1.75 8 64 70 850 1.8 800 1.9 700 2.1 61 69 60 67 f ≥ 1MHz f ≥ 1MHz 4.2 2.1 4.6 2.6 VO = VCM ± 0.5V 66 ±2 — +3 — ±0.4 — 56 ±10 58 VCM ±0.8 54 VCM ±0.7 Input Referred, VCM ±0.5V ±6 ±2 G = +4, f < 100kHz VS = +5V VS = +5V VS = 4.5V to 5.5V VCM ±1.6 +70 –70 0.2 5 — 14.3 14.3 70 MIN/ TEST MAX LEVEL(3) MHz MHz MHz MHz dB MHz MHz min typ typ min typ typ min B C C B C C B 58 65 V/µs ns ns dB dB min max typ min min B B C B B 5.2 2.8 5.6 3.0 nV/√Hz pA/√Hz max max B B 54 ±7 ±14 ±11 ±25 ±2.5 ±15 53 ±8 ±14 ±12 ±25 ±3 ±15 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B 53 VCM ±0.7 52 VCM ±0.6 dB V MΩ || pF min min typ A A C MΩ || pF typ C V mA mA Ω min min min typ A A A C V V mA mA typ max max min C A A A dB typ C 0.32 || 1 3.5 || 1 VH = VCM + 1.8V, VL = VCM – 1.8V RL ≥ 500Ω UNITS VCM ±1.4 +60 –60 VCM ±1.4 +55 –55 VCM ±1.3 +50 –50 +12 14.9 13.6 +12 15.1 13.4 +12 15.3 13.2 NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambient temperature +23°C at high temperature limit Test Level A specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperature tested specifications. (3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (4) Current is considered positive out of node. (5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (6) IVH (VH bias current) is negative, and IVL (VL bias current) is positive, under these conditions. See Note 3 and Figures 2 and 12. (7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or V L) when VIN = 0. (8) VH slew rate conditions are: VIN = VCM +0.4V, G = +6, VL = V CM –1.2V, VH = step between VCM +1.2V and VCM. VL slew rate conditions are similar. (9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, VO = VCM ±1VPP) centered between the limiter levels (VH and V L). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8). OPA699 SBOS261B www.ti.com 5 ELECTRICAL CHARACTERISTICS: VS = +5V (Cont.) Boldface limits are tested at +25°C. G = +6, RF = 750Ω, RL = 500Ω tied to VCM = +2.5V, VL = VCM –1.2V, and VH = VCM +1.2V, (see Figure 2 for AC performance only), unless otherwise noted. OPA699ID TYP PARAMETER OUTPUT VOLTAGE LIMITERS Maximum Limited Voltage Minimum Limited Voltage Default Limiter Voltage Minimum Limiter Separation (VH – VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude(6) Limiter Input Impedance Limiter Isolation(7) DC Performance in Limit Mode Limiter Voltage Accuracy Op Amp Bias Current Shift(4) AC Performance in Limit Mode Limiter Small-Signal Bandwidth Limiter Slew Rate(8) Limited Step Response Overshoot Recovery Time Linearity Guardband(9) THERMAL CHARACTERISTICS Temperature Range Thermal Resistance D SO-8 +25°C CONDITIONS Limiter Pins Open VO = 2.5V f = 5MHz VIN = VCM ±0.4V (VO – VH) or (VO – VL) Linear ↔ Limited Operation +3.9 +1.1 VCM ±1.1 400 — –15 3.4 || 1 –60 ±15 5 MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) –40°C to +85°C(2) VCM ±0.9 400 VCM ±1.8 VCM ±0.8 400 VCM ±1.8 VCM ±0.7 400 VCM ±1.8 ±30 ±35 ±40 UNITS MIN/ TEST MAX LEVEL(3) V V V mV V µA MΩ || pF dB typ typ min min max typ typ typ C C B B B C C C mV µA max typ A C VIN = ±0.4V, VO < 0.02VPP 450 100 MHz V/µs typ typ C C VIN = VCM to VCM ±0.4V Step VIN = VCM ±0.4V to VCM Step f = 5MHz, VO = 2VPP 55 3 30 mV ns mV typ typ typ C C C Specification, I Junction-to-Ambient –40 to +85 °C typ C 125 °C/W typ C NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambient temperature +23°C at high temperature limit Test Level A specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperature tested specifications. (3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (4) Current is considered positive out of node. (5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (6) I VH (VH bias current) is negative, and IVL (VL bias current) is positive, under these conditions. See Note 3 and Figures 2 and 12. (7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V H (or V L) when VIN = 0. (8) VH slew rate conditions are: VIN = VCM +0.4V, G = +6, VL = VCM –1.2V, VH = step between VCM +1.2V and VCM. VL slew rate conditions are similar. (9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, V O = VCM ±1VPP) centered between the limiter levels (VH and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8). 6 OPA699 www.ti.com SBOS261B TYPICAL CHARACTERISTICS: VS = ±5V TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted. INVERTING SMALL-SIGNAL FREQUENCY RESPONSE NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 9 G = +4 VO = 0.5VPP 6 Normalized Gain (dB) Normalized Gain (dB) G = +6 3 0 −3 G = +12 −6 −9 G = +20 −12 −3 G = −12 −6 −9 −12 See Figure 3 −18 1M 10M 100M 1M 1G 100M Frequency (Hz) NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 18 G = −6 VO = 1VPP G = +6 15 12 Gain (dB) VO = 4VPP VO = 7VPP 9 1G VO = 1VPP 15 VO = 2VPP 6 VO = 2VPP VO = 4VPP 12 VO = 7VPP 9 6 See Figure 1 See Figure 3 3 3 1M 10M 100M 1G 1M 10M 100M Frequency (Hz) Frequency (Hz) VH—LIMITER SMALL-SIGNAL FREQUENCY RESPONSE VL—LIMITER SMALL-SIGNAL FREQUENCY RESPONSE 1G 3 3 VO = 0.02VPP VO = 0.02VPP 0 Limiter Gain (dB) 0 Limiter Gain (dB) 10M Frequency (Hz) 18 Gain (dB) G = −6 0 −15 See Figure 1 −15 G = −4 VO = 0.5VPP 3 0.02VPP + 2.0VDC 0.7VDC 125Ω –3 VH VO OPA699 VL –3 VH VO OPA699 VL 0.02VPP + 2.0VDC –6 Open –6 Open 0.7VDC 125Ω 150Ω 750Ω 150Ω 750Ω –9 –9 1M 10M 100M 1M 1G OPA699 SBOS261B 10M 100M 1G Frequency (Hz) Frequency (Hz) www.ti.com 7 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted. LARGE-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE 2.5 0.4 VO = 0.5VPP VO = 4VPP VH = –VL = 2.5V 2.0 0.3 1.5 0.2 1.0 VOUT (V) VOUT (V) 0.1 0 –0.1 0.5 0 –0.5 –1.0 –0.2 –1.5 –0.3 –2.0 See Figure 1 Time (5ns/div) Time (5ns/div) VL—LIMITED PULSE RESPONSE VH—LIMITED PULSE RESPONSE 2.5 2.5 VOUT 1.5 1.0 VIN 0.5 0 –0.5 –1.0 –2.0 G = +6 VH = +2V VIN = 0 → 0.7V 1.5 1.0 0.5 0 −0.5 −1.5 Time (5ns/div) LIMITED OUTPUT RESPONSE DETAIL OF LIMITED OUTPUT RESPONSE 2.5 2.10 G = +6 VH = 2V VL = −2V 1.5 1.0 0.5 VIN −1.0 −2.0 2.05 2.00 Output Voltage (V) Input and Output Voltage (V) 2.0 −1.5 VOUT 1.95 1.90 1.85 1.80 1.75 1.70 VOUT 1.65 −2.5 1.60 Time (200ns/div) 8 VOUT −2.5 Time (5ns/div) −0.5 VIN −1.0 −2.0 –2.5 0 G = +6 VH = –2V VIN = 0 → 0.7V 2.0 Input and Output Voltage (V) Input and Output Voltage (V) 2.0 –1.5 See Figure 1 –2.5 –0.4 Time (50ns/div) OPA699 www.ti.com SBOS261B TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE 5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE –55 –60 2nd-Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) –60 –65 –70 –75 3rd-Harmonic –80 –85 –65 –70 –75 –80 3rd-Harmonic –85 See Figure 1 See Figure 1 –90 –90 1k 100 2.5 3.0 3.5 HARMONIC DISTORTION vs FREQUENCY –50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –55 2nd-Harmonic –65 –70 –75 –80 –85 –90 –95 3rd-Harmonic –100 –105 1 10 VO = 2VPP RL = 500Ω f = 5MHz –60 2nd-Harmonic –65 –70 3rd-Harmonic –75 –80 See Figure 1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 20 Output Voltage (VPP) VO = 2VPP RL = 500Ω f = 5MHz −60 2nd-Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) HARMONIC DISTORTION vs INVERTING GAIN −55 –65 –70 –75 6.0 –90 HARMONIC DISTORTION vs NONINVERTING GAIN –60 5.5 RL = 500Ω VH = –VL = VOPP /2 + 0.5V f = 5MHz Frequency (MHz) –55 5.0 –85 See Figure 1 0.5 4.5 HARMONIC DISTORTION vs OUTPUT VOLTAGE –55 VO = 2VPP RL = 500Ω 4.0 ± Supply Voltage (V) Load Resistance (Ω) –60 VO = 2VPP RL = 500Ω 2nd-Harmonic VO = 2VPP f = 5MHz 3rd-Harmonic –80 –85 –90 2nd-Harmonic −65 −70 −75 3rd-Harmonic −80 −85 −90 –95 4 8 12 16 −4 20 OPA699 SBOS261B −8 −12 −16 −20 Gain (V/V) Gain (V/V) www.ti.com 9 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted. −40 38 VO = 0VDC ± 1VP f = 5MHz RL = 500Ω −50 −60 2nd-Harmonic −70 3rd-Harmonic −80 G = +6V/V 36 Intercept Point (+dBm) Harmonic Distortion (dBc) 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT HARMONIC DISTORTION NEAR LIMITING VOLTAGES 34 32 Open PI 30 VH PO OPA699 28 500Ω VL Open 26 24 150Ω 750Ω 22 −90 20 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 2.0 1.7 1.8 1.9 0 10 20 ± Limit Voltage (V) RECOMMENDED RS vs CAPACITIVE LOAD 50 40 FREQUENCY RESPONSE vs CAPACITIVE LOAD 140 18 Gain to Capacitive Load (dB) 120 Resistance (Ω) 30 Frequency (MHz) 100 80 60 40 20 CL = Open 15 CL = 10pF CL = 1000pF 12 9 VO = 0.5VPP G = +6 CL = 100pF VIN RS 6 OPA699 CL 1kΩ(1) 750Ω 3 150Ω Note: (1) 1kΩ(1) is optional. 0 0 10 100 1000 1M 10M Capacitive Load (pF) OPEN-LOOP GAIN AND PHASE INPUT VOLTAGE AND CURRENT NOISE DENSITY 70 0 Gain 60 Open-Loop Gain (dB) Voltage Noise Density (nV/√Hz) Current Noise Density (pA/√Hz) 100 10 Voltage Noise (4.1nV/√Hz) Current Noise (2pA/√Hz) –30 VO = 0.5VPP 50 –60 40 –90 30 –120 Phase 20 –150 10 –180 0 –210 –10 1 100 1k 10k 100k 1M 10M Frequency (Hz) 10 1G 100M Frequency (Hz) –240 10k 100k 1M 10M 100M 1G Frequency (Hz) OPA699 www.ti.com SBOS261B Open-Loop Phase (°) 1 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted. LIMITED VOLTAGE RANGE vs TEMPERATURE VOLTAGE RANGES vs TEMPERATURE 4.0 5.0 VH = –VL = 4.3V VH and VL left open Internal Default Limited Voltage 3.9 VH 3.7 Voltage (V) Output Voltage Range 4.0 3.6 VL 3.5 3.4 3.3 3.5 3.2 Common-Mode Input Range −50 3.0 −25 0 25 50 −50 100 75 −25 0 Limiter Input Bias Current (µA) 75 LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE 100 20 100 Output Current, Sinking 75 Maximum Over Temperature 18 Supply Current (mA) 50 Minimum Over Temperature 25 0 –25 –50 Limiter Headroom = +VS – VH = VL – (–VS) Current = IVH or –IVL –75 98 Output Current, Sourcing 16 96 Supply Current 14 94 12 –100 92 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –50 –25 Limiter Headroom (V) 25 50 75 90 100 TYPICAL DRIFT OVER TEMPERATURE 80 –PSRR 70 60 Input Bias Current (µA) CMRR +PSRR 50 0 Ambient Temperature (°C) COMMON-MODE REJECTION RATIO AND POWER-SUPPLY REJECTION vs FREQUENCY CMRR and PSRR (dB) 50 Ambient Temperature (°C) 100 40 30 20 10 4.5 1 4.0 0.9 3.5 0.8 3.0 0.7 Input Bias Current (IB) 2.5 0.6 0.5 2.0 1.5 0.4 Input Offset Voltage (VOS) 1.0 0.5 0.3 0.2 Input Offset Current (IOS) 0.1 0 0 –0.5 10k 100k 1M 10M 100M −50 −25 0 0 25 50 75 100 Ambient Temperature (°C) Frequency (Hz) OPA699 SBOS261B 25 Ambient Temperature (°C) Output Currents (mA) 3.0 3.1 www.ti.com 11 Input Offset Voltage (mA) Input Offset Current (µA) ±Voltage Ranges (V) 3.8 4.5 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted. CLOSED-LOOP OUTPUT IMPEDANCE LIMITER FEEDTHROUGH −45 100 G = +4 VO = 0.5VPP −50 −60 0.02VPP + 2VDC −65 125Ω −70 VH VO OPA699 −75 VL −80 Open −85 150Ω −90 10 Output Impedance (Ω) Feedthrough (dB) −55 1 0.1 750Ω 0.01 −95 1 1M 100 10 10M CMRR and PSRR(±) vs TEMPERATURE OUTPUT VOLTAGE AND CURRENT LIMITATIONS 100 5 90 VH = –VL = 4.3V 3 Output Voltage (V) CMRR and PSRR (dB) 4 PSRR+ 80 70 PSRR– 60 1W Internal Power Limit 2 1 0 RL = 25Ω –1 RL = 50Ω –2 RL = 100Ω –3 CMRR −50 −25 0 25 1W Internal Power Limit –4 50 50 75 –5 –400 100 –300 –200 –100 0 100 200 300 400 Output Current (mA) Ambient Temperature (°C) 12 1G 100M Frequency (Hz) Frequency (MHz) OPA699 www.ti.com SBOS261B TYPICAL CHARACTERISTICS: VS = +5V TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω to VCM = +2.5V, VL = VCM – 1.2V, VH = VCM + 1.2V, unless otherwise noted. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 9 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 VO = 0.5VPP 6 3 3 Normalized Gain (dB) Normalized Gain (dB) G = –4 VO = 0.5VPP G = +4 G = +6 0 –3 –6 G = +20 –9 G = +12 0 G = –6 –3 G = –12 –6 –9 –12 –12 See Figure 3 See Figure 2 –15 –15 1M 10M 100M 1G 1M 10M Frequency (Hz) LARGE-SIGNAL FREQUENCY RESPONSE 15 VO = 3VPP, VLIM = VCM ± 2.0V Gain (dB) 12 SMALL-SIGNAL PULSE RESPONSE G = +6 0.3 0.2 VO = 2VPP, VLIM = VCM ± 1.5V 9 1G 0.4 VO = 1VPP, VLIM = VCM ± 1.2V 0.1 VOUT (V) 18 100M Frequency (Hz) 6 VLIM = VH = −VL 0 –0.1 –0.2 3 –0.3 See Figure 2 See Figure 2 –0.4 0 0.1 10M 100M 1G Time (5ns/div) Frequency (Hz) LARGE-SIGNAL PULSE RESPONSE VH and VL—LIMITED PULSE RESPONSE 1.5 2.5 G = +6 0.5 VOUT (V) 2.0 Input and Output Voltage (V) 1.0 0 –0.5 –1.0 1.0 0.5 0 VIN –0.5 –1.0 –1.5 –2.0 See Figure 2 –1.5 –2.5 Time (5ns/div) Time (20ns/div) OPA699 SBOS261B VOUT 1.5 www.ti.com 13 TYPICAL CHARACTERISTICS: VS = +5V (Cont.) TA = +25°C, G = +6, RF = 750Ω, and RL = 500Ω to VCM = +2.5V, VL = VCM – 1.2V, VH = VCM + 1.2V, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs LOAD RESISTANCE –50 VO = 2VPP f = 5MHz VO = 2VPP RL = 500Ω –55 –55 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –50 2nd-Harmonic –60 –65 3rd-Harmonic –70 –75 –60 2nd-Harmonic –65 –70 –75 3rd-Harmonic –80 –85 See Figure 2 See Figure 2 –90 –80 1k 100 0.5 1 Frequency (MHz) 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 38 36 –65 Intercept Point (+dBM) Harmonic Distortion (dBc) 2nd-Harmonic –70 3rd-Harmonic –75 RL = 500Ω to VS/2 f = 5MHz VH = VCM + VOPP/2 + 0.5V VL = VCM + VOPP/2 + 0.5V –80 See Figure 2 34 32 Open 30 PI VH PO 28 OPA699 26 VL Open 500Ω 24 750Ω 150Ω 22 –85 20 0.5 1.0 1.5 2.5 2.0 0 10 Output Voltage Swing (VPP) –55 –60 2nd-Harmonic –65 –70 3rd-Harmonic –75 75 Maximum Over Temperature 50 25 Minimum Over Temperature 0 –25 –50 Limiter Headroom = +VS – VH = VL – (–VS) Current = IVH or –IVL –75 –100 –80 0.9 1.0 1.1 1.2 1.3 1.4 1.5 50 40 LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE Limiter Input Bias Current (µA) Harmonic Distortion (dBc) –50 30 100 VO = VCM ±1VP f = 5MHz RL = 500Ω –45 20 Frequency (MHz) HARMONIC DISTORTION NEAR LIMITING VOLTAGES –40 1.6 1.7 0 1.8 Limit Voltages - 2.5V 14 20 10 Load Resistance (Ω) 0.5 1.0 1.5 2.0 2.5 Limiter Headroom (V) OPA699 www.ti.com SBOS261B TYPICAL APPLICATIONS WIDEBAND VOLTAGE LIMITING OPERATION The OPA699 is a gain voltage of +4V/V, voltage-feedback amplifier that combines features of a wideband, high slew rate amplifier with output voltage limiters. Its output can swing up to 1V from each rail and can deliver up to 120mA. These capabilities make it an ideal interface to drive an ADC while adding overdrive protection for the ADC inputs. Figure 1 shows the DC-coupled, gain of +6V/V, dual powersupply circuit configuration used as the basis of the ±5V Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output is set to 500Ω. Voltage swings reported in the specifications are taken directly at the input and output pins. For the circuit of Figure 1, the total output load will be 500Ω || 900Ω = 321Ω. The voltage limiting pins are set to ±2V through a voltage divider network between the +V S and ground for V H , and between –VS and ground for VL. These limiter voltages are adequately bypassed with a 0.1µF ceramic capacitor to ground. The limiter voltages (VH and VL) and the respective bias currents (IVH and IVL) have the polarities shown. One additional component is included in Figure 1. An additional resistor (100Ω) is included in series with the noninverting input. Combined with the 25Ω DC source resistance looking back towards the signal generator, this gives an input bias currentcanceling resistance that matches the 125Ω source resistance seen at the inverting input (see the DC accuracy and offset control section). The power-supply bypass for each 3.01kΩ supply consists of two capacitors: one electrolytic 2.2µF and one ceramic 0.1µF. The power-supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. An additional 0.01µF power-supply decoupling capacitor (not shown here) can be included between the two power-supply pins. In practical PC board layouts, this optional, added capacitor will typically improve the 2nd harmonic distortion performance by 3dB to 6dB. SINGLE-SUPPLY, NONINVERTING AMPLIFIER Figure 2 shows an AC-coupled, noninverting gain amplifier for single +5V supply operation. This circuit was used for AC characterization of the OPA699, with a 50Ω source (which it matches) and a 500Ω load. The mid-point reference on the noninverting input is set by two 1.5kΩ resistors. This gives an input bias current-canceling resistance that matches the 750Ω DC source resistance seen at the inverting input (see the DC accuracy and offset control section). The powersupply bypass for the supply consists of two capacitors: one electrolytic 2.2µF and one ceramic 0.1µF. The power-supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. The limiter voltages (VH and VL) and the respective bias currents (IVH and IVL) have the polarities shown. These limiter voltages are adequately bypassed with a 0.1µF ceramic capacitor to ground. Notice that the single-supply circuit can use three resistors to set VH and VL, where the dual-supply circuit usually uses four to reference the limit voltages to ground. While this circuit shows +5V operation, the same circuit may be used for single supplies up to +12V. 1.91kΩ +VS = +5V VS = +5V + 2.2µF 0.1µF + 0.1µF VH = +2V 0.1µF 2.2µF 523Ω 0.1µF 100Ω VH = 3.7V 7 3 VIN 8 49.9Ω OPA699 2 RF 750Ω RG 150Ω 5 1.5kΩ IVH 0.1µF 6 IVL VO 3 8 53.6Ω 500Ω IVH 7 VIN 1.5kΩ 4 OPA699 2 976Ω 0.1µF 6 VO 5 500Ω IVL 4 RF 750Ω 0.1µF 0.1µF 0.1µF VL = –2V RG 150Ω + 2.2µF 3.01kΩ 0.1µF 1.91kΩ VL = 1.3V 523Ω –VS = –5V FIGURE 1. DC-Coupled, Dual-Supply Amplifier. FIGURE 2. AC-Coupled, Single-Supply Amplifier. OPA699 SBOS261B www.ti.com 15 WIDEBAND INVERTING OPERATION +5V 24 G = –15 21 Gain (dB) Operating the OPA699 as an inverting amplifier has several benefits and is particularly useful when a matched 50Ω source and input impedance are required. Figure 3 shows the inverting gain of –4V/V circuit used as the basis of the inverting mode typical characteristics. 18 G = +15 15 +2V 12 0.1µF RT 169Ω VH OPA699 9 1M VO VL 10M 100M Frequency (Hz) 1G 500Ω –5V 50Ω Source RG 187Ω –2V FIGURE 4. G = +15 and –15 Frequency Response. RF 750Ω VI LOW-GAIN COMPENSATION FOR IMPROVED SFDR RM 68.1Ω FIGURE 3. Inverting G = –4 Specifications and Test Circuit. In the inverting case, only the feedback resistor appears as part of the total output load in parallel with the actual load. For a 500Ω load used in the typical characteristics, this gives a total load of 329Ω in this inverting configuration. The gain resistor is set to get the desired gain (in this case, 187Ω for a gain of –4) while an additional input resistor (RM) can be used to set the total input impedance equal to the source, if desired. In this case, RM = 68.1Ω in parallel with the 187Ω gain setting resistor gives a matched input impedance of 50Ω. This matching is only needed when the input needs to be matched to a source impedance, as in the characterization testing done using the circuit of Figure 3. For bias current-cancellation matching, the noninverting input requires a 169Ω resistor to ground. The calculation for this resistor includes a DC-coupled 50Ω source impedance along with RG and RM. Although this resistor will provide cancellation for the bias current, it must be well-decoupled (0.1µF in Figure 3) to filter the noise contribution of the resistor and the input current noise. As the required RG resistor approaches 50Ω at higher gains, the bandwidth for the circuit in Figure 3 will far exceed the bandwidth at that same gain magnitude for the noninverting circuit of Figure 1. This occurs due to the lower noise gain for the circuit of Figure 3 when the 50Ω source impedance is included in the analysis. For instance, at a signal gain of –15 (RG = 50Ω, RM = open, RF = 750Ω) the noise gain for the circuit of Figure 3 will be 1 + 750Ω/(50Ω + 50Ω) = 8.5 due to the addition of the 50Ω source in the noise gain equation. This approach gives considerably higher bandwidth than the noninverting gain of +15. Using the 1GHz gain bandwidth product for the OPA699, an inverting gain of –15 from a 50Ω source to a 50Ω RG will give 140MHz bandwidth, whereas the noninverting gain of +8 will give 55MHz, as shown in the measured results of Figure 4. 16 Where a low gain is desired, and inverting operation is acceptable, a new external compensation technique can be used to retain the full slew rate and noise benefits of the OPA699, while giving increased loop gain and the associated distortion improvements offered by a non-unity-gain stable op amp. This technique shapes the loop gain for good stability, while giving an easily controlled 2nd-order low-pass frequency response. To set the compensation capacitors (CS and CF), consider the half-circuit of Figure 5, where the 50Ω source is used. Considering only the noise gain for the circuit of Figure 5, the low-frequency noise gain (NG1) is set by the resistor ratio, while the high-frequency noise gain (NG2) is set by the capacitor ratio. The capacitor values set both the transition frequencies and the high-frequency noise gain. If the highfrequency noise gain, determined by NG2 = 1 + CS/CF, is set to a value greater than the recommended minimum stable gain for the op amp, and the noise gain pole (set by 1/RFCF) is placed correctly, a very well controlled 2nd-order low-pass frequency response results. +5V VH 200Ω OPA699 VO VL RG 402Ω RF 402Ω VI CS 13pF CF 2.8pF –5V FIGURE 5. Broadband, Low-Inverting Gain External Compensation. OPA699 www.ti.com SBOS261B To choose the values for both CS and CF, two parameters and only three equations need to be solved. The first parameter is the target high-frequency noise gain (NG2), which should be greater than the minimum stable gain for the OPA699. Here, a target of NG2 = 26 is used. The second parameter is the desired low-frequency signal gain, which also sets the lowfrequency noise gain (NG1). To simplify this discussion, we will target a maximally flat 2nd-order low-pass Butterworth frequency response (Q = 0.707). The signal gain shown in Figure 5 sets the low-frequency noise gain to NG1 = 1 + RF/RG (= 2 in this example). Then, using only these two gains and the gain bandwidth product for the OPA699 (1000MHz), the key frequency in the compensation is set by Equation1. ZO = GBP NG1 NG1 1− − 1− 2 2 NG2 NG2 NG 1 (1) Physically, this ZO (22.3MHz for the values shown above) is set by 1/(2πRF(CF + CS)) and is the frequency at which the rising portion of the noise gain would intersect the unity gain if projected back to a 0dB gain. The actual zero in the noise gain occurs at NG1 • ZO and the pole in the noise gain occurs at NG2 • ZO. That pole is physically set by 1/(RFCF). Since GBP is expressed in Hz, multiply ZO by 2π and use to get CF by solving Equation 2. CF = 1 (= 3pF) 2πRF Z O NG2 (2) Finally, since CS and CF set the high-frequency noise gain, determine CS using Equation 3 (solving for CS by using NG2 = 6): CS = (NG2 − 1)CF (3) which gives CS = 15pF. Both of these calculated values have been reduced slightly in Figure 5 to account for parasitics. The resulting closedloop bandwidth is approximately equal to Equation 4. f –3dB ≅ ZO • GBP (4) For the values shown in Figure 5, f–3dB is approximately 149MHz. This is less than that predicted by simply dividing the GBP product by NG1. The compensation network controls the bandwidth to a lower value, while providing the full slew rate at the output and an improved distortion performance due to increased loop gain at frequencies below NG1 • ZO. LOW DISTORTION, LIMITED OUTPUT, ADC INPUT DRIVER Figure 6 shows a simple ADC driver that operates on a single supply, and gives excellent distortion performance. The limit voltages track the input range of the converter, completely protecting against input overdrive. Note that the limiting voltages have been set 100mV above/below the corresponding reference voltage from the converter. This circuit also implements an improved distortion for an inverting gain of –2 using external compensation. VS = +5V 562Ω VH = +3.6V 0.1µF 1.4kΩ VS = +5V 102Ω +3.5V VS = +5V REFT 0.1µF 3 8 6 24.9Ω ADS822 10-Bit 40MSPS IN 5 2 100pF 750Ω INT/EXT GND +1.5V VIN 18pF 10-Bit Data 4 REFB 1000pF 374Ω +VS 7 OPA699 1.4kΩ RSEL 102Ω 4pF VL = +1.4V 0.1µF 562Ω FIGURE 6. Single Supply, Limiting ADC Input Driver. OPA699 SBOS261B www.ti.com 17 LIMITED OUTPUT, DIFFERENTIAL ADC INPUT DRIVER 3.5 Figure 7 shows a differential ADC driver that takes advantage of the OPA699 limiters to protect the input of the ADC. Two OPA699s are used. The first one is an inverting configuration at a gain of –2. The second one is in a noninverting configuration at a gain of +2. Refer to the section, Low Gain Compensation for Improved SFDR, for a discussion of stability issues of the OPA699 operating at a gain less than 4. Each amplifier is swinging 2VPP providing a 4VPP differential signal to drive the input of the ADC. Limiters have been set 100mV away from the magnitude of each amplifier maximum signal to provide input protection for the ADC while maintaining an acceptable distortion level. PRECISION HALF WAVE RECTIFIER Output Input and Output Voltage (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 Input –1.0 Time (5ns/div) FIGURE 9. 100MHz Sinewave Rectified. Figure 8 shows a half-wave rectifier with outstanding precision and speed. VH (pin 8) will default to a 3.5 typically if left open, while the negative limit is set to ground. The gain for the circuit in Figure 8 is set at +6. Figure 9 shows input and output for ±0.5V 100MHz input. VERY HIGH-SPEED SCHMITT TRIGGER Figure 10 shows a very high-speed Schmitt Trigger. The output levels are precisely defined, and the switching time is exceptional. The output voltage swings between VH and VL. +VS = +5V 50Ω Source 75Ω 2 R2 402Ω 7 VO = Open VIN 8 OPA699 6 R1 200Ω VO R3 200Ω 4 150Ω +2V VREF 5 3 VH OPA699 750Ω VOUT VL VIN –2V –VS = –5V FIGURE 10. Very High-Speed Schmitt Trigger. FIGURE 8. Precision Half-Wave Rectifier. +5V +1.1V OPA699 –1.1V –5V 100Ω 1kΩ 10pF 24.9Ω 0.01µF IN 1kΩ +5V +1.1V VIN = 200mVPP ADC VCM 4VPP 24.9Ω 0.01µF 1kΩ IN OPA699 100Ω 10pF –1.1V –5V 900Ω 100Ω FIGURE 7. Single to Differential AC-Coupled, High Gain Output Limited ADC Driver. 18 OPA699 www.ti.com SBOS261B The circuit operates as follows. When the input voltage is less than VHL then the output is limiting at VH. When the input is greater than VHH, then the output is limiting at VL, with VHL and VHH defined as the following: R || R 2 || R 3 R || R 2 || R 3 × VREF + 1 × VOUT VHL, HH = 1 R1 R2 Due to the inverting function realized by the Schmitt Trigger, VHL corresponds to VOUT = VH, and VHH corresponds to VOUT = VL. Figure 11 shows the Schmitt Trigger operating with VREF = +5V. This gives us VHH = 2.4V and VHL = 1.6V. The propagation delay for the OPA699 in a Schmitt Trigger configuration is 4ns from high-to-low, and 4ns from low-to-high. THEORY OF OPERATION The OPA699 is a voltage-feedback, gain of +4V/V stable op amp. The output voltage is limited to a range set by the voltage on the limiter pins (5 and 8). When the input tries to overdrive the output, the limiters take control of the output buffer. This action from the limiters avoids saturating any part of the signal path, giving quick overdrive recovery and excellent limiter accuracy at any signal gain. The limiters have a very sharp transition from the linear region of operation to output limiting. This transition allows the limiter voltages to be set very near (< 100mV) the desired signal range. The distortion performance is also very good near the limiter voltages. OUTPUT LIMITERS 4 Input and Output Voltage (V) OPERATING SUGGESTIONS 3 2 1 0 VOUT –1 VIN –2 –3 –4 Time (10ns/div) FIGURE 11. Schmitt Trigger Time Domain Response for a 10MHz Sinewave. The output voltage is linearly dependent on the input(s) when it is between the limiter voltages VH (pin 8) and VL (pin 5). When the output tries to exceed VH or VL, the corresponding limiter buffer takes control of the output voltage and holds it at VH or VL. Because the limiters act on the output, their accuracy does not change with the gain. The transition from the linear region of operation to output limiting is very sharp—the desired output signal can safely come to within 30mV of VH or VL with no onset of non-linearity. The limiter voltages can be set to within 0.7V of the supplies (VL ≥ –VS + 0.7V, VH ≤ +VS – 0.7V). They must also be at least 400mV apart (VH – VL ≥ 0.4V). When pins 5 and 8 are left open, VH and VL go to the default voltage limit; the minimum values are given in the electrical specifications. Looking at Figure 12 for the zero bias current case shows the expected range of (VS – default limit voltages) = headroom. DESIGN-IN TOOLS APPLICATIONS SUPPORT DEMONSTRATION BOARDS A PC board is available to assist in the initial evaluation of circuit performance of the OPA699ID. It is available as an unpopulated PCB with descriptive documentation, and can be requested through the TI web site. See the demonstration board literature for more information. The summary information for this board is shown in Table I. 100 Limiter Input Bias Current (µA) The Texas Instruments Applications Department is available for design assistance at 1-972-644-5580. The Texas Instruments web site (www.ti.com) has the latest product data sheets and other design tools. 75 Maximum Over Temperature 50 Minimum Over Temperature 25 0 –25 –50 Limiter Headroom = +VS – VH = VL – (–VS) Current = IVH or –IVL –75 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Limiter Headroom (V) PRODUCT PACKAGE BOARD PART NO. LITERATURE REQUEST NO. OPA699ID SO-8 DEM-OPA68xU SBOU009 TABLE I. Demo Board Summary Information. FIGURE 12. Limiter Bias Current vs Bias Voltage. OPA699 SBOS261B www.ti.com 19 When the limiter voltages are more than 2.1V from the supplies (VL ≥ –VS + 2.1V or VH ≤ +VS – 2.1V), you can use simple resistor dividers to set VH and VL (see Figure 1). Make sure to include the limiter input bias currents (Figure 8) in the calculations (that is, IVL = 50µA into pin 5, and IVH = +50µA out of pin 8). For good limiter voltage accuracy, run a minimum 1mA quiescent bias current through these resistors. When the limiter voltages need to be within 2.1V of the supplies (VL ≤ –VS + 2.1V or VH ≥ +VS – 2.1V), consider using low impedance buffers to set VH and VL to minimize errors due to bias current uncertainty. This condition will typically be the case for single-supply operation (VS = +5V). Figure 2 runs 2.5mA through the resistive divider that sets VH and VL. This limits errors due to IVH and IVL < ±1% of the target limit voltages. The limiters’ DC accuracy depends on attention to detail. The two dominant error sources can be improved as follows: • Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (for example, ±5%). Using a more accurate source, and bypassing pins 5 and 8 with good capacitors, will improve limiter PSRR. • The resistor tolerances in the resistive divider can also dominate. Use 1% resistors. Other error sources also contribute, but should have little impact on the limiters’ DC accuracy: • Reduce offsets caused by the Limiter Input Bias Currents. Select the resistors in the resistive divider(s) as described above. • Consider the signal path DC errors as contributing to uncertainty in the useable output swing. • The limiter offset voltage only slightly degrades limiter accuracy. Figure 13 shows how the limiters affect distortion performance. Virtually no degradation in linearity is observed for output voltage swinging right up to the limiter voltages. In this plot a fixed ±1V output swing is driven while the limiter voltages are reduced symmetrically. Until the limiters are reduced to ±1.1V, little distortion degradation is observed. OUTPUT DRIVE The OPA699 has been optimized to drive 500Ω loads, such as ADCs. It still performs very well driving 100Ω loads; the specifications are shown for the 500Ω load. This makes the OPA699 an ideal choice for a wide range of high-frequency applications. Many high-speed applications, such as driving ADCs, require op amps with low output impedance. As shown in the typical performance curve Output Impedance vs Frequency, the OPA699 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency, since loop gain decreases with frequency. THERMAL CONSIDERATIONS The OPA699 will not require heat sinking under most operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 150°C. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and the additional power dissipated in the output stage (PDL) while delivering load power. PDQ is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signals and loads. For a grounded resistive load, and equal bipolar supplies, it is at maximum when the output is at 1/2 either supply voltage. In this condition, PDL = VS2/(4RL) where RL includes the feedback network loading. Note that it is the power in the output stage, and not in the load, that determines internal power dissipation. The operating junction temperature is: TJ = TA + PD x θJA, where TA is the ambient temperature. For example, the maximum TJ for a OPA699ID with G = +6, RF = 750Ω, RL = 500Ω, and ±VS = ±5V at the maximum TA = +85°C is calculated as: PDQ = (10V × 15.5mA ) = 155mW PDL = Harmonic Distortion (dBc) 4 × (500Ω || 900Ω) = 19.4mW PD = 155mW + 19.4mW = 174.4mW −40 TJ = 85°C + 174.4mW × 125°C / W = 107°C VO = 0VDC ± 1VP f = 5MHz RL = 500Ω −50 This would be the maximum TJ from VO = ±2.5VDC. Most applications will be at a lower output stage power and have a lower TJ. −60 2nd-Harmonic −70 CAPACITIVE LOADS 3rd-Harmonic −80 −90 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 ± Limit Voltage (V) FIGURE 13. Harmonic Distortion Near Limit Voltages. 20 ( 5V ) 2 Capacitive loads, such as the input to ADCs, will decrease the amplifier phase margin, which may cause high-frequency peaking or oscillations. Capacitive loads ≥ 2pF should be isolated by connecting a small resistor in series with the output, as shown in Figure 14. Increasing the gain from +2 will improve the capacitive drive capabilities due to increased phase margin. OPA699 www.ti.com SBOS261B RG The pulse settling characteristics, when recovering from overdrive, are extremely good as shown in the typical characteristics. RF DISTORTION RS RL RT The OPA699 distortion performance is specified for a 500Ω load, such as an ADC. Driving loads with smaller resistance will increase the distortion, as illustrated in Figure 15. Remember to include the feedback network in the load resistance calculations. VO OPA699 CL RL is optional –55 2nd-Harmonic VO = 2VPP f = 5MHz FIGURE 14. Driving Capacitive Loads. In general, capacitive loads should be minimized for optimum high-frequency performance. The capacitance of coax cable (29pF/ft for RG-58) will not load the amplifier when the coaxial cable, or transmission line, is terminated in its characteristic impedance. Harmonic Distortion (dBc) –60 –65 –70 –75 3rd-Harmonic –80 –85 FREQUENCY RESPONSE COMPENSATION See Figure 1 –90 1k 100 The OPA699 is internally compensated to be unity-gain stable, and has a nominal phase margin of 60° at a gain of +6. Phase margin and peaking improve at higher gains. Recall that an inverting gain of –5 is equivalent to a gain of +6 for bandwidth purposes (that is, noise gain = 6). Standard external compensation techniques work with this device. For example, in the inverting configuration, the bandwidth may be limited without modifying the inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing the noise gain at high frequencies, which limits the bandwidth. For unity-gain stable amplifier is needed, the OPA698 is recommended. In applications where a large feedback resistor is required, such as a photodiode transimpedance amplifier, the parasitic capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this effect, connect a small capacitor in parallel with the feedback resistor. The bandwidth will be limited by the pole that the feedback resistor and this capacitor create. In other high-gain applications, use a three-resistor Tee network to reduce the RC time constants set by the parasitic capacitances. Load Resistance (Ω) FIGURE 15. 5MHz Harmonic Distortion vs Load Resistance. NOISE PERFORMANCE High slew rate, voltage-feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. The 4.1nV/√Hz input voltage noise for the OPA699, however, is much lower than comparable amplifiers. The inputreferred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 16 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI EO OPA699 RS IBN PULSE SETTLING TIME The OPA699 is capable of an extremely fast settling time in response to a pulse input. Frequency response flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an ADC, use the recommended RS in the typical performance curve Recommended RS vs Capacitive Load. Extremely fine-scale settling (0.01%) requires close attention to ground return current in the supply decoupling capacitors. ERS RF √ 4kTRS 4kT RG RG IBI √ 4kTRF 4kT = 1.6E –20J at 290°K FIGURE 16. Op Amp Noise Analysis Model. OPA699 SBOS261B www.ti.com 21 The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 5 shows the general form for the output noise voltage using the terms shown in Figure 16. (5) 2 2 EO = ENI2 + (IBNR S ) + 4kTRS NG2 + (IBIRF ) + 4kTRFNG Dividing this expression by the noise gain (NG = (1+RF/RG)) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 6. (6) 2 4kTRF 2 I R EN = ENI2 + (IBNR S ) + 4kTRS + BI F + NG NG Evaluating these two equations for the OPA699 circuit and component values (see Figure 1) will give a total output spot noise voltage of 27.4nV/√Hz and a total equivalent input spot noise voltage of 4.6nV/√Hz. This total input-referred spot noise voltage is only slightly higher than the 4.1nV/√Hz specification for the op amp voltage noise alone. This will be the case as long as the impedances appearing at each op amp input are limited to a maximum value of 300Ω. Keeping both (RF || RG) and the noninverting input source impedance less than 300Ω will satisfy both noise and frequency response flatness considerations. Since the resistor-induced noise is negligible, additional capacitive decoupling across the bias current cancellation resistor (RT) for the inverting op amp configuration of Figure 3 is not required, but is still desirable. through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input may be considered. However, the DC offset voltage on the summing junction will set up a DC current back into the source which must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a DC-coupled inverting amplifier, Figure 17 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the DC offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This will insure that the adjustment circuit has minimal effect on the loop gain as well as the frequency response. +5V Supply Decoupling Not Shown 0.1µF 328Ω OPA699 VO –5V RG 150Ω +5V 5kΩ RF 750Ω VI 20kΩ ±200mV Output Adjustment 10kΩ DC ACCURACY AND OFFSET CONTROL 0.1µF The balanced input stage of a wideband voltage feedback op amp allows good output DC accuracy in a large variety of applications. The power-supply current trim for the OPA699 gives even tighter control than comparable products. Although the high-speed input stage does require relatively high input bias current (typically 3µA at each input terminal), the close matching between them may be used to reduce the output DC error caused by this current. The total output offset voltage may be considerably reduced by matching the DC source resistances appearing at the two inputs. This reduces the output DC error due to the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage, with NG = noninverting signal gain, equal to: ±(NG • VOS(MAX)) ± (RF • IOS(MAX)) = ±(2 • 5mV) ± (750Ω • 2.0µA) = ±11.5mV A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most of these techniques eventually reduce to adding a DC current 22 5kΩ VO VI =– RF RG = –5 –5V FIGURE 17. DC-Coupled, Inverting Gain of –5, with Offset Adjustment. BOARD LAYOUT GUIDELINES Achieving optimum performance with the high-frequency OPA699 requires careful attention to layout design and component selection. Recommended PCB layout techniques and component selection criteria are: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Open a window in the ground and power planes around the signal I/O pins, and leave the ground and power planes unbroken elsewhere. b) Provide a high quality power supply. Use linear regulators, ground plane and power planes to provide power. Place high frequency 0.1µF decoupling capacitors < 0.2" away from each power-supply pin. Use wide, short traces to connect to these capacitors to the ground and power planes. Also use larger (2.2µF to 6.8µF) high-frequency decoupling OPA699 www.ti.com SBOS261B capacitors to bypass lower frequencies. They may be somewhat further from the device, and be shared among several adjacent devices. c) Place external components close to the OPA699. This minimizes inductance, ground loops, transmission line effects and propagation delay problems. Be extra careful with the feedback (RF), input and output resistors. h) Do not use sockets for high-speed parts like the OPA699. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network. Best results are obtained by soldering the part onto the board. POWER SUPPLIES d) Use high-frequency components to minimize parasitic elements. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter layout. Metal film or carbon composition axially-leaded resistors can also provide good performance when their leads are as short as possible. Never use wirewound resistors for high-frequency applications. Remember that most potentiometers have large parasitic capacitances and inductances. Multilayer ceramic chip capacitors work best and take up little space. Monolithic ceramic capacitors also work very well. Use RF type capacitors with low ESR and ESL. The large power pin bypass capacitors (2.2µF to 6.8µF) should be tantalum for better high frequency and pulse performance. The OPA699 is nominally specified for operation using either ±5V supplies or a single +5V supply. The maximum specified total supply voltage of 13V allows reasonable tolerances on the supplies. Higher supply voltages can break down internal junctions, possibly leading to catastrophic failure. Singlesupply operation is possible as long as common mode voltage constraints are observed. The common-mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow design of non-standard or single-supply operation circuits. Figure 2 shows one approach to single-supply operation. e) Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel capacitance. Good metal film or surface mount resistors have approximately 0.2pF parasitic parallel capacitance. For resistors > 1.5kΩ, this adds a pole and/or zero below 500MHz. Make sure that the output loading is not too heavy. The recommended 750Ω feedback resistor is a good starting point in most designs. INPUT AND ESD PROTECTION f) Use short direct traces to other wideband devices on the board. Short traces act as a lumped capacitive load. Wide traces (50 to 100 mils) should be used. Estimate the total capacitive load at the output, and use the series isolation resistor recommended in the typical performance curve, Recommended RS vs Capacitive Load. Parasitic loads < 2pF may not need the isolation resistor. g) When long traces are necessary, use transmission line design techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω transmission line is not required on board—a higher characteristic impedance will help reduce output loading. Use a matching series resistor at the output of the op amp to drive a transmission line, and a matched load resistor at the other end to make the line appear as a resistor. If the 6dB of attenuation that the matched load produces is not acceptable, and the line is not too long, use the series resistor at the source only. This will isolate the source from the reactive load presented by the line, but the frequency response will be degraded. Multiple destination devices are best handled as separate transmission lines, each with its own series source and shunt load terminations. Any parasitic impedances acting on the terminating resistors will alter the transmission line match, and can cause unwanted signal reflections and reactive loading. The OPA699 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 18. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA699), current limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, since high values degrade both noise performance and frequency response. +V CC External Pin –V CC FIGURE 18. I/O Pin ESD Protection. OPA699 SBOS261B Internal Circuitry www.ti.com 23 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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