SPT9110 100 MSPS SINGLE-TO-DIFFERENTIAL TRACK-AND-HOLD FEATURES APPLICATIONS • 400 MHz Sampling Bandwidth • 100 MHz Sampling Rate • Excellent Hold Mode Distortion -66 dB @ 50 MSPS (fIN = 25 MHz) -58 dB @ 100 MSPS (fIN = 50 MHz) • Track Mode Slew Rate: 700 V/µs • Low Power: 120 mW Differential Mode 75 mW Single-Ended Mode • Single +5 V Supply • Internal +2.5 V Reference • • • • THA for Differential ADCs RF Demodulation Systems Test Instrumentation Digital Sampling Oscilloscopes GENERAL DESCRIPTION The SPT9110 is a single-to-differential track-and-hold amplifier. It can be operated as a single-end THA only or, in full configuration, as a single-to-differential THA. An internal reference provides the common-mode voltage for the singleto-differential output stage. The THA, inverter and reference have separate power supply pins so each can be optionally powered up and used. This device provides an analog designer with a low cost single-to-differential THA amplifier for interfacing differential and single-ended ADCs. The SPT9110 is offered in a 28-lead SOIC package in the industrial temperature range. BLOCK DIAGRAM AVCC AVCC (THA) Analog In (VIN) 1X (INV) Out+ 1X Invert InA CHOLD 1 kΩ R1 1 kΩ Invert InB R2 - +2.5 V Reference CLK NCLK AVCC (Ref) Out+ Ref Out Ref In AGND ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)1 Output Currents2 Continuous Output Current ................................. ±15 mA Supply Voltages AVCC Supplies ............................................. -0.5 to +6 V Input Voltages Analog Input Voltage .................................... -0.5 to +6 V CLK, NCLK Input .......................................... -0.5 to +6 V Ref In ............................................................ -0.5 to +6 V Temperature Operating Temperature .............................. -40 to +85 °C Junction Temperature ......................................... +150 °C Lead, Soldering (10 seconds) ............................. +220 °C Storage ..................................................... -65 to +150 °C Note 1: Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical application. Note 2: Outputs are short circuit protected. ELECTRICAL SPECIFICATIONS AVCC = +5.0 V, AGND = 0.0 V, Output Load = 1 kΩ and 10 pF, VIN = 2.0 Vp-p,Internal Reference, unless otherwise specified. PARAMETERS DC Performance Gain ∆VIN = 2.0 Vp-p Single Ended Out Differential Out Offset VIN = +2.5 V Out+ Differential1 Output Drive Capacity2 Output Load at 10 pF Analog Input/Output Output Voltage Range Input Capacitance Input Resistance Reference Voltage Output Reference Output Current3 Reference Voltage Tempco Clock Inputs Input Type/Logic Family Input Bias Current Input Low Voltage (Differential) Input High Voltage (differential) TEST CONDITIONS TEST LEVEL MIN +25 °C Full Temperature +25 °C Full Temperature I V I V 0.95 +25 °C Full Temperature +25 °C, Ref In=Out+ CM Full Temperature Full Temperature Full Temperature I V I V IV V -100 Full Temperature +25 °C +25 °C 1.5 +25 °C Full Temperature VI V I I V V +25 °C +25 °C +25 °C V I I I 1.80 -15 100 2.35 SPT9110 TYP MAX UNITS 0.97 0.96 1.93 1.92 0.99 V/V V/V V/V V/V ±50 55 ±5 10 ±1 1 +100 2.00 ±15 ±10 3.5 5 140 2.45 ±100 75 Differential PECL 2 3.3 3.9 4.1 2.55 10 3.5 mV mV mV mV mA kΩ V pF kΩ V µA ppm/°C µA V V 1Differential offset is specified with Ref In equal to the common mode output voltage of OUT+ and so includes the offset error of the inverter only. 2This part is intended to drive a high impedance load. AC performance is degraded at ±10 mA. See the Typical Performance Graphs. 3Ref Out has a typical output impedance of 1 kΩ and should be buffered for driving loads other than Ref In. SPT9110 2 11/12/98 ELECTRICAL SPECIFICATIONS AVCC = +5.0 V, AGND = 0.0 V, Output Load = 1 kΩ and 10 pF, VIN = 2.0 Vp-p,Internal Reference, unless otherwise specified. PARAMETERS Track Mode Dynamics Bandwidth (-3 dB) Single Ended Out Differential Out Slew Rate 2.0 Vp-p Output Step Single Ended Out Differential Out7 Input RMS Spectral Noise Track-to-Hold Switching Aperture Delay Aperture Jitter Pedestal Offset Hold Mode Dynamics4 (VIN = 1 Vp-p) Worst Harmonic 5 MHz, 50 MSPS, Single-Ended Worst Harmonic 5 MHz, 50 MSPS, Differential Worst Harmonic 25 MHz, 50 MSPS, Single-Ended Worst Harmonic 25 MHz, 50 MSPS, Differential Worst Harmonic 50 MHz, 100 MSPS, Single-Ended Worst Harmonic 50 MHz, 100 MSPS, Differential Sampling Bandwidth5 (-3 dB) VIN = 2.0 Vp-p Hold Noise6 (RMS) Droop Rate, VIN = +2.5 V Feedthrough Rejection (50 MHz) VIN= 2 Vp-p TEST CONDITIONS TEST LEVEL MIN SPT9110 TYP MAX UNITS +25 °C V V 220 140 MHz MHz +25 °C 20 pF Load 20 pF Load IV IV 580 800 V/µs V/µs Single Ended V 3.5 nV/ Hz Differential V 13.0 nV/ Hz +25 °C +25 °C +25 °C Full Temperature V V IV V 250 <1 ±12 ±12 ps ps rms mV mV TA = +25 °C TA = -40 °C to +85 °C IV V -64 -68 -64 dB dB TA = +25 °C TA = -40 °C to +85 °C IV V -61 -65 -63 dB dB TA = +25 °C TA = -40 °C to +85 °C V V -66 -63 dB dB TA = +25 °C TA = -40 °C to +85 °C V V -64 -60 dB dB TA = +25 °C TA = -40 °C to +85 °C IV V -54 -58 -54 dB dB TA = +25 °C TA = -40 °C to +85 °C +25 °C IV V V -50 -54 -50 400 dB dB MHz +25 °C +25 °C Full Temperature Full Temperature V IV IV V 300 x tH ±40 ±80 -65 mV/s mV/µs mV/µs dB 4. For hold times longer than 50 ns, the input common mode voltage may affect the hold mode distortion. (This is due to nonlinear droop that varies with VCM.) For optimal performance, CADEKA recommends that the held output signal be used within 50 ns of the application of the hold signal. 5. Sampling bandwidth is defined as the -3 dB frequency response of the input sampler to the hold capacitor when operating in the sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier. 6. Hold mode noise is proportional to the length of time a signal is held. This value must be combined with the track mode noise to obtain total noise. 7. Optimized for hold mode performance and low power. SPT9110 3 11/12/98 ELECTRICAL SPECIFICATIONS AVCC = +5.0 V, AGND = 0.0 V, RLoad = 1 kΩ and 10 pF, VIN = 2.0 Vp-p, Internal Reference, unless otherwise specified. PARAMETERS Hold-to-Track Switching8 Acquisition Time to 0.1% 1 V Output Step Acquisition Time to 0.025% 1 V Output Step Power Supplies Supply Voltage Supply Current Single Ended Output Mode9 Differential Output Mode Power Dissipation Single Ended Output Mode9 Differential Output Mode Power Supply Rejection Ratio Single-Ended Output TEST CONDITIONS TEST LEVEL MIN SPT9110 TYP MAX UNITS +25 °C V 3.5 ns +25 °C V 4.0 ns IV I I I I V +25 °C ∆VCC = 0.5 VP-P 4.75 5 5.25 V 15 24 20 30 mA mA 75 120 44 100 150 mW mW dB 8. Measured at the hold capacitor. 9. Inverter powered down. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/ max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I TEST PROCEDURE 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characterization data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. SPT9110 4 11/12/98 TIMING SPECIFICATION DEFINITIONS TRACK-TO-HOLD SETTLING TIME ACQUISITION TIME The time required for the output to settle to within 4 mV of its final value. This is the time it takes the SPT9110 to acquire the analog signal at the internal hold capacitor when it makes a transition from hold mode to track mode. (See figure 1.) The acquisition time is measured from the 50% input clock transition point to the point when the signal is within a specified error band at the internal hold capacitor (ahead of the output amplifier). It does not include the delay and settling time of the output amplifier. Because the signal is internally acquired and settled at the hold capacitor before the output voltage has settled, the sampler can be put in hold mode before the output has settled. APERTURE DELAY The aperture delay time is the interval between the leading edge transition of the clock input and the instant when the input signal was equal to the held value. It is the difference in time between the digital hold switch delay and the analog signal propagation time. Figure 1 - Timing Diagram Aperture Delay Input Acquisition Time Observed at Hold Capacitor Output Observed at Amplifier Output CLK Hold Track Track-to-Hold Settling Hold NCLK SPT9110 5 11/12/98 Figure 2 - Typical Output Response to Step Input 500 mV/ Division Out- Inp ut Out+ Out+ — Out- 1.0 ns/Division PARTITIONED POWER SUPPLY MANAGEMENT Three separate +5 V supply connections power the THA, inverting the op amp and bandgap reference. Unused components can be powered off to minimize power dissipation. GENERAL DESCRIPTION The SPT9110 is a low cost 100 MSPS track-and-hold amplifier with single ended (75 mW) or differential output (120 mW). It consists of three components. The first is a single-ended track-and-hold amplifier (THA) with a 1.5 to 3.5 V input range and PECL clock inputs. The second is an inverting op amp with gain of -1 to provide the differential output (OUT-). The third component is a 2.5 V bandgap reference for the inverter. The single-ended mode requires use of only the THA and output on the OUT+ pin. In this mode the reference and inverter may be powered down. The differential mode requires use of all three components (unless an external reference is supplied). The output is measured between OUT+ and OUT- in this mode. SPT9110 6 11/12/98 Figure 3 - Typical Interface Circuit (Single-Ended Operational Design) 1 µF (TTL to PECL Translator) 1 + 10 50 50 1 GND(THA) CLK XUF (Dependent on Frequency) 2 GND(THA) A+5V 3 Analog IN 0.01 µF 2 - 50 4 GND(SUB) 7 + 5 GND(THA) 6 OP191 0.1 µF 4 7 GND(THA) (+2.5 V) 8 GND(THA) N/C 10 REF OUT + 4.7 µF 9 REF IN 3 27 4 26 AVCC(THA) 25 6 GND(CAP) 22 28 AVCC(THA) AVCC(THA) AVCC(THA) SPT9110 3 CLK AVCC(THA) OUT+ INV A INV B A+5V + 4.7 µF OUT- 12 GND(Ref) 0.01 µF AVCC(INV) 13 GND(SUB) 14 GND(INV) AVCC(INV) AVCC(ESD) Q0 Q0 Q1 Q1 VCC 8 0.1 µF 7 DO D1 6 TTL Clock (Sample Clock, up to 100 MHz) 5 GND 4.7 µF + 24 A+5V 23 0.01 µF 22 21 OUT 22 20 N/C 19 N/C 0.01 µF 11 AVCC(Ref) 2 MC100ELT22 0.01 µF (+3.0 V) (Optional Level-Shift Circuit) Analog In A+5V 300 18 N/C 17 N/C 16 N/C 15 A+5V 0.01 µF Notes: 1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if driving from a source that already provides for this offset. 2. The device may be operated from -5 V supply on GND pins and 0 V on AVCC pins. All input and output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs. 3. VCC (ESD) is the high voltage for the ESD protection diodes and must be connected in all applications. NOTE: It should be tied to VCC (THA), not to VCC (INV). Figure 4 - Typical Interface Circuit (Differential Operational Design) 1 µF (TTL to PECL Translator) 1 + 10 50 (Optional Level-Shift Circuit) 50 1 GND(THA) CLK XUF (Dependent on Frequency) 2 GND(THA) A+5V 3 Analog IN 0.01 µF + 2 - 50 7 OP191 4 4 GND(SUB) 5 GND(THA) 6 0.1 µF 22 7 GND(THA) (+2.5 V) 8 GND(THA) + 9 REF IN 4.7 µF 10 REF OUT 28 3 27 4 AVCC(THA) 26 AVCC(THA) 25 AVCC(THA) 6 GND(CAP) SPT9110 3 CLK AVCC(THA) AVCC(THA) OUT+ INV A INV B A+5V + 4.7 µF OUT- 12 GND(Ref) 0.01 µF AVCC(INV) 13 GND(SUB) AVCC(INV) 14 GND(INV) AVCC(ESD) Q0 Q1 Q1 VCC 8 0.1 µF 7 DO D1 6 5 TTL Clock (Sample Clock, up to 100 MHz) GND 4.7 µF + 24 A+5V 23 22 0.01 µF 21 20 OUT+ 22 (Differential Output) 19 0.01 µF 11 AVCC(Ref) Q0 2 MC100ELT22 0.01 µF (+3.0 V) Analog In A+5V 300 18 17 16 22 OUT0.01 µF + A+5V 4.7 µF 15 Notes: 1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if driving from a source that already provides for this offset. 2. The device may be operated from -5 V supply on GND pins and 0 V on AVCC pins. All input and output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs. 3. VCC (ESD) is the high voltage for the ESD protection diodes and must be connected in all applications. NOTE: It should be tied to VCC (THA), not to VCC (INV). SPT9110 7 11/12/98 TYPICAL PERFORMANCE CHARACTERISTICS Single-Ended (OUT+) Hold Mode Distortion vs. Sample Rate Track Mode Bandwidth +2 -65 Input = 25 MHz OUT+ 0 -55 dB Worst Harmonic (dB) -60 -2 -50 Input = 50 MHz -4 -45 OUT-40 50 -6 70 90 110 130 150 Sample Rate (MSPS) 170 0 190 40 80 120 Input Frequency (MHz) 160 200 Slew Rate vs. Temperature Reference Output Voltage vs. Temperature 2.5 VOUT = 2 VP-P 900 2.49 OUT+ V/µs Volts 700 2.48 500 2.47 OUT- 2.46 300 -50 0 +50 100 -50 0 Differential Track Mode Distortion vs. Input Frequency 100 Single Ended Track Mode Distortion vs. Input Frequency VIN = 1 VP-P -75 50 Temperature (°C) Temperature (°C) VIN = 1VP-P -75 -70 OUT+ -65 Worst Harmonics (dB) Worst Harmonic (dB) -70 -65 -60 -60 -55 -50 OUT-45 -55 -40 -35 -50 0 5 10 15 20 25 Input Frequency (MHz) 30 35 40 10 20 30 40 50 Input Frequency (MHz) 60 70 80 SPT9110 8 11/12/98 TYPICAL PERFORMANCE CHARACTERISTICS Track Mode Distortion vs. AC Coupled Resistive Load Hold Mode Distortion vs. Temperature fIN = 40 MHz, 1 VP-P CLoad = 10 pF -70 -65 -76 Worst Harmonic (dB) Worst Harmonic (dB) OUT+ -60 -55 0.01 µF -50 THA RLoad fIN = 5 MHz, fS = 50 MSPS -78 CLoad -45 -74 -72 Out-70 -68 Out+ -40 -35 2000 1750 1500 1250 1000 750 RLoad (Ohms) 500 250 -66 -40 0 -20 20 40 60 80 100 80 100 °C Hold Mode Distortion vs. Temperature Hold Mode Distortion vs. Temperature fIN = 25 MHz, fS = 50 MSPS -70 0 fIN = 50 MHz, fS = 100 MSPS -65 OUT+ -60 Worst Harmonic (dB) Worst Harmonic (dB) -65 -60 OUT- -55 -50 -40 -55 -50 -45 -20 0 20 40 60 80 100 -40 -40 -20 0 20 40 60 °C °C DC Parameters vs. Temperature (VIN = 2.5 V) 80 60 mV (mV/µs for Droop) Single-Ended Offset 40 20 Pedestal Offset Differential Offset 0 -20 Droop -40 -50 0 50 100 Temperature (°C) SPT9110 9 11/12/98 PACKAGE OUTLINE 28-LEAD SOIC INCHES SYMBOL 28 I H 1 A MIN MILLIMETERS MAX MIN MAX A B 0.696 0.004 0.712 0.012 17.68 0.10 18.08 0.30 C D 0.014 .050 typ 0.019 0.00 0.36 1.27 0.48 E F 0.009 0.080 0.012 0.100 0.23 2.03 0.30 2.54 G H I 0.016 0.394 0.291 0.050 0.419 0.299 0.41 10.01 7.39 1.27 10.64 7.59 H F B C D G E SPT9110 10 11/12/98 PIN ASSIGNMENTS PIN FUNCTIONS Name Function AGND (THA) 1 28 CLK Analog In Single-ended analog input to the THA AGND (THA) 2 27 NCLK Invert InA Analog In 3 26 AVCC (THA) Inverting input A to inverting amplifier resistor R1 Invert InB 4 25 AVCC (THA) Inverting input B to inverting amplifier resistor R2 AGND (THA) 5 24 AVCC (THA) Out+ Single-ended output of the THA AGND (Cap) 6 23 AVCC (THA) Out- Output from the inverting amplifier AGND (THA) 7 22 CLK Noninverting differential PECL clock input AVCC (THA) NCLK Inverting differential PECL clock input AGND (THA) 8 21 Out+ Ref In Ref In 9 20 Invert InA Common-mode reference for the inverting amplifier Ref Out 10 19 Invert InB Ref Out Internal +2.5 V reference output 18 AVCC (THA) Track-and-hold analog +5 V supply AVCC (Ref) 11 Out- AVCC (INV) Inverter +5 V supply AGND (Ref) 12 17 AVCC (INV) AVCC (Ref) Internal reference +5 V supply AGND (Sub) 13 16 AVCC (INV) AVCC (ESD) +5 V supply for ESD protection diodes AGND (INV) 14 15 AVCC (ESD) AGND (Sub) AGND (THA) Track-and-hold analog ground AGND (Cap) Hold capacitor analog ground AGND (Sub) Substrate analog ground AGND (INV) INVERTER analog ground AGND (Ref) Internal reference analog ground ORDERING INFORMATION PART NUMBER SPT9110SIS TEMPERATURE RANGE -40 to +85 °C PACKAGE TYPE 28L SOIC SPT9110 11 11/12/98