Product Specification SG6980 Single-Stage PFC Controller FEATURES OVERVIEW DESCRIPTION Innovative switching-charge multiplier divider Multi-vector control for improved PFC output transient response 1:1 Synchronous switching with SYNC Average current mode control Remote on/off control Power-on sequence control Programmable PFC output-voltage control Cycle-by-cycle current limiting Over-voltage and under-voltage protections Brownout and open-loop protections Low start-up and operating current The highly integrated SG6980 is designed for power supplies with boost power-factor-correction (PFC). It requires very few external components to achieve desirable operation and includes versatile protections / compensation. It is available in 16-pin DIP and SOP packages. The innovative switching-charge multiplier divider enhances the PFC circuit’s noise immunity. The proprietary multi-vector control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, SG6980 shuts off to prevent extra-high voltage on output. The PFC gate driver can be synchronized with external SYNC signal and the switching noise can be reduced. During start-up, the RDY (ready) is pulled low until the PFC output voltage reaches the setting level. This signal can be used to control the second forward stage for proper power-on sequence. In addition, SG6980 provides complete protection functions, such as brownout and RI open/short. APPLICATIONS Active-PFC switching power supplies TV and home appliances Computer and telecom TYPICAL APPLICATION SG6980 © System General Corp. Version 1.0.1 (IAO33.0064.B0) -1- www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller MARKING DIAGRAMS PIN CONFIGURATION T: D = DIP S=SOP P: Z = Lead Free XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location SG6980TP XXXXXXXYWWV VRMS IAC OTP VEA RI FB IEA RDY IPFC VDD IMP OUT IPK GND SYNC ON/OFF ORDERING INFORMATION Part Number Pb-Free Package SG6980DZ 16-Pin DIP SG6980SZ 16-Pin SOP © System General Corp. Version 1.0.1 (IAO33.0064.B0) -2- www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller PIN DESCRIPTIONS Name Pin Type Function VRMS Line-Voltage Detection Line voltage detection. The pin is used for PFC multiplier and brownout protection. For brownout protection, the controller is disabled with a 195ms delay time when the VRMS voltage drops below 0.8V. There is a 200mV hysteresis for brownout protection. Over-Temperature Protection This pin supplies an over-temperature protection signal. A constant current is output from this pin. If RI is equal to 24kΩ, the magnitude of the constant current is 50µA. An external NTC thermistor must be connected from this pin to ground. The impedance of the NTC thermistor decreases whenever the temperature increases. Once the voltage of the OTP pin drops below 1.2V, the SG6980 is off, and auto restarts when the voltage is back to 1.4V. OTP 1 2 RI 3 Oscillator Setting The resistance of a resistor connected between RI and ground determines the switching frequency. A resistance between 15kΩ and 40KΩ is recommended. The switching frequency is equal to [1560 / RI] kHz, where RI is in kΩ. For example, if RI is equal to 24kΩ, then the switching frequency is 65kHz. IEA 4 Current Amplifier Output This is the output of the PFC current amplifier. The signal from this pin is compared with an internal sawtooth and determines the pulse width for PFC gate drive. IPFC 5 Inverting Input for PFC Current Amplifier The inverting input of the PFC current amplifier. Proper external compensation circuits will result in excellent input power factor via average-current-mode control. IMP 6 Non-inverting Input for PFC Current Amplifier and Output of Multiplier The non-inverting input of the PFC current amplifier and also the output of the multiplier. Proper external compensation circuits result in excellent input power factor via average-current-mode control. IPK 7 Peak Current Limit The peak current setting for PFC. SYNC 8 Synchronous Signal This pin receives the external switching signal. The PFC switching can be synchronized by SYNC with 1:1 ratio. ON/OFF 9 Remote On/Off Active high. The SG6980 is disabled whenever the voltage at this pin is lower than 1V or the pin is open. When SG6980 is disabled by ON/OFF, the IDD current is lower than 35µA. GND 10 Ground The ground. OUT 11 Gate Drive The totem pole output drive for the PFC MOSFET. This pin is internally clamped under 18V to protect the MOSFET. VDD 12 Supply The power supply pin. The threshold voltages for start-up and turn-off are 12.5V and 10V, respectively. The operating current is lower than 5mA. RDY 13 Ready Signal Output This pin outputs a ready signal to control the power on sequence. Once the SG6980 is turned on and the FB (PFC feedback input) voltage is higher than 2.7V, this pin locks high impedance. Disabling the SG6980 resets this pin to the low. FB 14 Feedback Input The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. VEA 15 Error Amplifier Output The error amplifier output for PFC voltage feedback loop. A compensation network (usually a capacitor) is connected between this pin and ground. A large capacitor value results in a narrow bandwidth and improves the power factor. IAC 16 Input AC Current This input is used to provide current reference for the multiplier. The suggested maximum IAC is 350µA. © System General Corp. Version 1.0.1 (IAO33.0064.B0) -3- www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller BLOCK DIAGRAM © System General Corp. Version 1.0.1 (IAO33.0064.B0) -4- www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller ABSOLUTE MAXIMUM RATING Symbol Parameter Value Unit VVDD DC Supply Voltage* 25 V IAC Input AC Current 2 mA VHigh OUT, SYNC, ON/OFF, RDY -0.3 to 25V V VLow Others -0.3 to 7V V PD Power Dissipation DIP 0.8 SOP 0.4 TJ Operating Junction Temperature +150 TA Operating Ambient Temperature Range -20~+125 TSTG Rθj-C W ℃ Storage Temperature RDY -55 to +150 Thermal resistance (Junction-to-Case) DIP 36.70 SOP 37.76 ℃ 260 ℃/W TL Lead Temperature (Wave Soldering or IR, 10 Seconds) VESD,HBM ESD Capability, Human Body Model 4 KV VESD,MM ESD Capability, Machine Model 250 V ℃ *All voltage values, except differential voltages, are given with respect to the network ground terminal. *Stress beyond those listed under “ABSOLUTE MAXIMUM RATING” may cause permanent damage to the device. ELECTRICAL CHARACTERISTICS VDD=15V, TA=25°C unless otherwise noted. VDD Section Symbol Parameter VDD-OP Continuously Operating Voltage Test Conditions Min. Typ. Max. Unit 20 V IDD-OP Operating Current RI= 24KΩ,VDD = 15V; Gate Open 4 5 mA I IC-OFF Input Current VON/OFF<VON ，VDD=25V 25 35 µA IDD-ST Start-up Current VDD＜VDD-ON-0.16V 10 20 µA VDD-ON Start Threshold Voltage 11.5 12.5 13.5 V VDD-OFF Minimum Operating Voltage 9 10 11 V VDD-OVP VDD Over-Voltage Protection with a Debounce Time 23.5 24.5 25.5 V tD-VDDOVP Debounce Time of VDD OVP 10 40 µs Oscillator & Green-Mode Operation Symbol Parameter Test Conditions Min. Typ. FOSC PWM Frequency RI= 24KΩ 62 65 RI Nominal RI Value 15 Max. Unit 68 KHz 40 KΩ RIOPEN Maximum RI Value for Protection 200 KΩ RISHORT Maximum RI Value for Protection 2 KΩ © System General Corp. Version 1.0.1 (IAO33.0064.B0) -5- www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller VRMS for UVP and RDY Symbol Parameter Min. Typ. Max. Unit VRMS-UVP-1 RMS AC Voltage Under-Voltage Threshold (with TUVP Delay) Test Conditions 0.75 0.80 0.85 V VRMS-UVP-2 Recovery Level on VRMS for UVP Mode VRMS-UVP-1 VRMS-UVP-1 VRMS-UVP-1 V +0.18 +0.20 +0.22 tUVP Under-Voltage Protection Propagation Delay Time (No Delay at Start-up) 150 195 240 ms Voltage Error Amplifier Symbol Parameter VREF Reference Voltage Test Conditions Min. Typ. Max. Unit 2.95 3 3.05 Av Open-Loop Gain 60 V Zo Output Impedance 110 dB KΩ 1.083 • VREF 1.100 • VREF V OVPFB PFC Over-Voltage Protection on FB 1.066 • VREF △OVPFB PFC Feedback Voltage Protection Hysteresis 60 90 120 mV tOVP-PFC Debounce Time of PFC OVP 40 70 120 µs VFB-H Clamp-High Feedback Voltage 1.033 • VREF 1.050 • VREF 1.066 • VREF V GFB-H Clamp-High Gain 500 0.916 • VREF 0.950 • VREF µA/mV 0.966 • VREF VFB-L Clamp-Low Feedback Voltage GFB-L Clamp-Low Gain IFB-L Clamp-Low Maximum Current 1.5 2 UVPFB PFC Feedback Under-Voltage Protection 0.35 0.40 0.45 V tUVP-PFC Debounce Time of PFC Feedback UVP 40 70 120 µs Min. Typ. Max. Unit 6.5 V µA/mV mA Current Error Amplifier Symbol Parameter VOFFSET Input Offset Voltage ((-) > (+)) 8 mV AI Open-Loop Gain 60 dB 1.5 MHz BW Unit Gain Bandwidth CMRR Common-Mode Rejection Ratio VOUT-HIGH Output High Voltage VOUT-LOW Output Low Voltage IMR1, IMR2 Reference Current source IL Maximum Source Current IH Maximum Sink Current © System General Corp. Version 1.0.1 (IAO33.0064.B0) Test Conditions VCM = 0 ~ 1.5V 70 dB 3.2 RI=24KΩ (IMR=20+IRI • 0.8) V 50 3 V µA mA 0.25 -6- 0.2 70 mA www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller Peak Current Limit Symbol Parameter Test Conditions Min. Typ. IP Constant Current Output RI = 24KΩ 90 100 110 µA VPK Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit (Vsense < Vpk) VRMS=1.05V 0.15 0.20 0.25 V VRMS=3V 0.35 0.40 0.45 V tPD-PFC Propagation Delay tLEB-PFC Leading-Edge Blanking Time 250 330 Typ. Max. Unit 200 ns 430 ns Multiplier Symbol Parameter Test Conditions Min. IAC Input AC Current Linear RDY 0 Max. Unit IMO–MAX Maximum Multiplier Current Output RI=24 KΩ 230 250 IMO-1 Multiplier Current Output (Low-Line, High-Power) VRMS=1.05V; IAC=90µA; VEA=7.5V; RI=24KΩ 200 250 IMO–2 Multiplier Current Output (High-Line, High-Power) VRMS=3V; IAC=264µA; VEA=7.5V; RI=24KΩ 65 85 VIMP Voltage of IMP Open 3.4 3.9 4.4 Min. Typ. Max. Unit 15 18 V 1.5 V 120 ns 360 µA µA 280 µA µA V PFC Output Driver Symbol Parameter Test Conditions VZ Output Voltage Maximum (clamp) VDD=20V VOL Output Voltage Low VDD = 15V; IO = 100mA VOH Output Voltage High tR Rising Time tF Falling Time VDD = 13V; IO = 100mA VDD = 15V; CL = 5nF; OUT = 2V to 9V VDD = 15V; CL = 5nF; OUT = 9V to 2V DCYMAX Maximum Duty Cycle 8 V 30 70 30 50 93 100 ns 98 % RDY Section Symbol Parameter FB-RDY-high FB Voltage, RDY High Impedance Test Conditions IFB-RDY-high Input Leakage Current, RDY High Impedance FB=2.5V VOL Output Voltage Low, RDY Failed ISINK =1mA tRDY-delay time Interval Between FB > 2.7V and RDY High Impedance tRDY-UVP_delay time Delay Time Between Gate off and RDY Pull Low when UVP Occurs Min. Typ. Max. Unit 2.7 V 500 4 10 nA 0.5 V 6 ms 16 ms OTP Section Symbol Parameter Test Conditions Min. Typ. Max. Unit IOTP OTP Pin Output Current RI = 24KΩ 90 100 110 µA VOTP-OFF OTP Threshold Voltage 1.15 1.20 1.25 V VOTP-ON Recovery Level on OTP 1.35 1.40 1.45 V TOTP OTP Debounce Time 10 40 µs © System General Corp. Version 1.0.1 (IAO33.0064.B0) -7- www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller SYNC Section Symbol Parameter VSYNC-HIGH Synchronizing Signal High Threshold Test Conditions Min. Typ. Max. Unit VSYNC-LOW Synchronizing Signal Low Threshold FMin Minimum Synchronizing Frequency FMax Maximum Synchronizing Frequency tMIN_PULSE_W Minimum Synchronizing Pulse Width RI = 24KΩ tMAX_PULSE_W Maximum Synchronizing Pulse Width RI = 24KΩ tD-65KHZ Delay Time Between SYNC and OUT, Switching Frequency = 65KHz RI=24KΩ 1 3 µs tD-50KHZ Delay Time Between SYNC and OUT, Switching Frequency = 50KHz RI=31.2KΩ 1 3 µs 3.5 RI=24KΩ V 0.9 V 150 KHz FOSC-6 100 KHz 200 500 15.8 ns µs ON/OFF Section Symbol Parameter Min. Typ. Max. Unit Ron/off Impedance of ON/OFF Pin 18 27 50 VON Enable Signal High Threshold 3 VOFF Enable Signal Low Threshold © System General Corp. Version 1.0.1 (IAO33.0064.B0) Test Conditions 1 -8- KΩ V V www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller TYPICAL CHARACTERISTICS Operating Current (IDD OP) vs Temperature Reference Voltage (V REF) vs Temperature 6 .0 3.10 3.05 5 .0 V REF (V) IDD OP (mA) 5 .5 4 .5 4 .0 3.00 2.95 3 .5 2.90 3 .0 -40 -25 -1 0 5 20 35 50 65 80 95 1 10 -40 12 5 -25 -10 5 1 3.0 16 .0 1 2.8 14 .0 V DD-OFF (V) V DD-ON (V) 35 50 65 80 95 110 125 11 0 125 Min. Operating Voltage (V DD-OFF ) vs Temperature Start Threshold Voltage (V DD-ON ) vs Temperature 1 2.6 1 2.4 12 .0 10 .0 8 .0 1 2.2 6 .0 1 2.0 -4 0 -2 5 -10 5 20 35 50 65 80 95 11 0 -4 0 1 25 -25 -1 0 5 Temperature (℃ ) 20 35 50 65 80 95 Temperature (℃ ) PW M frequency (FOSC ) vs Temperature Minimum synchronizing frequency (Fmin ) vs Temperature 6 6 .0 5 .00 6 5 .0 4 .00 Fmin ( KHz) FOSC (KHz) 20 Temperature (℃ ) Temperature (℃ ) 6 4 .0 6 3 .0 6 2 .0 3 .00 2 .00 1 .00 6 1 .0 0 .00 -4 0 -25 -1 0 5 20 35 50 65 80 95 11 0 12 5 © System General Corp. Version 1.0.1 (IAO33.0064.B0) -4 0 -25 -1 0 5 20 35 50 65 80 95 11 0 1 25 Temperature (℃ ) Temperature (℃ ) -9- www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller RMS AC Voltage Under-voltage Threshold (V RMS-UVP-1) vs Temperature 0 .90 1 20 .0 PFC Feedback Voltage Protection Hysteresis (△ OVP FB ) vs Temperature 1 10 .0 △ OVP FB (mV) V RMS-UVP-1 (V) 0 .85 0 .80 0 .75 1 00 .0 90 .0 80 .0 70 .0 0 .70 -4 0 -25 -1 0 5 20 35 50 65 80 95 1 10 -40 12 5 -25 -10 5 Temperature (℃ ) 50 65 80 95 1 10 1 25 Multiplier Current Output (IMO-2 ) vs Temperature 2 5 0.0 80 .0 2 4 8.0 79 .0 2 4 6.0 78 .0 IMO-2 (uA) IMO-1 (uA) 35 Temperature (℃ ) Multiplier Current Output (IMO-1 ) vs Tem perature 2 4 4.0 2 4 2.0 77 .0 76 .0 2 4 0.0 75 .0 -40 -2 5 -1 0 5 20 35 50 65 80 95 1 10 12 5 -40 -25 -1 0 5 20 35 50 65 80 95 11 0 1 25 Temperature (℃ ) Temperature (℃ ) Recovery Level on OTP (V OTP-ON ) vs Temperature OTP Threshold Voltage (V OTP-OFF ) vs Temperature 1 .3 0 1.4 3 1 .2 5 1.4 1 V OTP-ON (V) V OTP-OFF (V) 20 1 .2 0 1.3 9 1.3 7 1 .1 5 1.3 5 1 .1 0 -40 -2 5 -1 0 5 20 35 50 65 80 95 11 0 1 25 -25 -1 0 5 20 35 50 65 80 95 11 0 125 Temperature (℃ ) Temperature (℃ ) © System General Corp. Version 1.0.1 (IAO33.0064.B0) -4 0 - 10 - www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller OPERATION DESCRIPTION The highly integrated SG6980 is designed for a power supply with boost PFC. It requires very few external components to achieve high performance and includes versatile protections / compensation. The PFC function is implemented by average current mode control. The patented switching-charge multiplier-divider provides a high-degree of noise immunity for the PFC circuit. This enables the PFC circuit to operate over a much wider region. The proprietary multi-vector output voltage control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, the SG6980 shuts off PFC to prevent extra-high voltage on output. Programmable two-level high/low line compensation optimizes THD performance. Line Voltage Detection (VRMS) Figure 1 shows a resistive divider with low-pass filtering for line-voltage detection on the VRMS pin. The VRMS voltage is used for the PFC multiplier, brownout protection, and RDY control. For brownout protection, the SG6980 is disabled with 195ms delay time if the voltage VRMS drops below 0.8V. For PFC multiplier and RDY control, please refer to below sections for more detail. In addition, SG6980 provides complete protection functions, such as brownout and RI open/short. Switching Frequency and Current Sources The switching frequency of SG6980 can be programmed by the resistor RI connected between RI pin and GND. The relationship is: fPWM = 1560 (kHz ) ------------RI (kΩ) PFC Output Voltage Control (1) For example, a 24kΩ resistor RI results in a 65kHz switching frequency. Accordingly, constant current IT flows through RI. I T = 1.2V RI (kΩ ) (mA) ---------------- FIG.1 For a universal input (90VAC ~ 264VAC) power supply applying active boost PFC and forward as a second stage, the output voltage of PFC is usually designed around 400V. Vo = RA + RB × 3V ---RB (3) (2) IT is used to generate internal current reference. If there is a SYNC signal input, the switching frequency is defined by the SYNC signal. The SNYC frequency must be larger than the programmed switching frequency, less 6KHz. FIG.2 Output Voltage Setting © System General Corp. Version 1.0.1 (IAO33.0064.B0) - 11 - www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller ON/OFF For ON/OFF control, the SG6980 is disabled immediately if the voltage at this pin is below 1V. Usually, the pin opens when turn off can have the best power saving. The operating current during turn off is less than 35µA. SYNC Signal Section The SG6980 can synchronize the OUT and synchronize signals provided by second stage, which reduces switching noise and the ripple on output voltage. Figure 3 shows the relationship between the OUT and SYNC signals. FIG.4 Multiplier and Control Loop of PFC Stage The current source output from the switching-charge multiplier/divider can be expressed as: IAC × VEA IMO = K × (µA ) ----------------VRMS 2 (4) IMP, the current output from IMP pin, is the summation of IMO and IMR1. IMR1 and IMR2 are identical, fixed-current sources. R2 and R3 are also identical. They are used to pull high the operating point of the IMP and ICS pins if the voltage across RS goes negative with respect to ground. Through the differential amplification of the signal across Rs, better noise immunity is achieved. The output of IEA is compared with an internal sawtooth and the pulse width for PFC is determined. Through the average current-mode control loop, the input current IS is proportional to IMO: FIG.3 Synchronized Interleaving-Switching RDY Signal Section SG6980 provides a RDY pin to inform the next stage and other applications. RDY signal is high impedance when the FB voltage goes up to 2.7V and delays around 5ms. Use the pin to turn on the second stage PWM when the bulk capacitor voltage is high enough. In SG6980, the RDY pin (open-drain structure) is used for next-stage-ready signal. PFC Operation The purpose of a boost active power factor corrector (PFC) is to shape the input current of a power supply. The input current waveform and phase follow that of the input voltage. Using SG6980, average-current-mode control is utilized for continuous-current-mode operation for the PFC booster. With the innovative multi-vector control for voltage loop and switching-charge multiplier/divider for current reference, excellent input power factor is achieved with good noise immunity and transient response. Figure 4 shows the total control loop for the average-current-mode control circuit of SG6980. © System General Corp. Version 1.0.1 (IAO33.0064.B0) - 12 - IMO × R 2 = IS × RS --------------- (5) According to Equation 5, the minimum value of R2 and maximum of RS can be determined because IMO should not exceed the specified maximum value. There are different concerns in determining the value of the sense resistor, RS. The value of RS should be small enough to reduce power consumption, large enough to maintain the resolution. A current transformer (CT) may be used to improve the efficiency of high-power converters. To achieve a good power factor, the voltage for VRMS and VEA should be kept as DC as possible, according to Equation 4. Good RC filtering for VRMS and narrow bandwidth (lower than the line frequency) for voltage loop are suggested for better input current shaping. The transconductance error amplifier has output impedance RO and a capacitor CEA (1µF ~ 10µF) connected to ground (as shown in Figure 4). This establishes a dominant pole f1 (per Equation 6) for the voltage loop. www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller f1 = 1 2π × R0 × CEA Cycle-by-Cycle Current Limiting ---------------------------- (6) The average total input power can be expressed as: Pin = Vin(rms) × Iin(rms) The voltage of VRMS determines the voltage of VPK. The relationship between VPK and VRMS is shown in Figure 6. ∝ VRMS × IMO ∝ VRMS × ∝ VRMS × IAC × VEA VRMS 2 Vin × VEA R AC VRMS 2 SG6980 provides cycle-by-cycle current limiting for PFC stages. Figure 6 shows the peak current limit for the PFC stage. The PFC gate drive is terminated once the voltage on IPK pin goes below VPK. -------------- (7) The amplitude of the constant current IP is determined by the internal current reference IT, according to the equation: ∝ VEA From Equation 7, VEA, the output of the voltage error amplifier, controls the total input power and the power delivered to the load. Ip = 2 × I 1.2V ----------------------R I (8) Therefore the peak current of the IS is given by: Multi-Vector Error Amplifier The voltage-loop error amplifier of SG6980 is transconductance, which has high output impedance (> 90kΩ). A capacitor CEA (1µF ~ 10µF) connected from VEA to ground provides a dominant pole for the voltage loop. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of the PFC output voltage. Figure 5 shows the voltage loop with multi-vector for fast transient error amplifier. When the variation of the feedback voltage exceeds ± 5% of the reference voltage, the transconductance error amplifier adjusts its output impedance to increase the loop response. If the feedback resistance is opened, SG6980 shuts off immediately to prevent extra-high voltage on the output capacitor. T = 2× IS_peak = (Ip × RP) - V pk RS ------------------ (9) FIG.6 Current Limit Gate Drivers SG6980 output stages are fast totem-pole gate drivers. The output driver is clamped by an internal 18V Zener diode to protect the power MOSFET. Over-Temperature Protection SG6980 provides an OTP pin for over-temperature protection. A constant current is output from this pin. If RI is equal to 24kΩ, the magnitude of the constant current is 50µA. An external NTC thermistor must be connected from this pin to ground. When the OTP voltage drops below 1.2V, SG6980 shuts down. SG6980 auto restarts when the OTP voltage is higher than 1.4V. FIG. 5 Voltage Error Amplifier with Multi-Vector © System General Corp. Version 1.0.1 (IAO33.0064.B0) - 13 - www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller Protections & Built-in Latch Circuit The SG6980 provides full protection functions to prevent the power supply and the load from being damaged. The protection features include: PFC Feedback Over-Voltage Protection. When the PFC feedback voltage exceeds the over-voltage threshold, the SG6980 inhibits the PFC switching signal. This protection prevents the PFC power converter from operating abnormally while the FB pin is open. PFC Feedback Under-Voltage Protection. The SG6980 stops the PFC switching signal whenever the PFC feedback voltage drops below the under-voltage threshold. This protection feature is designed to prevent the PFC power converter from experiencing abnormal conditions while the FB pin is shorted to ground. 2 provides a signal ground. It should be connected directly to the decoupling capacitor CDD and/or to the ground pin. The ground trace 3 is independently tied from the decoupling capacitor to the PFC output capacitor CO. The ground in the output capacitor CO is the major ground reference for power switching. To provide a good ground reference and reduce the switching noise of both the PFC and PWM stages, the ground traces 6 and 7 should be located very near and be low impedance. The ICS pin is connected directly to RS through R3 to improve noise immunity. (Beware that it may incorrectly be connected to the ground trace 2). The IMP and IPK pins should also be connected directly, via the resistors R2 and RP, to another terminal of RS. VDD Over-Voltage Protection. The built-in clamping circuit clamps VDD whenever the VDD voltage exceeds the over-voltage threshold. RI Pin Open / Short Protection. The RI pin is used to set the switching frequency and internal current reference. If the RI pin is short or open, SG6980 is off. PCB Layout SG6980 has a single ground pin. High sink currents in the output therefore cannot be returned separately. Good high-frequency or RF layout practices should be followed. Avoid long PCB traces and component leads. Locate decoupling capacitors near the SG6980. A resistor of 5 ~ 20Ω is recommended, connecting in series from the output to the gate of the MOSFET. FIG. 7 PCB Layout Isolating the interference between the PFC and PWM stages is also important. Figure 7 shows an example of the PCB layout. The ground trace 1 is connected from the ground pin to the decoupling capacitor, which should be low impedance and as short as possible. The ground trace © System General Corp. Version 1.0.1 (IAO33.0064.B0) - 14 - www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller REFERENCE CIRCUIT © System General Corp. Version 1.0.1 (IAO33.0064.B0) - 15 - www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller PACKAGE INFORMATION 16 PINS – PLASTIC DIP (D) θ D 9 16 E1 eB E 8 1 A2 L A e b1 A1 Dimensions: Symbol A A1 A2 b b1 D E E1 e L eB Millimeter Min. 0.381 3.175 18.669 θ° © System General Corp. Version 1.0.1 (IAO33.0064.B0) 6.121 2.921 8.509 0° Typ. Max. 5.334 3.302 1.524 0.457 19.177 7.620 6.299 2.540 3.302 9.017 7° Inch Min. Typ. 3.429 0.015 0.125 19.685 0.735 6.477 0.241 3.810 9.525 0.115 0.335 15° - 16 - 0° Max. 0.210 0.130 0.060 0.018 0.755 0.300 0.248 0.100 0.130 0.355 7° 0.135 0.775 0.255 0.150 0.375 15° www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller 16 PINS – PLASTIC SOP (S) 16 9 E 1 H Detail A F 8 b c e θ D A2 A L y Detail A A1 Dimension: Symbol A A1 A2 b c D E e H L F y θ° Millimeter Min. 1.346 0.101 1.244 © System General Corp. Version 1.0.1 (IAO33.0064.B0) Typ. Max. 1.753 0.254 1.499 Inch Min. 0.053 0.004 0.049 0.406 0.203 9.804 3.810 10.008 3.988 0.386 0.150 6.198 1.270 0.228 0.016 0.394 0.157 0.050 0.381X45° 0° Max. 0.069 0.010 0.059 0.016 0.008 1.270 5.791 0.406 Typ. 0.244 0.050 0.015X45° 0.101 8° - 17 - 0° 0.004 8° www.sg.com.tw • www.fairchildsemi.com September 17, 2007 Product Specification SG6980 Single-Stage PFC Controller © System General Corp. Version 1.0.1 (IAO33.0064.B0) - 18 - www.sg.com.tw • www.fairchildsemi.com September 17, 2007