Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller FEATURES Green-mode PFC and PWM operation No switching of PFC at light loads saves power Low start-up and operating current Innovative switching-charge multiplier-divider Multi-vector control for improved PFC output transient response Interleaved PFC/PWM switching Programmable two-level PFC output voltage Average-current-mode control for PFC Cycle-by-cycle current limiting for PFC/PWM PFC over-voltage and under-voltage protections PFC and PWM feedback open-loop protection Brownout protection Over-temperature protection For PFC stage, the proprietary multi-vector control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, the SG6902 shuts off PFC to prevent extra-high voltage on output. Programmable two-level output voltage control reduces the PFC output voltage at low line input to increase the efficiency of the power supply. For the flyback PWM, the synchronized slope compensation ensures the stability of the current loop under continuous-conduction-mode operation. Built-in line-voltage compensation maintains a constant output power limit. Hiccup operation during output overloading is also guaranteed. APPLICATIONS The patented interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light loads, the switching frequency is continuously decreased to reduce power consumption. If output loading is further reduced, the PFC stage is turned off to further reduce power consumption. Switching Power Supplies with Active PFC High-Power Adaptors DESCRIPTION The highly integrated SG6902 is designed for power supplies with boost PFC and Flyback PWM. It requires very few external components to achieve green-mode operation and versatile protections. It is available in a 20-pin SOP package. In addition, SG6902 provides protection functions, such as brownout and RI pin open/short protections. TYPICAL APPLICATION © System General Corp. Version 1.3.1 (IAO33.0022.B3) -1- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller MARKING DIAGRAM PIN CONFIGURATION T: S=SOP P : Z=Lead Free + ROHS Compatible Null=regular package XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location SG6902TP XXXXXXXXYWWV ORDERING INFORMATION Part Number Pb-Free SG6902SZ © System General Corp. Version 1.3.1 (IAO33.0022.B3) Package 20-pin SOP -2- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller PIN DESCIRPTIONS Name Pin No. Type Function VRMS 1 Line Voltage Detection Line voltage detection. The pin is used for PFC multiplier, RANGE control of PFC output voltage, and brownout protection. For brownout protection, the controller is disabled after a delay time when the VRMS voltage drops below a threshold. RI 2 Oscillator Setting Reference setting. One resistor connected between RI and AGND determines the switching frequency. The switching frequency is equal to [1560 / RI] kHz, where RI is in kΩ. For example, if RI is 24kΩ, the switching frequency is 65kHz. OTP 3 This pin supplies an over-temperature protection signal. A constant current is output from this pin. An external NTC thermistor must be connected from this pin to ground. Over-Temperature Protection The impedance of the NTC thermistor decreases whenever the temperature increases. Once the voltage of the OTP pin drops below the OTP threshold, the SG6902 is disabled. IEA 4 Output for PFC Current Amplifier This is the output of the PFC current error amplifier. The signal from this pin is compared with an internal sawtooth and determines the pulse width for PFC gate drive. IPFC 5 Inverting Input for PFC Current Amplifier The inverting input of the PFC current error amplifier. Proper external compensation circuits result in excellent input power factor via average-current-mode control. IMP 6 Non-Inverting Input for PFC Current Amplifier The non-inverting input of the PFC current amplifier and also the output of multiplier. Proper external compensation circuits will result in excellent input power factor via average-current-mode control. ISENSE 7 Peak Current Limit Setting for The peak-current setting for PFC. PFC FBPWM 8 PWM Feedback Input The control input for voltage-loop feedback of PWM stage. It is internally pulled high through a resistor. An external opto-coupler from secondary feedback circuit is usually connected to this pin. IPWM 9 PWM Current Sense The current-sense input for the flyback PWM. Via a current sense resistor, this pin provides the control input for peak-current-mode control and cycle-by-cycle current limiting. AGND 10 Ground Signal ground. SS 11 PWM Soft-Start During start-up, the SS pin charges an external capacitor with a 50µA (RI=24kΩ) constant-current source. The voltage on FBPWM is clamped by SS during start-up. In the event of a protection condition occurring and/or PWM being disabled, the SS pin quickly discharges. OPWM 12 PWM Gate Drive The totem-pole output drive for the flyback PWM MOSFET. This pin is internally clamped under 18V to protect the MOSFET. GND 13 Ground Power ground. OPFC 14 PFC Gate Drive The totem-pole output drive for the PFC MOSFET. This pin is internally clamped under 18V to protect the MOSFET. VDD 15 Supply The power supply pin. RANGE 16 PFC Output Voltage Control Two-level output voltage setting for PFC. The PFC output voltage at low line can be reduced to improve efficiency. The RANGE pin is of high impedance while the VRMS voltage is lower than a threshold. OVP 17 PFC Over-Voltage Input The PFC stage over-voltage input. The comparator disables the PFC output driver if the voltage at this input exceeds a threshold. This pin can be connected to FBPFC or it can be connected to the PFC boost output through a divider network. FBPFC 18 Voltage Feedback Input for PFC The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. VEA 19 The error amplifier output for PFC voltage feedback loop. A compensation network Error Amplifier Output for (usually a capacitor) is connected between this pin and ground. A large capacitor PFC Voltage Feedback Loop value results in a narrow bandwidth and improves the power factor. IAC 20 Input AC Current © System General Corp. Version 1.3.1 (IAO33.0022.B3) Before start-up, this input is used to provide start-up current for VDD. For normal operation, this input is used to provide current reference for the multiplier. -3- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller BLOCK DIAGRAM © System General Corp. Version 1.3.1 (IAO33.0022.B3) -4- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VDD DC Supply Voltage* 25 V IAC Input AC Current 2 mA VHIGH OPWM, OPFC, IAC -0.3 to +25.0 V VLOW Others -0.3 to +7.0 V PD Power Dissipation at TA < 50°C SOP TJ Operating Junction Temperature -40 to +125 TSTG Storage Temperature Range -55 to +150 RθJC Thermal Resistance (Junction-to-Case) SOP TL ESD 1.15 W °C °C 23.64 °C/W Lead Temperature (Wave Soldering or Infrared, 10 Seconds) 260 °C Electrostatic Discharge Capability, Human Body Model 4.5 KV Electrostatic Discharge Capability y, Machine Model 250 V *All voltage values, except differential voltages, are given with respect to GND pin. *Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit TA Operating Ambient Temperature* -30 to +85 °C *For proper operation. ELECTRICAL CHARACTERISTICS VDD=15V, TA=25°C unless otherwise noted. VDD Section Symbol Parameter Test Conditions Min. Typ. Max. Unit 20 V 10 25 µA VDD-OP Continuously Operating Voltage IDD-ST Start-up Current VTH-ON –0.16V IDD-OP Operating Current OPFC, OPWM Open, RI=24kΩ 6 10 mA VTH-ON Start Threshold Voltage 15 16 17 V VDD-MIN Minimum Operating Voltage 9 10 11 V VDD-OVP VDD OVP Threshold 23.5 24.5 25.5 V TVDD-OVP Debounce Time of VDD OVP 25 µs VDD-TH-G VDD Low-Threshold Voltage to Exit Green-off Mode VDD-MIN +2.1 V © System General Corp. Version 1.3.1 (IAO33.0022.B3) RI=24kΩ 8 VDD-MIN +0.9 -5- VDD-MIN +1.5 www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller Oscillator & Green-Mode Operation Symbol Parameter VRI RI Voltage Test Conditions Min. Typ. Max. Unit 1.176 1.200 1.224 V FOSC PWM Frequency RI=24kΩ 62 65 68 KHz FOSC-MINFREQ Minimum Frequency in Green Mode RI=24kΩ 18.0 20.0 22.5 KHz 47 KΩ RI RI Pin Resistance Range RIOPEN RI Pin Open Protection If RI> RIopen , SG6902 Turns Off 15 200 KΩ RISHORT RI Pin Short Protection If RI< RIshort , SG6902 Turns Off 2 KΩ VRMS for UVP and RANGE Symbol Parameter Min. Typ. Max. Unit VRMS-UVP-1 RMS AC Voltage Under-Voltage Protection Threshold (with TUVP Delay) Test Conditions 0.75 0.80 0.85 V VRMS-UVP-2 Recovery Level on VRMS VRMS-UVP-1 VRMS-UVP-1 VRMS-UVP-1 V +0.16V +0.18V +0.2V TD-PWM When UVP Occurs, Interval from PFC Off to PWM Off RI=24kΩ TUVP Under-Voltage Protection Delay Time* RI=24kΩ VRMS-H High VRMS Threshold for RANGE Comparator TUVP-Min+ 9 TUVP-Min+ ms 14 150 195 240 ms 1.90 1.95 2.00 V 1.55 1.60 1.65 V 145 170 200 ms VRMS-L Low VRMS Threshold for RANGE Comparator TRANGE Range Enable Delay Time RI=24kΩ VOL Output Low Voltage of RANGE Pin Io=1mA 0.5 V IOH Output High Leakage Current of RANGE Pin RANGE=5V 50 nA Unit * No delay for start-up. PFC STAGE Voltage Error Amplifier Symbol Parameter VREF Reference Voltage Av-PFC* Open-Loop Gain Test Conditions Min. Typ. Max. 2.95 3.00 3.05 60 ZO* Output Impedance OVPPFC PFC Over Voltage Protection (OVP Pin) △OVPPFC PFC Feedback Voltage Protection Hysteresis TOVP-PFC Debounce Time of PFC OVP VFBPFC-H Clamp-High Feedback Voltage GFBPFC-H* Clamp-High Gain VFBPFC-L Clamp-Low Feedback Voltage GFBPFC-L* Clamp-Low Gain IFBPFC-L 110 RI=24kΩ V dB KΩ 3.20 3.25 3.30 60 90 120 mV 40 70 120 µs 3.10 3.15 3.20 V 2.90 V 0.5 V mA/V 2.75 2.85 6.5 mA/mV Maximum Source Current 1.5 2.0 mA IFBPFC-H Maximum Sink Current 70 110 UVPFBPFC PFC Feedback Under-Voltage Protection 0.35 0.40 0.45 VFBHIGH FB Open Voltage 6 7 8 V TUVP-PFC Debounce Time of PFC UVP 40 70 120 µs * RI=24kΩ µA V Not tested in production. © System General Corp. Version 1.3.1 (IAO33.0022.B3) -6- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller Current Error Amplifier Symbol Parameter VOFFSET Input Offset Voltage Test Conditions Min. 8 mV AI*1 Open-Loop Gain 60 dB BW *1 Unit Gain Bandwidth 1.5 MHz CMRR*1 Common Mode Rejection Ratio VOUT-HIGH Output High Voltage VCM=0 to +1.5V Typ. Max. 70 Unit dB 3.2 V VOUT-LOW Output Low Voltage IMR1, IMR2 Reference Current Source IL Maximum Source Current 3 mA IH Maximum Sink Current 0.25 mA RI=24kΩ (IMR=20+IRI•0.8) 50 0.2 V 70 µA Peak Current Limit Symbol Parameter Test Conditions Min. Typ. Max. Unit µA IP Constant Current Output RI=24kΩ 90 100 110 VPK Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit (VSENSE < VPK) VRMS=1.05V 0.15 0.20 0.25 V VRMS=3V 0.35 0.40 0.45 V TPD-PFC Propagation Delay 200 ns TBNK-PFC Leading-Edge Blanking Time 270 350 450 ns Typ. Multiplier Symbol Parameter Test Conditions Min. IAC Input AC Current Multiplier Linear Range 0 Max. Unit 360 µA VDROP Voltage Drop from the IAC Pin to VDD IAC=240µA IMO–MAX*1 Maximum Multiplier Current Output RI=24 kΩ 3.5 IMO-1 Multiplier Current Output (Low-line, High-power) VRMS=1.05V; IAC=90µA; VEA=7.5V; RI=24kΩ 200 250 IMO–2 Multiplier Current Output (High-line, High-power) VRMS=3V; IAC=264µA; VEA=7.5V; RI=24kΩ 65 85 VIMP Voltage of IMP Open 3.4 3.9 4.4 V Min. Typ. Max. Unit 16 18 V 11.5 14.0 ms 1.5 V 250 V µA 280 µA µA PFC Output Driver Symbol Parameter Test Conditions VZ-PFC Output Voltage Maximum (Clamp) VDD=20V TPFC Interval OPFC Lags Behind OPWM at Start-up RI=24kΩ VOL-PFC Output Voltage Low VDD=15V; IO=100mA VOH-PFC Output Voltage High VDD=13V; IO=100mA 8 TR-PFC Rising Time VDD=15V; CL=5nF; OPFC=2V to 9V 40 70 120 ns TF-PFC Falling Time VDD=15V; CL=5nF; OPFC=9V to 2V 40 60 110 ns DCMAX-PFC Maximum Duty Cycle 98 % © System General Corp. Version 1.3.1 (IAO33.0022.B3) 9.0 93 -7- V www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller PWM STAGE FBPWM Symbol Parameter Av-PWM ZFB* Min. Typ. Max. Unit FB to Current Comparator Attenuation 2.5 3.1 3.5 V/V Input Impedance 4 5 7 KΩ IFB Maximum Source Current 0.8 1.2 1.5 mA FBOPEN-LOOP PWM Open-Loop Protection Threshold 4.2 4.5 4.8 V TOPEN-PWM PWM Open-Loop Protection Delay Time RI=24kΩ 45 56 70 ms VPFC-OFF1 PFC Off Voltage at FBPWM RANGE=Ground VG+0.2V VPFC-OFF2 PFC Off Voltage at FBPWM RANGE=Open VG+0.2V TPFC-OFF PFC Off Delay Time RI=24kΩ VPFC-ON 1.6 PFC On Voltage at FBPWM RANGE=Ground VRMS=1.6V VG+0.35 V V VPFC-ON 2.85 PFC On Voltage at FBPWM RANGE=Ground VRMS=2.85V VG+0.35 V V VPFC-ON 0.8 PFC On Voltage at FBPWM RANGE=Open VRMS=0.8V VG+0.85 V V VPFC-ON 1.95 PFC On Voltage at FBPWM RANGE=Open VRMS=1.95V VG+0.5V V VN Frequency Reduction Threshold on FBPWM RANGE=Ground SG*1 VG * Test Conditions 500 650 V V 800 ms 1.9 2.1 2.3 V Green-Mode Modulation Slope 60 75 90 Hz/V Voltage on FBPWM at FS=20KHz 1.35 1.60 1.75 V Test Conditions Min. Typ. Max. Unit Not tested in production. PWM-Current Sense Symbol Parameter TPD-PWM Propagation Delay to Output 120 ns VLIMIT-1 Peak Current Limit Threshold Voltage1 RANGE=Open 0.65 0.70 0.75 V VLIMIT-2 Peak Current Limit Threshold Voltage2 RANGE=Ground 0.60 0.65 0.70 V TBNK-PWM Leading-Edge Blanking Time 270 350 450 ns △VS=△VSLOPE x (Ton/T) △VS: Compensation Voltage Added to Current Sense 0.45 0.50 0.55 V Min. Typ. Max. Unit 16 18 V △VSLOPE Slope Compensation 60 PWM Output Driver Symbol Parameter Test Conditions VZ-PWM Output Voltage Maximum (Clamp) VDD=20V VOL-PWM Output Voltage Low VDD=15V; IO=100mA VOH-PWM Output Voltage High VDD=13V; IO=100mA 8 TR-PWM Rising Time VDD=15V; CL=5nF; OPWM=2V to 9V 30 60 120 ns TF-PWM Falling Time VDD=15V; CL=5nF; OPWM=9V to 2V 30 50 110 ns DCMAX-PWM Maximum Duty Cycle 73 78 83 % © System General Corp. Version 1.3.1 (IAO33.0022.B3) -8- 1.5 V V www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller OTP Section Symbol Parameter Test Conditions Min. Typ. Max. Unit IOTP OTP Pin Output Current RI=24kΩ 90 100 11 µA VOTP-OFF OTP Threshold Voltage 1.15 1.20 1.25 V VOTP-ON Recovery Level on OTP 1.35 1.40 1.45 V TOTP OTP Debounce Time 25 µs RI=24kΩ 8 Soft-Start Section Symbol Parameter Test Conditions Min. Typ. Max. Unit ISS Constant Current Output for Soft-Start RI=24kΩ 44 50 56 µA RD* Discharge RDSON * 470 Ω Not tested in production. © System General Corp. Version 1.3.1 (IAO33.0022.B3) -9- www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller TYPICAL CHARACTERISTICS Min. Operation Voltge (V DD-MIN) vs Temperature Start-UP Current (IDD-ST) vs Temperature 11.0 20 10.8 18 10.6 16 10.4 VDD-MIN (V) IDD-ST (uA) 14 12 10 8 10.2 10.0 9.8 6 9.6 4 9.4 2 9.2 9.0 0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ -40℃ -25℃ -10℃ 95℃ 110℃ 125℃ 5℃ 20℃ 12 70 10 60 Frequency (KHz) Start-up Current (uA) 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 2.2 2.3 2.4 2.5 2.6 2.2 2.3 2.4 2.5 2.6 Frequency vs. FB Voltage Start-up Current vs. VDD Voltage 8 6 4 2 50 40 30 20 10 0 0 0 1.65 3.3 4.95 6.6 8.25 9.9 11.55 13.2 14.85 16.5 18.15 1.5 1.6 1.7 1.8 1.9 2 2.1 FB Voltage (V) VDD Voltage (V) Duty cycle vs. FB Voltage Start Threshold Voltage (VTH-ON) vs Temperature 17.00 90 16.80 80 16.60 70 Duty cycle (%) 16.40 VTH-ON(V) 35℃ Temperature (℃) Temperature (℃) 16.20 16.00 15.80 15.60 60 50 40 30 15.40 20 15.20 10 15.00 0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 1.5 Temperature (℃) © System General Corp. Version 1.3.1 (IAO33.0022.B3) 1.6 1.7 1.8 1.9 2 2.1 FB Voltage (V) - 10 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller VDD OVP Threshold (VDD-OVP) vs Temperature High VRMS Threshold for RANGE Comparator (V RMS-H ) vs Temperature 2.00 25.5 1.99 1.98 25.1 VRMS-H (V) VDD-OVP (V) 1.97 24.7 24.3 1.96 1.95 1.94 1.93 23.9 1.92 1.91 23.5 1.90 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ Temperature (℃) 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Low VRMS Threshold for RANGE Comarator (V RMS-L) vs Temperature 68.0 67.5 67.0 66.5 66.0 65.5 65.0 64.5 64.0 63.5 63.0 62.5 62.0 1.65 1.64 1.63 1.62 VRMS-L (V) FOSC (KHz) PWM Frequency (FOSC) vs Temperature 1.61 1.60 1.59 1.58 1.57 1.56 1.55 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ Temperature (℃) 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) PWM Frequency (FOSC-MINFREQ) vs Temperature Reference Voltage (V REF ) vs Temperature 3.05 22.0 3.04 21.5 3.03 21.0 3.02 20.5 VREF (V) FOSC-MINFREQ (KHz) 35℃ Temperature (℃) 20.0 19.5 3.01 3.00 2.99 2.98 19.0 2.97 18.5 2.96 18.0 2.95 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40 Temperature (℃) © System General Corp. Version 1.3.1 (IAO33.0022.B3) -25 -10 5 20 35 50 65 80 95 110 125 Temperature (℃) - 11 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller Maximum Duty Cycle (DCMAX) vs Temperature 3.30 98.0 3.29 97.5 3.28 97.0 3.27 96.5 DCMAX (%) OVPPFC (V) PFC over Voltage Protection (OVPPFC) vs Temperature 3.26 3.25 3.24 96.0 95.5 95.0 3.23 94.5 3.22 94.0 3.21 93.5 3.20 93.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ Temperature (℃) 120.0 110.0 FBOPEN-LOOP (V) 100.0 T R (nS) 90.0 80.0 70.0 60.0 50.0 40.0 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 65℃ 80℃ 4.80 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 -40℃ -25℃ -10℃ 95℃ 110℃ 125℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) Temperature (℃) Falling Time (TF) vs Temperature PWM Open Loop Protection Delay Time (TOPEN-PWM) vs Temperature 110.0 75 72 100.0 69 TOPEN-PWM (mS) 90.0 TF (nS) 50℃ PWM Open Loop Protection voltage (FBOPEN-LOOP) vs Temperature Rising Time (T R) vs Temperature -40℃ -25℃ -10℃ 35℃ Temperature (℃) 80.0 70.0 60.0 66 63 60 57 54 51 50.0 48 40.0 45 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ Temperature () © System General Corp. Version 1.3.1 (IAO33.0022.B3) 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Temperature (℃) - 12 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller Peak Current Limit Threshold Voltge1 (V LIMIT-1) vs Temperature Fall Time (TF-PWM ) vs Temperature 0.75 110.0 0.74 100.0 0.73 90.0 TF-PWM (nS) VLIMIT-1 (V) 0.72 0.71 0.70 0.69 80.0 70.0 60.0 0.68 50.0 0.67 40.0 0.66 0.65 30.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ Temperature (℃) 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ Maximum Duty Cycle (DCMAXPWM) vs Temperature 0.70 83.0 0.69 82.0 0.68 81.0 0.67 80.0 DC MAXPWM (%) VLIMIT-2 (V) Peak Current Limit Threshold Voltage2 (V LIMIT-2) vs Temperature 0.66 0.65 0.64 0.63 79.0 78.0 77.0 76.0 0.62 75.0 0.61 74.0 0.60 73.0 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ Temperature (℃) 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 95℃ 110℃ 125℃ Temperature (℃) Rising Time (T R-PWM) vs Temperature OTP Threshold Voltage (VOTP-OFF ) vs Temperature 120.0 1.25 110.0 1.24 100.0 1.23 1.22 90.0 VOTP-OFF (V) TR-PWM (nS) 35℃ Temperature (℃) 80.0 70.0 60.0 1.21 1.20 1.19 1.18 50.0 1.17 40.0 1.16 30.0 1.15 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ Temperature (℃) © System General Corp. Version 1.3.1 (IAO33.0022.B3) 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ Temperature (℃) - 13 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller OPERATION DESCRIPTION The highly integrated SG6902 is designed for power supplies with boost PFC and flyback PWM. It requires very few external components to achieve green-mode operation and versatile protections / compensation. The patented interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light loads, the switching frequency is continuously decreased to reduce power consumption. If output loading is reduced, the PFC stage is turned off to further reduce power consumption. The PFC function is implemented by average-current-mode control. The patented switching charge multiplier-divider provides a high-degree noise immunity for the PFC circuit. The proprietary multi-vector output voltage control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, the SG6902 shuts off PFC to prevent extra-high voltage on output. Programmable two-level output voltage control reduces the PFC output voltage at low line input to increase the efficiency of the power supply. For the flyback PWM, the synchronized slope compensation ensures the stability of the current loop under continuous-mode operation. Built-in line-voltage compensation maintains constant output power limit. Hiccup operation during output overloading is also guaranteed. To prevent the power supply from drawing large current during start-up, the start-up for PFC stage is delayed 11.5ms after the operation of PWM stage. In addition, SG6902 provides complete protection functions, such as brownout, over-voltage, and RI pin open/short protections. Start-up Figure 1 shows the start-up circuit of the SG6902. A resistor RAC is utilized to charge VDD capacitor through S1. The turn-on and turn-off thresholds are fixed internally at 16V/10V. During start-up, the hold-up capacitor must be charged to 16V through the start-up resistor to enable SG6902. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10V during this start-up process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 14 - supply VDD during start-up. Since SG6902 consumes less than 25µA start-up current, the value of RAC can be large to reduce power consumption. One 10µF capacitor should hold enough energy for successful start-up. After start-up, S1 switches so that the current IAC is the input for PFC multiplier. This helps reduce circuit complexity and power consumption. FIG.1 Start-up Circuit Switching Frequency and Current Sources The switching frequency can be programmed by resistor RI connected between RI and GND. The relationship is: FOSC = 1560 (kHz) ----------RI (kΩ ) (1) For example, a 24kΩ resistor for RI results in a 65kHz switching frequency. Accordingly, a constant current, IT, flows through RI: IT = 1.2V (mA) ---------------RI (kΩ ) (2) IT is used to generate internal current reference. www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller Line-Voltage Detection (VRMS) Figure 2 shows a resistive divider with low-pass filtering for line-voltage detection on the VRMS pin. The VRMS voltage is used for the PFC multiplier, brownout protection, and range control. For brownout protection, the SG6902 is disabled with 195ms delay time if the voltage VRMS drops below 0.8V. For PFC multiplier and range control, refer to the sections below for details. FIG.3 Range Control Two-Level Output Voltage Interleave Switching and Green-Mode Operation The SG6902 uses interleaved switching to synchronize the PFC and flyback stages, which reduces switching noise and spreads the EMI emissions. Figure 4 shows off-time, TOFF, inserted between the turn-off of the PFC gate drive and the turn-on of the PWM. FIG.2 Line-Voltage Detection Circuit PFC Output Voltage Control (RANGE) For a universal input (90VAC ~ 264VAC) power supplies applying active boost PFC and flyback as a second stage, the output voltage of PFC is usually designed around 250V at low line and 390V at high line. This is to improve efficiency at low-line input. In SG6902, the RANGE pin (open-drain structure) is used for the two-level output voltage setting. Figure 3 shows the RANGE output that programs the PFC output voltage. The RANGE output is shorted to ground if the VRMS voltage exceeds 1.95V while high impedance (open) and the VRMS voltage drops below 1.6V. The output voltages can be designed using below equations: Range = Open ⇒ VO = R A + RB × 3V RB R + (RB // R C ) Range = Ground ⇒ VO = A × 3V (RB // R C ) © System General Corp. Version 1.3.1 (IAO33.0022.B3) ---- The off-time TOFF is increased in response to the decreasing of the voltage level of FBPWM. Therefore, the PWM switching frequency is continuously decreased to reduce switching losses. To further reduce power losses under extra light-load conditions, the PFC stage is turned off with a 650ms delay time. FIG.4 Interleaved Switching Pattern (3) - 15 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller FIG.5 Average-Current-Mode Control Loop PFC Operation The purpose of a boost active power factor corrector (PFC) is to shape the input current of a power supply. The input current waveform and phase follow that of the input voltage. Average-current-mode control is utilized for continuous-current-mode operation for the PFC booster. With the innovative multi-vector control for voltage loop and switching charge multiplier-divider for current reference, excellent input power factor is achieved with good noise immunity and transient response. Figure 5 shows the total control loop for the average-current-mode control circuit of SG6902. The current source output from the switching charge multiplier-divider can be expressed as: IMO = K × IAC × VEA (µA) -----------VRMS 2 (4) IIMP, the current output from the IMP pin, is the summation of IMO and IMR1. IMR1 and IMR2 are identical fixed-current sources. R2 and R3 are also identical. They are used to pull high the operating point of the IMP and IPFC pins since the voltage across RS goes negative with respect to ground. The constant current sources IMR1 and IMR2 are typically 60µA. Through the differential amplification of the signal across RS, better noise immunity is achieved. The output of IEA is compared with an internal sawtooth and the pulse width for PFC is determined. Through the average current-mode control loop, the input current, IS, is proportional to IMO: IMO × R 2 = IS × R S -------------------© System General Corp. Version 1.3.1 (IAO33.0022.B3) (5) - 16 - According to Equation 5, the minimum value of R2 and maximum of RS can be determined, because IMO should not exceed the specified maximum value. There are different concerns in determining the value of the sense resistor RS. The value of RS should be small enough to reduce power consumption, but large enough to maintain the resolution. A current transformer (CT) can improve the efficiency of high-power converters. To achieve good power factor, the voltage for VRMS and VEA should be kept as DC as possible, according to Equation 4. Good RC filtering for VRMS and narrow bandwidth (lower than the line frequency) for voltage loop are suggested for better input current shaping. The transconductance error amplifier has output impedance ZO (>90kΩ) and a capacitor CEA (1µF ~ 10µF) that should be connected to ground (as shown in Figure 5). This establishes a dominant pole f1 for the voltage loop: f1 = 1 ---------------------2π × R 0 ×CEA (6) The average total input power can be expressed as: Pin = VIN(rms) × IIN(rms) ∝ VRMS × IMO ∝ VRMS × ∝ VRMS × = 2× I AC × VEA ---------------- (7) VRMS 2 Vin × VEA R AC VRMS 2 VEA R AC VEA, the output of the voltage error amplifier, controls the total input power and the power delivered to the load. www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller Multi-vector Error Amplifier Cycle-by-Cycle Current Limiting The voltage-loop error amplifier is transconductance, which has high output impedance (> 90kΩ). A capacitor CEA (1µ ~ 10µF) connected from VEA to ground provides a dominant pole for the voltage loop. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of the PFC output voltage. SG6902 provides cycle-by-cycle current limiting for both PFC and PWM stages. Figure 7 shows the peak current limit for the PFC stage. The PFC gate drive is terminated once the voltage on the ISENSE pin goes below VPK. Figure 6 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage exceeds ±5% of the reference voltage, the transconductance error amplifier adjusts its output impedance to increase the loop response. If RA is opened, SG6902 shuts off immediately to prevent extra-high voltage on the output capacitor. The voltage of VRMS determines the voltage of VPK. The relationship between VPK and VRMS is shown in Figure 7. The amplitude of the constant current, IP, is determined by the internal current reference, IT, according to the following equation: IP = 2 × IT = 2 × 1.2V --------------------RI (8) The peak current of the IS is given by (VRMS<1.05V): IS_peak = (IP × RP ) - 0.2V RS ------------------ (9) FIG.7 VRMS Controlled Current Limiting FIG.6 Multi-vector Error Amplifier Flyback PWM and Slope Compensation PFC Over-Voltage Protection (OVP) When the OVP feedback voltage exceeds the over-voltage threshold, the SG6902 inhibits the PFC switching signal. This protection also prevents the PFC power converter from operating abnormally while the FBPFC pin is open. © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 17 - As shown in Figure 8, peak-current-mode control is utilized for flyback PWM. The SG6902 inserts a synchronized 0.5V ramp at the beginning of each switching cycle. This built-in slope compensation ensures stable operation for continuous-current-mode operation. When the IPWM voltage, across the sense resistor, reaches the threshold voltage, 0.65V or 0.7V selected by RANGE, the OPWM is turned off after a small propagation delay, TPD-PWM. This propagation delay introduces additional current, proportional to TPD-PWM•VPFC/Lp, where VPFC is the output voltage of PFC and Lp is the magnetized inductance of the flyback transformer. Since the propagation delay is nearly constant, higher VPFC results in a larger additional current www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller and the output power limit is higher than under low VPFC. To compensate for this variation, the peak current threshold is modulated by the RANGE output. When RANGE is shorted to GND, the PFC output voltage is high and the corresponding threshold is 0.65V. When RANGE is opened, the PFC output voltage is low and the corresponding threshold is 0.7V. FIG.8 Peak Current Control Loop SG6902 provides an OTP pin for over-temperature protection. A constant current is output from this pin. If RI is equal to 24kΩ, the magnitude of the constant current is 100µA. An external NTC thermistor must be connected from this pin to ground, as shown as Figure 9. When the OTP voltage drops below 1.2V, SG6902 is disabled until the OTP voltage exceeds 1.4V. Fig.9 OTP Function Limited Power Control Soft-Start Every time the output of power supply is shorted or overloaded, the FBPWM voltage increases. If the FB voltage is higher than a designed threshold, 4.5V, for longer than 56ms, the OPWM is turned off. As OPWM is turned off, the supply voltage VDD begins decreasing. When VDD is lower than the turn-off threshold, such as 10V, SG6902 is totally shut down. Due to the start-up resistor, VDD is charged up to the turn-on threshold voltage, 16V, until enabled again. If the overloading condition persists, the protection occurs repeatedly to prevent the power supply from being overheated during overloading condition. © System General Corp. Version 1.3.1 (IAO33.0022.B3) Over-Temperature Protection (OTP) - 18 - During start-up of PWM stage, the SS pin charges an external capacitor with a constant current source. The voltage on FBPWM is clamped by SS voltage during start-up. In the event of a protection condition and/or PWM being disabled, the SS pin quickly discharges. Gate Drivers SG6902 output stage is a fast totem-pole gate driver. The output driver is clamped by an internal 18V Zener diode to protect the power MOSFET. www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller PCB Layout SG6902 has two ground pins. Good high-frequency or RF layout practices should be followed. Avoid long PCB traces and component leads. Locate decoupling capacitors near the SG6902. A resistor (5 ~ 20Ω) is recommended, connected in series from the OPFC and OPWM, to the gate of the MOSFET. Isolating the interference between the PFC and PWM stages is also important. Figure 10 shows an example of the PCB layout. The ground trace connected from the AGND pin to the decoupling capacitor should be low impedance and as short as possible. The ground trace 1 provides a signal ground and should be connected directly to the decoupling capacitor VDD and/or to the AGND pin. The ground trace 2 shows that the AGND pins should connect to the PFC output capacitor CO independently. The ground trace 3 is independently tied from the PGND to the PFC output capacitor CO. The ground in the output capacitor CO is the major ground reference for power switching. To provide a good ground reference and reduce switching noise of both the PFC and PWM stages, the ground traces 6 and 7 should be located very near and be low impedance. The IPFC pin is connected directly to RS through R3 to improve noise immunity (do not incorrectly connect to ground trace 2). The IMP and ISENSE pins should be connected directly via the resistors R2 and RP to another terminal of RS. Because the ground trace 4 and 5 are PFC and PWM stages of the current loop, they should be as short as possible. Fig.10 Layout Considerations © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 19 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller REFERENCE CIRCUIT © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 20 - www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller PACKAGE INFORMATION 20 PINS – PLASTIC SOP (S) E H Detail A 1 F 10 b c e A D θ L A2 y A1 Detail A Dimensions: Symbol A A1 A2 b c D E e H L F y θ° Millimeter Min. 2.362 0.101 2.260 Typ. Max. 2.642 0.305 2.337 Inch Min. 0.093 0.004 0.089 0.406 0.203 12.598 7.391 12.903 7.595 0.496 0.291 10.643 1.270 0.394 0.016 © System General Corp. Version 1.3.1 (IAO33.0022.B3) 0.508 0.299 0.050 0.508X45° 0° Max. 0.104 0.012 0.092 0.016 0.008 1.270 10.007 0.406 Typ. 0.419 0.050 0.020X45° 0.101 8° - 21 - 0° 0.004 8° www.sg.com.tw • www.fairchildsemi.com September, 2007 Product Specification SG6902 Green-Mode PFC / Flyback-PWM Controller © System General Corp. Version 1.3.1 (IAO33.0022.B3) - 22 - www.sg.com.tw • www.fairchildsemi.com September, 2007