Revised March 2005 74LVT573 • 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs General Description Features The LVT573 and LVTH573 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. The LVTH573 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. ■ Input and output interface capability to systems at 5V VCC These octal latches are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT573 and LVTH573 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH573), also available without bushold feature (74LVT573) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink 32 mA/64 mA ■ Functionally compatible with the 74 series 573 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number Package Package Description Number 74LVT573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVT573SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVT573MSA MSA20 74LVT573MTC MTC20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVT573MTCX_NL (Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVTH573SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH573MSA MSA20 74LVTH573MTC MTC20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH573MTCX_NL (Note 1) MTC20 Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS012450 www.fairchildsemi.com 74LVT573 • 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs March 1999 74LVT573 • 74LVTH573 Pin Descriptions Logic Symbols Pin Names IEEE/IEC Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Latch Outputs Truth Table Inputs Connection Diagram LE OE Dn On X H X Z H L L L H L H H L L X O0 H HIGH Voltage Level L LOW Voltage Level Z High Impedance X Immaterial O0 Outputs Previous O0 before HIGH to LOW transition of Latch Enable Functional Description The LVT573 and LVTH573 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW, the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current Value Conditions 0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50 ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Units V V Output in 3-STATE Output in High or Low State (Note 3) V VI GND mA VO GND mA 64 VO ! VCC Output at High State 128 VO ! VCC Output at Low State mA r64 r128 65 to 150 mA mA qC Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V High-Level Output Current 32 mA Low-Level Output Current 64 mA VCC Supply Voltage VI Input Voltage IOH IOL TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 3.0V Units 40 85 qC 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol TA VCC (V) Parameter Min 40qC to 85qC Typ Max Units Conditions (Note 4) 1.2 VIK Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC 0.2 2.7 2.4 3.0 2.0 VOL II(HOLD) 2.7 Output LOW Voltage 2.0 0.8 100 PA IOL 24 mA IOL 16 mA 32 mA 0.5 IOL 3.0 0.55 IOL (Note 5) Current to Change State II Input Current 75 V PA 500 PA 500 Output Current 32 mA IOL 3.0 75 Power Up/Down 3-STATE 8 mA IOH 0.4 3.0 IPU/PD 100 PA IOH 0.5 Bushold Input Over-Drive Power Off Leakage Current IOH V 3.0 II(OD) IOFF VO t VCC 0.1V 2.7 (Note 5) Data Pins V 0.2 3.0 Control Pins II VO d 0.1V or 2.7 Bushold Input Minimum Drive 18 mA V V 64 mA VI 0.8V VI 2.0V (Note 6) (Note 7) 3.6 10 VI 5.5V 3.6 r1 VI 0V or VCC VI 0V VI VCC 5 3.6 PA 1 0 r100 PA 0–1.5V r100 PA 0V d VI or VO d 5.5V VO VI 0.5V to 3.0V GND or VCC IOZL 3-STATE Output Leakage Current 3.6 5 PA VO 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 PA VO 3.0V 3 www.fairchildsemi.com 74LVT573 • 74LVTH573 Absolute Maximum Ratings(Note 2) 74LVT573 • 74LVTH573 DC Electrical Characteristics Symbol (Continued) 40qC to 85qC TA VCC (V) Parameter Min Typ Max Units Conditions (Note 4) IOZH 3-STATE Output Leakage Current 3.6 10 PA VCC VO d 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ Power Supply Current 3.6 0.19 mA VCC d VO d 5.5V, 'ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC 0.6V Outputs Disabled (Note 8) Other Inputs at VCC or GND Note 4: All typical values are at VCC 3.3V, TA 25qC. Note 5: Applies to bushold versions only (74LVTH573). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol (Note 9) Parameter 25qC TA VCC (V) Min Typ Max Conditions Units CL 50 pF, RL 500: VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 10) VOLV Quiet Output Minimum Dynamic VOL 3.3 0.8 V (Note 10) Note 9: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA 40qC to 85qC CL 50 pF, RL 500: Symbol Parameter VCC Min 3.3V r 0.3V Typ (Note 11) VCC Max Min Units 2.7V Max tPHL Propagation Delay 1.5 4.4 1.5 4.9 tPLH Dn to On 1.5 4.1 1.5 4.7 tPHL Propagation Delay 1.9 4.4 1.9 4.9 tPLH LE to On 1.9 4.4 1.9 5.0 tPZL Output Enable Time 1.5 5.1 1.5 6.6 1.5 5.1 1.5 5.9 Output Disable Time 2.0 4.6 2.0 4.9 2.0 4.9 2.0 5.5 tPZH tPLZ tPHZ tS Setup Time, Dn to LE 0.7 ns ns ns ns 0.6 ns tH Hold Time, Dn to LE 1.5 1.7 ns tW LE Pulse Width 3.0 3.0 ns tOSHL Output to Output Skew (Note 12) tOSLH Note 11: All typical values are at VCC 3.3V, TA 1.0 1.0 1.0 1.0 ns 25qC. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 13) Typical Units CIN Symbol Input Capacitance Parameter VCC Open, VI 0V or VCC 4 pF COUT Output Capacitance VCC 3.0V, VO 0V or VCC 6 pF Note 13: Capacitance is measured at frequency f www.fairchildsemi.com Conditions 1 MHz, per MIL-STD-883, Method 3012. 4 74LVT573 • 74LVTH573 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74LVT573 • 74LVTH573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVT573 • 74LVTH573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com 74LVT573 • 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8