Ordering number : ENN7936 LC863548B, LC863540B LC863532B, LC863528B LC863524B, LC863520B LC863516B CMOS IC FROM 48K/40K/32K/28K/24K/20K/16K-byte, RAM 640/512-byte on-chip and 176 × 9-bit OSD RAM 8-bit 1-chip Microcontroller Overview The LC863548/40/32/28/24/20/16B are 8-bit single chip microcontrollers with the following on-chip functional blocks : • CPU : Operable at a minimum bus cycle time of 0.424µs • On-chip ROM capacity Program ROM : 48K/40K/32K/28K/24K/20K/16K-bytes CGROM : 16K-bytes • On-chip RAM capacity : 640/512-bytes • OSD RAM : 176 × 9-bits • On-screen display controller • Four channels × 6-bit AD Converter • Three channels × 7-bit PWM • Two channels × 16-bit timer/counter, 14-bit base timer • IIC-bus compliant serial interface circuit (Multi-master type) • ROM correction function • 13-source 8-vectored interrupt system • Integrated system clock generator and display clock generator Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators. All of the above functions are fabricated on a single chip. Ver.0.92 62102 73004 JO IM No.7936-1/17 LC863548B/40B/32B/28B/24B/20B/16B Features ■Read-Only Memory (ROM) : 49152 × 8-bits/40960 × 8-bits/32768 × 8-bits/ 28672 × 8-bits/24576 × 8-bits/20480 × 8-bits/ 16384 × 8-bits for program 16128 × 8-bits for CGROM ■Random Access Memory (RAM) : 512 × 8-bits (working area) : LC863548B/40B 384 × 8-bits (working area) : LC863532B/28B/24B/20B/16B 128 × 8-bits (working or ROM correction function) 176 × 9-bits (for CRT display) ■OSD functions • Screen display : 36 characters × 8 lines (by software) • RAM : 176 words (9-bits per word) Display area : 36 words × 4 lines Control area : 8 words × 4 lines • Characters Up to 252 kinds of 16 × 32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts (Ex. 16 × 16 dot character font × 2) • Various character attributes Character colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode) Character background colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode) Fringe/shadow colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode) Full screen colors : 16 colors (analog mode : l Vp-p output) /8 colors (digital mode) Rounding Underline Italic character (slanting) • Attribute can be changed without spacing • Vertical display start line number can be set for each row independently (Rows can be overlapped) • Horizontal display start position can be set for each row independently • Horizontal pitch (bit 9 to 16) *1 and vertical pitch (bit 1 to 32) can be set for each row independently • Different display modes can be set for each row independently Caption • Text mode/OSD mode 1/OSD mode 2 (Quarter size) /Simplified graphic mode • Ten character sizes *1 Horez. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4), (0.5 × 0.5) (1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.75 × 0.5) • Shuttering and scrolling on each row • Simplified Graphic Display *1 Note : range depends on display mode : refer to the manual for details. ■Bus Cycle Time/Instruction-Cycle Time Bus cycle time 0.424µs Instruction cycle time Clock divider 0.848µs 1/2 System clock oscillation Internal VCO (Ref : X'tal 32.768kHz) Oscillation frequency Voltage 14.156MHz 4.5V to 5.5V 7.5µs 15.0µs 1/2 Internal RC 800kHz 4.5V to 5.5V 91.55µs 183.1µs 1/1 Crystal 32.768kHz 4.5V to 5.5V 183.1µs 366.2µs 1/2 Crystal 32.768kHz 4.5V to 5.5V ■Ports • Input/Output Ports : 4 ports (24 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 3 ports (16 terminals) ■AD converter • 4-channels × 6-bit AD converters No.7936-2/17 LC863548B/40B/32B/28B/24B/20B/16B ■Serial interfaces • IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected internally. ■PWM output • 3-channels × 7-bit PWM ■Timer • Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. • Timer 1 : 16-bit timer/ PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : A variable-bit PWM (9 to 16 bits) In mode 0/1, the resolution of timer/PWM is 1 tCYC In mode 2/3, the resolution of timer/PWM is selectable by program ; tCYC or 1/2 tCYC • Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 ■Remote control receiver circuit (connected to the P73/INT3/T0IN terminal) • Noise rejection function • Polarity switching ■Watchdog timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ■ROM correction function Max 128-bytes/2 addresses ■Interrupts • 13 sources 8 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8-bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8-bits) 6. Timer T1H, Timer T1L 7. Vertical synchronous signal interrupt (VS), horizontal line (HS) 9. IIC, Software • Interrupt priority control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 8 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. No.7936-3/17 LC863548B/40B/32B/28B/24B/20B/16B ■Sub-routine stack level • A maximum of 128 levels (stack is built in the internal RAM) ■Multiplication/division instruction • 16-bits × 8-bits (7 instruction cycle times) • 16-bits ÷ 8-bits (7 instruction cycle times) ■3 oscillation circuits • Built-in RC oscillation circuit used for the system clock • Built-in VCO circuit used for the system clock and OSD • X’tal oscillation circuit used for base timer, system clock and PLL reference ■Standby function • HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. • HOLD mode The HOLD mode is used to stop the oscillations ; RC (internal), VCO, and X’tal oscillations. This mode can be released by the following conditions. 1. Pull the reset terminal (RES) to low level. 2. Feed the selected level to either P70/INT0 or P71/INT1. ■Package • MFP36S • DIP36S ■Development tools • Flash EEPROM • Evaluation chip • Emulator : LC86F3548A : LC863096 : EVA86000 (main) + ECB863200A (evaluation chip board) + SUB863400A (sub board) + POD36-CABLE (cable) + POD36-DIP (for DIP36S) or POD36-MFP (for MFP36S) No.7936-4/17 LC863548B/40B/32B/28B/24B/20B/16B Package Dimensions unit : mm 3204B Package Dimensions unit : mm 3170A No.7936-5/17 LC863548B/40B/32B/28B/24B/20B/16B Pin Assignment P10/SDA0 1 36 P03 P11/SCLK0 2 35 P02 P12/SDA1 3 34 P01 P13/SCLK1 4 33 P00 VSS 5 32 P17/PWM XT1 6 31 P16/PWM3 XT2 7 30 P15/PWM2 VDD 8 29 P14/PWM1 P04/AN4 9 28 P73/INT3/T0IN P05/AN5 10 27 P72/INT2/T0IN P06/AN6 11 26 P71/INT1 P07/AN7 12 25 P70/INT0 RES 13 24 P32 FILT 14 23 P31 P33 15 22 BL P30 16 21 B VS 17 20 G HS 18 19 R Top view No.7936-6/17 LC863548B/40B/32B/28B/24B/20B/16B System Block Diagram Interrupt Control IR X’tal RC VCO ROM Clock Generator Standby Control PLA PC PLL IIC ROM Correct Control ACC XRAM B Register Timer 0 Bus Interface C Register Timer 1 Port 1 ALU Base Timer Port 3 ADC Port 7 PSW INT0 to 3 Noise Rejection Filter RAR PWM RAM OSD Control Circuit CGROM VRAM Stack Pointer Port 0 Watch Dog Timer No.7936-7/17 LC863548B/40B/32B/28B/24B/20B/16B Pin Description Pin name VSS I/O Function - Negative power supply XT1 I Input terminal for crystal oscillator XT2 O Output terminal for crystal oscillator VDD - Positive power supply RES I Reset terminal FILT O Filter terminal for PLL VS I Vertical synchronization signal input terminal HS I Horizontal synchronization signal input terminal R O Red (R) output terminal of RGB image output G O Green (G) output terminal of RGB image output B O Blue (B) output terminal of RGB image output BL O Option Fast blanking control signal Switch TV image signal and caption/OSD image signal Port 0 I/O P00 to P07 • 8-bit input/output port Pull-up resistor Input/output can be specified in nibble unit provided/not provided (If the N-ch open drain output is selected by option, the corresponding port data can be Output Format read in output mode.) CMOS/Nch-OD • Other functions AD converter input port (P04 to P07 : 4 channels) Port 1 I/O • 8-bit input/output port Output Format Input/output can be specified for each bit P10 to P17 CMOS/Nch-OD (programmable pull-up resister provided) • Other functions Port 3 I/O P10 IIC0 data I/O P11 IIC0 clock output P12 IIC1 data I/O P13 IIC1 clock output P14 PWM1 output P15 PWM2 output P16 PWM3 output P17 Timer 1 (PWM) output • 4-bit input/output port Input/output can be specified for each bit P30 to P33 (CMOS output/input with programmable pull-up resister) Port 7 P70 P71 to P73 I/O • 4-bit input/output port Input or output can be specified for each bit P70 : I/O with programmable pull-up resister P71 to P73 : CMOS output/input with programmable pull-up resister • Other function P70 INT0 input/HOLD release input/ Nch-Tr. Output for watchdog timer P71 INT1 input/HOLD release input P72 INT2 input/Timer 0 event input P73 INT3 input (noise rejection filter connected) / Timer 0 event input Interrupt receiver format, vector addresses rising falling rising/ falling H level L level vector INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH Note : A capacitor of at least 10µF must be inserted between VDD and VSS when using this IC. Continued on next page. No.7936-8/17 LC863548B/40B/32B/28B/24B/20B/16B Continued from preceding page. • Output form and existence of pull-up resistor for all ports can be specified for each bit. • Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1. • Port status in reset Terminal I/O Port 0 I Pull-up resistor OFF, ON after reset release Pull-up resistor status at selecting CMOS output option Port 1 I Programmable pull-up resistor OFF Absolute Maximum Ratings / Ta = 25°C, VSS = 0V Pins Conditions Limits Parameter Symbol Supply voltage VDD max VDD Input voltage VI(1) RES, HS, VS -0.3 VDD+0.3 Output voltage VO(1) R, G, B, BL, FILT -0.3 VDD+0.3 Input/output voltage VIO Ports 0, 1, 3, 7 -0.3 VDD+0.3 High Peak IOPH(1) Ports 0, 1, 3, 7 level output output current VDD[V] typ R, G, B, BL current • CMOS output unit +7.0 • CMOS output -5 Total ΣIOAH(1) Ports 0, 1 The total of all pins. -20 output ΣIOAH(2) Ports 3, 7 The total of all pins. -10 ΣIOAH(3) R, G, B, BL The total of all pins. -12 mA Low Peak IOPL(1) Ports 0, 1, 3 For each pin. 20 level output IOPL(2) Port 7 For each pin. 15 output current IOPL(3) R, G, B, BL For each pin. 5 Total ΣIOAL(1) Ports 0, 1 The total of all pins. 40 output ΣIOAL(2) Ports 3, 7 The total of all pins. 20 ΣIOAL(3) R, G, B, BL The total of all pins. 12 Pd max MFP36S Ta = -10 to +70°C current current Maximum power dissipation Operating 340 DIP36S 500 Topr temperature range Storage V -4 • For each pin. current max -0.3 • For each pin. IOPH(2) min -10 +70 -55 +125 mW °C Tstg temperature range Recommended Operating Range / Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Operating supply VDD(1) voltage range VDD(2) Hold voltage VHD Pins VDD VDD Conditions Limits VDD [V] min typ max 0.844µs ≤ tCYC ≤ 0.852µs 4.5 5.5 4µs ≤ tCYC ≤ 400µs 4.5 5.5 2.0 5.5 0.6VDD VDD 4.5 to 5.5 0.75VDD VDD 4.5 to 5.5 VDD-0.5 VDD unit RAMs and the registers data are kept in HOLD mode. High level input VIH(1) Port 0 Output disable voltage VIH(2) • Ports 1, 3 (Schumitt) Output disable 4.5 to 5.5 V • Port 7 (Schumitt) port input/interrupt • RES, HS, VS (Schumitt) VIH(3) Port 70 Watchdog timer input Output disable Continued on next page. No.7936-9/17 LC863548B/40B/32B/28B/24B/20B/16B Continued from preceding page. Parameter Symbol Low level input VIL(1) voltage VIL(2) Pins Limits Conditions Port 0 Output disable • Ports 1, 3 (Schumitt) Output disable VDD [V] min typ max 4.5 to 5.5 VSS 0.2VDD 4.5 to 5.5 VSS 0.25VDD 4.5 to 5.5 VSS 0.6VDD unit • Port 7 (Schumitt) port input/interrupt • RES, HS, VS V (Schumitt) VIL(3) Port 70 Output disable Watchdog timer input Operation cycle time Oscillation tCYC(1) • All functions operating 4.5 to 5.5 0.844 tCYC(2) • OSD is not operating 4.5 to 5.5 0.844 FmRC Internal RC oscillation 4.5 to 5.5 0.4 frequency range 0.848 0.852 400 0.8 3.0 µs MHz Electrical Characteristics / Ta = -10°C to +70°C, VSS = 0V Parameter High level input Symbol IIH(1) Pins Ports 0, 1, 3, 7 current Conditions Limits VDD[V] min typ max unit • Output disable • Pull-up MOS Tr. OFF • VIN = VDD 4.5 to 5.5 1 4.5 to 5.5 1 (Including the off-leak current of the output Tr.) IIH(2) • RES • VIN = VDD • HS, VS Low level input IIL(1) Ports 0, 1, 3, 7 current µA • Output disable • Pull-up MOS Tr. OFF • VIN = VSS 4.5 to 5.5 -1 4.5 to 5.5 -1 4.5 to 5.5 VDD-1 VDD-0.5 (Including the off- leak current of the output Tr.) IIL(2) • RES VIN = VSS • HS, VS High level VOH(1) output voltage • CMOS output of IOH = -1.0mA ports 0, 1, 3, 71 to 73 VOH(2) R, G, B, BL IOH = -0.1mA R. G. B : digital mode 4.5 to 5.5 Low level VOL(1) Ports 0, 1, 3, 71 to 73 IOL = 10mA 4.5 to 5.5 1.5 output voltage VOL(2) Ports 0, 3, 71 to 73 IOL = 1.6mA 4.5 to 5.5 0.4 VOL(3) • R, G, B, BL IOL = 3.0mA • Port 1 R. G. B : digital mode 4.5 to 5.5 0.4 VOL(4) Port 70 IOL = 1mA 4.5 to 5.5 0.4 Rpu • Ports 0, 1, 3, 7 VOH = 0.9VDD Pull-up MOS Tr. resistance Bus terminal RBS 4.5 to 5.5 13 V 38 80 kΩ 4.5 to 5.5 130 300 Ω 4.5 to 5.5 0.1VDD V 4.5 to 5.5 10 pF • P10 to P12 • P11 to P13 short circuit resistance (SCL0 to SCL1, SDA0 to SDA1) Hysteresis VHIS voltage • Ports 1, 3, 7 Output disable • RES • HS, VS Pin capacitance CP All pins • f = 1MHz • Every other terminals are connected to VSS. • Ta = 25°C No.7936-10/17 LC863548B/40B/32B/28B/24B/20B/16B IIC Input/Output Conditions / Ta = -10°C to +70°C, VSS = 0V Parameter Standard Symbol SCL Frequency High speed unit min max min max 400 kHz fSCL 0 100 0 BUS free time between stop to start tBUF 4.7 - 1.3 - µs HOLD time of start, restart condition tHD ; STA 4.0 - 0.6 - µs tLOW 4.7 - 1.3 - µs L time of SCL H time of SCL tHIGH 4.0 - 0.6 - µs Set-up time of restart condition tSU ; STA 4.7 - 0.6 - µs HOLD time of SDA tHD ; DAT 0 - 0 0.9 µs Set-up time of SDA tSU ; DAT 250 - 100 - ns Rising time of SDA, SCL tR - 1000 20 + 0.1Cb 300 ns Falling time of SDA, SCL tF - 300 20 + 0.1Cb 300 ns tSU ; STO 4.0 - 0.6 - µs max unit Set-up time of stop condition Refer to figure 7 Note : Cb : Total capacitance of all BUS (unit : pF) Pulse Input Conditions / Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Pins Conditions High/low level pulse tPIH(1) •INT0, INT1 • Interrupt acceptable width tPIL(1) •INT2/T0IN • Timer 0-countable tPIH(2) INT3/T0IN • Interrupt acceptable tPIL(2) (1 tCYC is selected for • Timer 0-countable Limits VDD[V] min typ 4.5 to 5.5 1 4.5 to 5.5 2 4.5 to 5.5 32 noise rejection clock.) tCYC tPIH(3) INT3/T0IN • Interrupt acceptable tPIL(3) (16 tCYC is selected for • Timer 0-countable tPIH(4) INT3/T0IN • Interrupt acceptable tPIL(4) (64 tCYC is selected for • Timer 0-countable 4.5 to 5.5 128 4.5 to 5.5 200 4.5 to 5.5 3 noise rejection clock.) noise rejection clock.) tPIL(5) RES Reset acceptable tPIH(6) HS, VS • Display position tPIL(6) controllable (Note) • The active edge of HS and VS must be apart µs at least 1 tCYC. • Refer to figure 4. Rising/falling time tTHL Refer to figure 4. HS tTLH 4.5 to 5.5 500 ns AD Converter Characteristics / Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Resolution N Absolute precision ET Conversion time tCAD Pins Conditions Limits VDD [V] min typ (Note) Vref selection bit LSB 1-bit conversion time = 2 × tCYC µs 1.69 4.5 to 5.5 finish VAIN unit ±1 to conversion Analog input max 6 AN4 to AN7 VSS voltage range Analog port IAINH VAIN = VDD input current IAINL VAIN = VSS VDD 1 -1 V µA Note : Absolute precision does not include quantizing error (1/2LSB). No.7936-11/17 LC863548B/40B/32B/28B/24B/20B/16B Analog Mode RGB Characteristics / Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Pins Conditions Analog output R. G. B Low level output voltage Analog output mode Intensity output Hi level output Time setting R. G. B Limits VDD [V] 5.0 min typ max unit 0.45 0.5 0.55 0.90 1.0 1.10 1.35 1.5 1.65 70% 10pf load 50 V ns Sample Current Dissipation Characteristics / Ta = -10°C to +70°C, VSS = 0V The sample current dissipation characteristics are the measurement result of SANYO provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Current dissipation Symbol IDDOP(1) Pins VDD during basic Conditions Limits VDD [V] min typ max unit • FmX’tal = 32.768kHz X’tal oscillation operation • System clock : VCO (Note 3) • VCO for OSD operating 4.5 to 5.5 13 25 • OSD is Digital mode • Internal RC oscillation stops IDDOP(2) VDD mA • FmX’tal = 32.768kHz X’tal oscillation • System clock : VCO • VCO for OSD operating 4.5 to 5.5 21 37 4.5 to 5.5 50 300 µA 4.5 to 5.5 4 10 mA 4.5 to 5.5 300 1000 • OSD is Analog mode • Internal RC oscillation stops IDDOP(3) VDD • FmX’tal = 32.768kHz X’tal oscillation • System clock : X’tal (Instruction cycle time : 366.2µs) • VCO for system VCO for OSD, internal RC oscillation stop • Data slicer, AD converters stop Current dissipation IDDHALT(1) VDD in HALT mode • HALT mode • FmX’tal = 32.768kHz (Note 3) X’tal oscillation • System clock : VCO • VCO for OSD stops • Internal RC oscillation stops IDDHALT(2) VDD • HALT mode • FmX’tal = 32.768kHz X’tal oscillation • VCO for system stops • VCO for OSD stops • System clock : Internal RC IDDHALT(3) VDD µA • HALT mode • FmX’tal = 32.768kHz X’tal oscillation • VCO for system stops 4.5 to 5.5 35 200 4.5 to 5.5 0.05 20 • VCO for OSD stops • System clock : X’tal (Instruction cycle time : 366.2µs) Current dissipation in HOLD mode IDDHOLD VDD • HOLD mode • All oscillation stops. µA (Note 3) Note 3 : The currents through the output transistors and the pull-up MOS transistors are ignored. No.7936-12/17 LC863548B/40B/32B/28B/24B/20B/16B Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions : • Recommended circuit parameters are verified by an oscillator manufacturer using a SANYO provided oscillation evaluation board. • Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C) Frequency 32.768kHz Manufacturer Seiko Epson Oscillator C-002RX Recommended circuit parameters Operating supply C1 C2 Rf Rd 18pF 18pF OPEN 390kΩ voltage range 4.5 to 5.5V Oscillation stabilizing time typ max 1.00S 1.50S Notes Notes : The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with SANYO sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 XT2 Rf C1 X’tal Rd C2 Figure 1 Recommended oscillation circuit No.7936-13/17 LC863548B/40B/32B/28B/24B/20B/16B VDD VDD limit 0V Power supply Reset time RES Internal RC resonator oscillation XT1, XT2 tmsVCO VCO for system Operation mode stable Unfixed Reset Instruction execution mode <Reset time and oscillation stabilizing time> Valid HOLD release Internal RC resonator oscillation XT1, XT2 tmsVCO stable VCO for system Operation mode HOLD Instruction execution mode <HOLD release signal and oscillation stabilizing time> Figure 2 Oscillation stabilizing time No.7936-14/17 LC863548B/40B/32B/28B/24B/20B/16B tPIL (1) to (5) tPIH (1) to (4) Figure 3 Pulse input timing condition - 1 tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6) more than ±1tCYC Figure 4 Pulse input timing condition - 2 LC863548A 10kΩ HS HS C536 Figure 5 Recommended Interface circuit No.7936-15/17 LC863548B/40B/32B/28B/24B/20B/16B 100Ω FILT + 2.2µF - 1MΩ 33000pF Figure 6 FILT recommended circuit Note : Place FILT parts on board as close to the microcontroller as possible. S P Sr P SDA tBUF tF tHD ; STA tR tHD ; STA tsp SCL tLOW tHD ; DAT tHIGH tSU ; DAT S : start condition P : stop condition Sr : restart condition tSU ; STA tsp : Spike suppression tSU ; STO Standard mode : not exist High speed mode : less than 50ns Figure 7 IIC timing I ≈ 1mA ↓ I ↓ I ↓ PAD R≈ 500Ω Figure 8 R. G. B. analog output equivalent circuit No.7936-16/17 LC863548B/40B/32B/28B/24B/20B/16B PS No.7936-17/17