Ordering number : ENN*6697 CMOS IC LC865520B/16B/12B/08B/04B 8-Bit Single Chip Microcontroller with On-Chip 20/16/12/08/04K-Byte ROM and 512-Byte RAM Preliminary Overview The LC865520B/16B/12B/08B/04B are 8-bit single chip microcontrollers with the following one-chip features: - CPU : Operable at a minimum bus cycle time of 0.5µs - On-chip ROM Capacity : 20K/16K/12K/8K/4K bytes - On-chip RAM Capacity : 512 bytes (LC865520B/16B/12B/08B/04B) - 16-bit timer/counter (can be divided into two 8 bit timers) - 16-bit timer/PWM (can be divided into two 8 bit timers) - 8-channel × 8-bit AD converter - Two 8-bit synchronous serial-interface circuits - 13-source 10-vectored interrupt system Features (1) Read Only Memory (ROM) 20480 × 8 bits 16384 × 8 bits 12288 × 8 bits 8192 × 8 bits 4096 × 8 bits : LC865520B : LC865516B : LC865512B : LC865508B : LC865504B (2) Random Access Memory (RAM) : LC865520B/16B/12B/08B/04B 512 × 8 bits (3) Bus Cycle Time/Instruction Cycle Time The LC865520B/16B/12B/08B/04B are constructed to read ROM twice within one instruction cycle. It has 1.7 times the performance capability for the same instruction cycle compared to our 4-bit microcontrollers (LC66000 series). Bus cycle time indicates the speed to read ROM. Bus cycle time Instruction cycle time Clock divider 0.5µs 2µs 7.5µs 183µs Ver.1.02 32300 1µs 4µs 15µs 366µs System clock oscillation Oscillation Frequency Voltage 1/1 1/2 Ceramic (CF) Ceramic (CF) 6MHz 3MHz 4.5V to 6.0V 2.5V to 6.0V 1/2 1/2 Internal RC Crystal (XTAL) 800kHz 32.768kHz 2.5V to 6.0V 2.5V to 6.0V 11901 RM (IM) Chigira No.6697-1/21 LC865520B/16B/12B/08B/04B (4) Ports - Input/output ports : 3 ports (16 terminals : port 1,7,8) Input/output programmable for each bit individually - Maximum 15V withstand tolerance input/output port : 2 ports (15 terminals) Input/output programmable in nibble units : 1 port (8 terminals : port 0) (When the N-channel open drain output is selected, input/output can be specified by bit.) Input/output programmable for each bit individually : 1 port (7 terminals : port 3) - Input ports : 2 ports (6 terminals : port 7,8) (5) AD converter - 8-channel × 8-bit AD converter (6) Serial interface - 1 channel × 16-bit serial interface (8-bit transmission available by program) - 1 channel × 8-bit serial interface LSB first/MSB first-function available - An internal 8-bit baud-rate generator is common to both serial-interface circuits. (7) Timer - Timer 0 16-bit timer/counter 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with programmable prescaler Mode 1 : 8-bit timer with programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with programmable prescaler Mode 3 : 16-bit counter The resolution of Timer is tCYC. (tCYC: cycle time) - Timer 1 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable-bit PWM (9-16bits) In Mode 0 and Mode 1, the resolution of Timer and PWM is tCYC. In Mode 2 and Mode 3, the resolution of Timer and PWM is selectable by program: tCYC or 1/2 tCYC. - Base timer Generates an overflow every 500ms for a clock application (using 32.768kHz crystal oscillation for the base timer oscillator). Generates an overflow every 976µs, 3.9ms, 15.6ms or 62.5ms (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock, or programmable prescaler output of Timer 0. (8) Buzzer output - Built-in 4KHz and 2KHz buzzer generation function (using 32.768kHz crystal oscillation for the base timer oscillator) (9) Remote receiver circuit (share with P73/INT3/T0IN terminal) - Noise Rejection function (The filtering time of the noise rejection filter (1tCYC/16tCYC/64tCYC) can be switched by program.) (tCYC: instruction-cycle-time) - Polarity switch function (10) Watchdog timer - External RC circuit is required. - Interrupt or system reset is activated when the timer overflows. No.6697-2/21 LC865520B/16B/12B/08B/04B (11) Interrupt - 13-source and 10-vectored interrupt function: 1. External interrupt INT0 (including watchdog timer) 2. External interrupt INT1 3. External interrupt INT2, Timer/counter T0L (lower 8 bits of Timer 0) 4. External interrupt INT3, Base timer 5. Timer/counter T0H (upper 8 bits of Timer 0) 6. Timer T1L (lower 8 bits of Timer 1), Timer T1H (upper 8 bits of Timer 1) 7. Serial interface SIO0 8. Serial interface SIO1 9. AD converter 10. Port 0 - Built-in Interrupt Priority control register Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority level can be assigned to the 11 interrupt sources of interrupts 3 to 10 shown above by the interrupt priority control register. For the external interrupt INT0 and INT1(interrupt 1 and 2), low or highest can be set regardless of the interrupt priority register. (12) Sub-routine stack levels - A maximum of 128 levels (set stack inside RAM) (13) Multiplication and division 16 bits × 8-bit (7 instruction-cycle-times) 16 bits / 8-bit (7 instruction-cycle-times) (14) 3 types of oscillation circuits - Built-in RC oscillation circuit used for the system clock. - CF oscillation circuit used for the system clock. - Crystal oscillation circuit used for the system clock and the time-base clock. (15) Standby function - HALT mode The HALT mode stops the program execution, which minimizes power consumption. This operation mode can be released by a system reset or an interrupt request. - HOLD mode The HOLD mode stops all oscillation circuits: CF, RC and Crystal oscillations. This mode can be released by the following conditions. • Feed "L" level to the reset terminal ( RES ) • Feed the selected level to P70/INT0, P71/INT1 terminals • Feed "L" level to the Port 0 (16) Shipping form • DIP42S • QIP48E (17) Development tools Evaluation (EVA) chip EPROM version One time version Emulator : : : : LC866096 LC86E5420 LC86P5420 EVA-86000 + ECB867100 (Evaluation chip board) + POD865400 (POD) No.6697-3/21 LC865520B/16B/12B/08B/04B Notice for use 1. The following must be taken into consideration by the user: Oscillation frequency range for system clock. Supply voltage range Clock Divider 15kHz to 30kHz 30kHz to 6MHz 15kHz to 30kHz 30kHz to 1.5MHz 1.5MHz to 3MHz Internal RC oscillation 4.5V to 6.0V 2.5V to 6.0V 4.5V to 6.0V 2.5V to 6.0V 1/1 1/1,1/2 1/1 1/1,1/2 1/2 1/1,1/2 1/2 Notes Can not use 1/2 divider Can not use 1/2 divider Can not use 1/1 divider Can not use 1/1 divider No.6697-4/21 LC865520B/16B/12B/08B/04B Pin Assignment •DIP42S P00 P01 P02 P03 P04 P05 P06 P07 P70/INT0 RES XT1/P74 XT2/P75 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P17/PWM0 P16/BUZ P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P36 P35 P34 P33 P32 P31 P30 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P87/AN7 P86/AN6 P85/AN5 Package Dimension (unit : mm) 3025B SANYO : DIP-42S(600mil) No.6697-5/21 LC865520B/16B/12B/08B/04B Pin Assignment 36 35 34 33 32 31 30 29 28 27 26 25 P12/SCK0 P11/SI0/SB0 P10/SO0 P36 P35 P34 P33 NC P32 P31 P30 P73/INT3/T0IN •QIP48E 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 NC P72/INT2/T0IN P71/INT1 P87/AN7 P86/AN6 P85/AN5 NC P84/AN4 P83/AN3 P82/AN2 P81/AN1 P80/AN0 P05 P06 P07 P70/INT0 RES XT1/P74 NC XT2/P75 VSS CF1 CF2 VDD 1 2 3 4 5 6 7 8 9 10 11 12 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM0 NC P00 P01 P02 P03 P04 NC *Leave NC pins open. Package Dimension (unit : mm) 3156 SANYO : QIP-48E No.6697-6/21 LC865520B/16B/12B/08B/04B System Block Diagram IR Interrupt Control ROM RC Clock Generator Stand-by Control CR PLA PC X’tal Base Timer Bus Interface ACC SIO0 Port 1 B Register SIO1 Port 7 C Register Timer 0 Port 8 ALU Timer 1 Port 3 ADC PSW INT0-3 Noise Rejection Filter RAR RAM Stack Pointer Port 0 Watch Dog Timer No.6697-7/21 LC865520B/16B/12B/08B/04B Pin description Name VSS VDD PORT0 P00 to P07 I/O I/O PORT1 P10 to P17 I/O PORT3 P30 to P36 I/O PORT7 • 4-bit input/output port • Data direction programmable for each bit individually • 2-bit input port • Other functions I/O P70 : INT0 input/HOLD release input/N-ch Tr. output for watchdog timer I P71 : INT1 input/HOLD release input P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input P74 : Input terminal XT1 for 32.768kHz X'tal oscillation P75 : Output terminal XT2 for 32.768kHz X'tal oscillation • Interrupt detection style, vector address Rising Falling Rising/ H level L level Vector Falling INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH P70 to P73 P74, P75 Function description Power terminal (-) Power terminal (+) • 8-bit input/output port • Port 0 interrupt input • Data direction programmable in nibble units • HOLD release input • A withstand tolerance of 15V when selecting N-channel open drain output • 8-bit input/output port • Data direction programmable for each bit individually • Other functions P10 SIO0 data output P11 SIO0 data input, bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input, bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer 1 output (PWM0 output) • 7-bit input/output port • Data direction programmable for each bit individually • A withstand tolerance of 15V when selecting N-channel open drain output Option • Pull-up resistor : Provided/Not provided (specified in nibble units) • Output form : CMOS/N-channel open drain (specified by bit) • Output form : CMOS/N-channel open drain (specified by bit) • Pull-up resistor : Provided/Not provided (specified by bit) • Output form : CMOS/N-channel open drain (specified by bit) Continue. No.6697-8/21 LC865520B/16B/12B/08B/04B Name PORT8 P80 to 83 P84 to 87 I/O RES XT1/P74 I I XT2/P75 O CF1 CF2 I O I I/O Function description • 4-bit input port • Data direction programmable for each bit individually • 4-bit input/output port • Other function AD converter input port (8 pins) Reset • Input terminal for 32.768kHz X'tal oscillation • Other function XT1 : Input port P74 • When not in use, connect terminal to VDD • Output terminal for 32.768kHz X'tal oscillation • Other function XT2 : Input port P75 • When not in use - If set as port, connect terminal to VDD. - If set as oscillation, leave terminal open. Input terminal for ceramic resonator Output terminal for ceramic resonator Option - - - - * All port options (except pull-up resistor of port 0) can be specified by bit. A state of port terminals at reset Name Port 0 Ports 1,3 Input/output mode Input Input Style of pull-up resistors when pull-up option is enabled Fixed pull-up resistor OFF Programmable pull-up resistor OFF No.6697-9/21 LC865520B/16B/12B/08B/04B 1. Absolute Maximum Ratings at VSS=0V and Ta=25°C Parameter Supply voltage Input voltage Input/Output voltage High level output current Peak output current Total output current Low level output current Peak output current Total output current Maximum power consumption Operating temperature range Storage temperature range Symbol Pins VDDMAX VDD VI(1) • Ports 74,75 • Ports 80,81,82,83 • RES VIO(1) • Port 1 • Ports 70,71,72,73 • Ports 84,85,86,87 • Ports 0, 3 of CMOS output VIO(2) Ports 0, 3 of N-ch open drain output IOPH • Ports 0, 1, 3 • Ports 71,72,73 • Ports 84,85,86,87 ΣIOAH(1) Ports 0, 1 ΣIOAH(2) Port 3 ΣIOAH(3) • Ports 71,72,73 • Ports 84,85,86,87 IOPL(1) Ports 0, 1, 3 IOPL(2) • Ports 70,71,72,73 • Ports 84,85,86,87 ΣIOAL(1) Ports 0,1,70 ΣIOAL(2) Port 3 ΣIOAL(3) • Ports 71,72,73 • Ports 84,85,86,87 Pdmax(1) DIP42S Pdmax(2) QFP48E Conditions VDD VDD[V] min. -0.3 -0.3 Ratings unit typ. max. V +7.0 VDD+0.3 -0.3 VDD+0.3 -0.3 15 • CMOS output • For each pin -10 Total of all pins Total of all pins Total of all pins -30 -15 -10 mA For each pin For each pin 20 15 Total of all pins Total of all pins Total of all pins 60 40 20 Ta= -30 to+70°C Ta= -30 to+70°C 630 350 mW °C Topr -30 70 Tstg -55 125 No.6697-10/21 LC865520B/16B/12B/08B/04B 2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V Parameter Operating Supply voltage range Hold voltage Input high voltage Symbol VDD(1) VDD VDD(2) VHD VIH(1) VIH(2) VIH(3) VIH(4) VIH(5) VIH(6) VIH(7) Input low voltage Pins VIL(1) VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) Operation tCYC cycle time Oscillation FmCF(1) frequency range (Note 1) FmCF(2) FmRC FsXtal Conditions VDD[V] 0.98µs ≤ tCYC ≤ 400µs min. 4.5 3.9µs ≤ tCYC ≤ 400µs 2.5 Ratings typ. max. 6.0 unit V 6.0 VDD RAM and register data 2.0 6.0 are kept in HOLD mode. Port 0 of CMOS output Output disable 2.5 to 6.0 0.33VDD VDD +1.0 Port 0 of N-ch open Output disable 4.0 to 6.0 0.75VDD 13.5 drain output 2.5 to 4.0 0.8VDD 13.5 • Port 1 Output disable 2.5 to 6.0 0.75VDD VDD • Ports 72,73 • Port 3 of CMOS output Port 3 of N-ch open Output disable 4.0 to 6.0 0.75VDD 13.5 drain output 2.5 to 4.0 0.8VDD 13.5 Output disable 2.5 to 6.0 0.75VDD VDD • Port 70 Port input/interrupt • Port 71 • RES Port 70 Output disable 2.5 to 6.0 0.9VDD VDD Watchdog timer • Port 8 • Output disable 2.5 to 6.0 0.75VDD VDD • Ports 74,75 • Using as port Port 0 of CMOS output Output disable 2.5 to 6.0 VSS 0.2VDD Port 0 of N-ch open Output disable 2.5 to 6.0 VSS 0.25VDD drain output • Ports 1,3 Output disable 2.5 to 6.0 VSS 0.25VDD • Ports 72,73 Output disable 2.5 to 6.0 VSS 0.25VDD • Port 70 Port input/interrupt • Port 71 • RES Port 70 Output disable 2.5 to 6.0 VSS 0.8VDD Watchdog timer to 1.0 • Port 8 • Output disable 2.5 to 6.0 VSS 0.25VDD • Ports 74,75 • Using as port 4.5 to 6.0 0.98 400 µs 2.5 to 6.0 3.9 400 CF1, CF2 • 6MHz 4.5 to 6.0 5.88 6 6.12 MHz (ceramic resonator) • Refer to figure 1 CF1, CF2 •3MHz 2.5 to 6.0 2.94 3 3.06 (ceramic resonator) • Refer to figure 1 Internal RC oscillation 2.5 to 6.0 0.3 0.8 3.0 XT1, XT2 •32.768kHz 2.5 to 6.0 32.768 kHz (crystal oscillation) • Refer to figure 2 Continue. No.6697-11/21 LC865520B/16B/12B/08B/04B Parameter Symbol Pins Conditions Oscillation stabilizing time (Note 1) tmsCF(1) CF1, CF2 tmsCF(2) CF1, CF2 •6MHz (ceramic resonator) • Refer to figure 3 •3MHz (ceramic resonator) • Refer to figure 3 •32.768kHz (crystal oscillation) • Refer to figure 3 tssXtal XT1, XT2 VDD[V] 4.5 to 6.0 min. Ratings typ. max. unit ms 4.5 to 6.0 2.5 to 6.0 4.5 to 6.0 s 2.5 to 6.0 (Note 1) The oscillation parameters are shown on table 1 and 2. No.6697-12/21 LC865520B/16B/12B/08B/04B 3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V Parameter Input high current Symbol IIH(1) Ports 0,3 of open drain output IIH(2) • Port 0 without pull-up MOS Tr. • Ports 1,3 • Ports 70,71,72,73 • Port 8 IIH(3) IIH(4) Input low current IIL(1) IIL(2) IIL(3) Output high voltage Output low voltage Pins RES Ports 74,75 • Ports 1,3 • Port 0 without pull-up MOS Tr. • Ports 70,71,72,73 • Port 8 RES Ports 74,75 VOH(1) • Ports 0,1,3 of CMOS output VOH(2) • Ports 71,72,73 • Ports 84,85,86,87 VOL(1) Ports 0,1,3 VOL(2) VOL(3) VOL(4) • Ports 71,72,73 VOL(5) • Ports 84,85,86,87 VOL(6) Port 70 VOL(7) Pull-up MOS Rpu Tr. resistor Hysteresis voltage VHIS Pin capacitance CP • Ports 0,1,3 • Ports 70,71,72,73 • Ports 84,85,86,87 • Port 1 • Ports 70,71,72,73 • RES All pins Conditions • Output disable • VIN=13.5V (including the off-leak current of the output Tr.) • Output disable • Pull-up MOS Tr. OFF. • VIN=VDD (including the off-leak current of the output Tr.) VIN=VDD • VIN=VDD • Using as port • Output disable • Pull-up MOS Tr. OFF. • VIN=VSS (including the off-leak current of the output Tr.) VIN=VSS • VIN=VSS • Using as port IOH=-1.0mA VDD[V] min. Ratings typ. max. 2.5 to 6.0 5 2.5 to 6.0 1 2.5 to 6.0 2.5 to 6.0 1 1 2.5 to 6.0 -1 2.5 to 6.0 2.5 to 6.0 -1 -1 4.5 to 6.0 VDD-1 2.5 to 6.0 VDD-0.5 IOL=10mA IOL=1.6mA • IOL=1.0mA • Every pin's IOL ≤ 1mA IOL=1.6mA 4.5 to 6.0 4.5 to 6.0 2.5 to 6.0 1.5 0.4 0.4 4.5 to 6.0 0.4 • IOL=0.5mA • Every pin's IOL ≤ 1mA IOL=1mA 2.5 to 6.0 0.4 Output disable 4.5 to 6.0 0.4 2.5 to 6.0 0.4 4.5 to 6.0 15 40 70 2.5 to 4.5 25 70 150 2.5 to 6.0 • f=1MHz 2.5 to 6.0 • All pins except the measured terminal: VIN=VSS • Ta=25°C µA V IOH=-0.1mA • IOL=0.5mA • Every pin's IOL ≤ 1mA VOH=0.9VDD unit kΩ 0.1VDD V 10 pF No.6697-13/21 LC865520B/16B/12B/08B/04B 4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V Serial output Serial input Input clock Output clock Serial clock Parameter Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Symbol Pins tCKCY(1) tCKL(1) SCK0,SCK1 Conditions Refer to figure 5 VDD[V] min. 2.5 to 6.0 2 1 tCKH(1) tCKCY(2) tCKL(2) tICK Data hold time tCKI Output delay time (External clock used for serial transfer clock) tCKO(1) Output delay time (Internal clock used for serial transfer clock) tCKO(2) max. unit tCYC 1 SCK0,SCK1 tCKH(2) Data set-up time Ratings typ. • SI0,SI1 • SB0,SB1 • SO0,SO1 • SB0,SB1 • Use a 1kΩ pullup resistor in the open drain output. • Refer to figure 5 • Data set-up to SCK0,1 • Data hold from SCK0,1 • Refer to figure 5 • Use a 1kΩ pullup resistor in the open drain output. • Data hold from SCK0,1 • Refer to figure 5 2.5 to 6.0 2 1/2tCKCY 1/2tCKCY 4.5 to 6.0 0.1 2.5 to 6.0 4.5 to 6.0 2.5 to 6.0 4.5 to 6.0 0.4 0.1 0.4 µs 7/12 tCYC +0.2 2.5 to 6.0 7/12 tCYC 4.5 to 6.0 1/3 +1 tCYC +0.2 2.5 to 6.0 1/3 tCYC +1 No.6697-14/21 LC865520B/16B/12B/08B/04B 5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V Parameter Symbol Pins Conditions High/low level pulse width tPIH(1) tPIL(1) tPIH(2) tPIL(2) • INT0, INT1 • INT2/T0IN INT3/T0IN (The noise rejection clock is selected to 1/1.) INT3/T0IN (The noise rejection clock is selected to 1/16.) INT3/T0IN (The noise rejection clock is selected to 1/64.) • Interrupt acceptable • Timer0-countable • Interrupt acceptable • Timer0-countable tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) RES VDD[V] 2.5 to 6.0 min. 1 2.5 to 6.0 2 • Interrupt acceptable • Timer0-countable 2.5 to 6.0 32 • Interrupt acceptable • Timer0-countable 2.5 to 6.0 128 Reset acceptable 2.5 to 6.0 200 Ratings typ. max. unit tCYC µs 6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS=0V Parameter Resolution Absolute precision (Note 2) Conversion time Symbol Pins Conditions N ET AD conversion time = 16 × tCYC (ADCR2=0) (Note 3) tCAD VAIN IAINH IAINL min. Ratings typ. 8 max. ±1.5 AD conversion time = 32 × tCYC (if ADCR2=1) (Note 3) Analog input voltage range Analog port input current VDD[V] 4.5 to 6.0 AN0 - AN7 VAIN=VDD VAIN=VSS 15.68 (tCYC= 0.98µs) 31.36 (tCYC= 0.98µs) VSS unit bit LSB 65.28 (tCYC= 4.08µs) 130.56 (tCYC= 4.08µs) VDD µs 1 µA V -1 (Note 2) Absolute precision excludes the quantizing error (±1/2 LSB). (Note 3) The conversion time is the time from executing the AD conversion instruction to setting the complete digital conversion value in the register. No.6697-15/21 LC865520B/16B/12B/08B/04B 7. Sample Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V Parameter Current drain during basic operation (Note 4) Symbol Pins IDDOP(1) VDD IDDOP(2) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) Conditions • FmCF=6MHz by ceramic resonator • FsXtal=32.768kHz by crystal oscillation • System clock : CF oscillation (6MHZ) • Internal RC oscillation stops • 1/1 divided • FmCF=3MHz by ceramic resonator • FsXtal=32.768kHz by crystal oscillation • System clock : CF oscillation (3MHz) • Internal RC oscillation stops • 1/2 divided • FmCF=0Hz (when oscillation stops) • FsXtal=32.768kHz by crystal oscillation • System clock : RC oscillation • 1/2 divided • FmCF=0Hz (when oscillation stops) • FsXtal=32.768kHz by crystal oscillation • System clock : X'tal oscillation (32.768kHz) • Internal RC oscillation stops • 1/2 divided Ratings typ. 12 max. 22 4.5 to 6.0 3 7 2.5 to 4.5 2.0 5 4.5 to 6.0 1.2 3 2.5 to 4.5 1.0 2.5 4.5 to 6.0 35 130 2.5 to 4.5 25 70 VDD[V] 4.5 to 6.0 min. unit mA µA Continue. No.6697-16/21 LC865520B/16B/12B/08B/04B Parameter Symbol Pins Current drain IDDHALT(1) VDD in HALT mode (Note 4) IDDHALT(2) IDDHALT(3) IDDHALT(4) IDDHALT(5) IDDHALT(6) IDDHALT(7) Current drain IDDHOLD(1) VDD in HOLD mode (Note 4) IDDHOLD(2) Conditions • HALT mode • FmCF=6MHz by ceramic resonator • FsXtal=32.768kHz by crystal oscillation • System clock : CF oscillation (6MHz) • Internal RC oscillation stops • 1/1 divided • HALT mode • FmCF=3MHz by ceramic resonator • FsXtal=32.768kHz by crystal oscillation • System clock : CF oscillation (3MHz) • Internal RC oscillation stops • 1/2 divided • HALT mode • FmCF=0Hz (when oscillation stops) • FsXtal=32.768kHz by crystal oscillation • System clock : RC oscillation •1/2 divided • HALT mode • FmCF=0Hz (when oscillation stops) • FsXtal=32.768kHz by crystal oscillation • System clock : X'tal oscillation (32.768kHz) • Internal RC oscillation stops • 1/2 divided HOLD mode Ratings typ. 7 Max. 12 4.5 to 6.0 2.2 5 2.5 to 4.5 1.2 3 4.5 to 6.0 800 2000 2.5 to 4.5 500 1500 4.5 to 6.0 25 100 2.5 to 4.5 12 55 4.5 to 6.0 0.06 30 2.5 to 4.5 0.02 20 VDD[V] 4.5 to 6.0 min. unit mA µA (Note 4) The current of the output transistors and pull-up MOS transistors are excluded. No.6697-17/21 LC865520B/16B/12B/08B/04B Recommended Oscillation Circuit and Characteristics The recommended circuit parameters are verified by an oscillator manufacturer using a SANYO provided oscillation evaluation board. Table 1. Recommended circuit parameters for the main system clock using the ceramic resonator Frequency Manufacturer 6MHz 3MHz Recommended circuit parameter C1 C2 Rd1 33pF 33pF 470Ω (15pF) (15pF) 470Ω Oscillator MURATA CSA6.00MG CSTS0600MG03 MURATA CSA3.00MG CST3.00MGW 33pF (30pF) 33pF (30pF) 470Ω 470Ω Operating supply voltage range Note 4.5V to 6.0V 4.5V to 6.0V Internal C1, C2 2.5V to 6.0V 2.5V to 6.0V Internal C1, C2 Table 2. Recommended circuit parameters for the sub system clock using the crystal oscillation Frequency Manufacturer 32.768kHz SEIKO EPSON Recommended circuit parameter Oscillator MC-306 C3 C4 Rd2 18pF 18pF 560Ω Operating supply voltage range Note 2.5V to 6.0V The recommended circuit parameter may vary according to the applications. For further assistance, please contact the oscillator manufacturer keeping the following in mind. !"Since the oscillation frequency precision is affected by the wiring capacitance of the application board, etc., is it required to adjust the oscillation frequency on the production board. !"The oscillation frequency and the recommended circuit parameter shown above apply when the operating temperature range is -30°C to +70°C. When using the clock oscillation circuit under the conditions which exceed the operating temperature range or in applications that require precision tolerances, please contact the oscillator manufacturer. !"If using other circuit parameter than listed above, please contact SANYO. Since the gain of oscillation circuit is reduced in order to minimize the power consumption of the circuit and the circuit can be affected by the noise, wiring capacity, etc., it is suggested to take the followings into consideration. !"The distance between the clock I/O terminals (XT1, XT2) and external parts should be as short as possible. !"The capacitors' (C1, C2) VSS should be placed close to the microcontroller's GND terminal and away from any other GND. !"The signal lines with large current or with rapid state changes should be placed away from the oscillation circuit. CF1 CF2 XT1 XT2 Rd2 Rd1 CF C1 Figure 1 X’tal C2 Ceramic oscillation circuit C3 Figure 2 C4 Crystal oscillation circuit No.6697-18/21 LC865520B/16B/12B/08B/04B VDD VDD limit 0V Power supply Reset time RES RC oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode Unstable Instruction execution OCR6=1 Reset Instruction execution <Reset time and oscillation stabilizing time> HOLD release signal Valid RC oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode HOLD Instruction execution <HOLD release signal and oscillation stabilizing time> (OCR6=1when entering HOLD) Figure 3 Oscillation stabilizing time No.6697-19/21 LC865520B/16B/12B/08B/04B VDD (Note) Select CRES and RRES value to assure that at least 200µs reset time is generated after the VDD becomes higher than the minimum operating voltage. RRES RES CRES Figure 4 Reset circuit 0.5VDD <AC timing point> tCKCY tCKL VDD tCKH SCK0 SCK1 1kΩ tICK tCKI SI0 SI1 tCKO 50pF SO0, SO1 SB0, SB1 <Timing> Figure 5 tPIL Figure 6 <Test load> Serial input / output test condition tPIH Pulse input timing condition No.6697-20/21 LC865520B/16B/12B/08B/04B memo: PS No.6697-21/21