Ordering number : ENN7972 LC875BP4A LC875BM2A LC875BJ0A LC875BH4A CMOS IC ROM 256K/224K/192K/176K byte, RAM 4096K byte on-chip 8-bit 1-chip Microcontroller Overview The LC875BP4A, LC875BM2A, LC875BJ0A, LC875BH4A is 8-bit single chip microcontroller with the following onechip features : • CPU : Operable at a minimum bus cycle time of 100ns • On-chip ROM Capacity : LC875BP4A 256K bytes : LC875BM2A 224K bytes : LC875BJ0A 192K bytes : LC875BH4A 176K bytes • On-chip RAM Capacity : 4K bytes • Two high performance 16-bit timer/counters (can be divided into 8-bit timers) • Four 8-bit timers with prescalers • Timer for use as date/time clock • Two synchronous serial I/O ports (with automatic block transmit/receive function) • One asynchronous/synchronous serial I/O port • Two UART ports (full duplex) • 12-bit PWM × 4 • 12-channel × 8-bit AD converter • High speed clock counter • System clock divider • 27-source 10-vectored interrupt system Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. Ver.1.00 92706 / 81205HKIM B8-7735 No.7972-1/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Features Read Only Memory (ROM) • 262144 × 8-bits (LC875BP4A) • 229376 × 8-bits (LC875BM2A) • 196608 × 8-bits (LC875BJ0A) • 180224 × 8-bits (LC875BH4A) Random Access Memory (RAM) : 4096 × 9-bit Bus Cycle Time • 100ns (10MHz) Note : Bus cycle time indicates the speed to read ROM. Minimum Instruction Cycle Time (tCYC) • 300ns (10MHz) Ports • Input/output ports Input/output programmable for each bit individually Data direction programmable in two bits Data direction programmable in nibble units • Input ports • Oscillator pins • Reset pin • Power supply 64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn, S2Pn, PWM0, PWM1, XT2) 16 (PEn, PFn) 8 (P0n) 1 (XT1) 2 (CF1, CF2) 1 (RES) 8 (VSS1 to 4, VDD1 to 4) Timer • Timer 0 : 16-bit timer/counter with capture register Mode 0 :8-bit timer with 8-bit programmable prescaler (with an 8-bit capture register) × 2-channels Mode 1 :8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with 8-bit capture register) Mode 2 :16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3 :16-bit counter (with a 16-bit capture register) • Timer 1 : 16-bit timer/counter that support PWM/ toggle output Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs ) Mode 1 : 8-bit PWM with an 8-bit prescaler × 2-channels Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (Toggle outputs also present at the lower-order 8-bits) Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8-bits can be used as PWM.) • Timer 4 : 8-bit timer with a 6-bit prescaler • Timer 5 : 8-bit timer with a 6-bit prescaler • Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer 1. The clock is selectable from sub-clock (32.768kHz crystal oscillation), system clock or programmable prescaler output of timer 0. 2. Interrupt are programmablein 5 different time schemes. High Speed Clock Counter 1. Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2. Can generate output real time. No.7972-2/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Serial Interface • SIO 0 : 8-bit synchronous serial interface 1. LSB first/MSB first-function available 2. An internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC) 3. Consecutive automatic data communication (1 to 256-bits) • SIO 1 : 8-bit asynchronous/synchronous serial interface Mode 0 : Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC) Mode 1 : Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud-rate 8 to 2048 tCYC) Mode 2 : Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC) Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection) • SIO2 : 8-bit synchronous serial interface 1. LSB-first 2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC) 3. Consecutive automatic data communication (1 to 32 bytes) UART :2-channels 1. Full duplex 2. 7/8/9 bit data bits selectable 3. 1stop bit 4. built-in baudrate generator AD Converter • 12-channel × 8-bit AD converter PWM • 4-channel × synchronous variable 12-bit PWM Remote Receiver Circuit (share with P73/INT3/T0IN terminal) • Noise rejection function (The filtering time of the noise rejection filter (1tCYC/32 tCYC/128 tCYC) can be switched by program.) Watchdog Ttimer • External RC circuit is required. • Interrupt or system reset is activated when the timer overflows. Interrupts • 27-source and 10-vectored interrupt function : 1. Three interrupt priorities, low (L), high (H) and highest (X) are supported with multi-level nesting possible. During interrupt handling, an equal or lower level interrupt request is refused. 2. If interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Selectable Level 1 00003H X or L Interrupt Signal 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1, 2 receive 8 0003BH H or L SIO1/SIO2/UART1, 2 transmit 9 00043H H or L ADC/T6/T7/PWM4, PWM5 10 0004BH H or L Port 0/T4/T5/PWM0, PWM1 INT0 • Priority Level : X > H > L • For equal priority levels, vector with lowest address takes precedence. No.7972-3/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Subroutine Stack Levels • A maximum of 3072 levels (set stack inside RAM) Multiplication and division • 16-bits × 8-bits (5 instruction-cycle times) • 24-bits × 16-bits (12 instruction-cycle times) • 16-bits ÷ 8-bits (8 instruction-cycle times) • 24-bits ÷ 16-bits (12 instruction-cycle times) Oscillation Circuits • Built-in RC oscillation circuit used for the system clock • CF oscillation circuit used for the system clock • Crystal oscillation circuit used for the system clock System Clock Divider • Operable on the lowest power consumption • Minimum instruction cycle time (300ns, 600ns, 1.2µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched by program (when using 10MHz main clock) Standby Function • HALT mode The HALT mode stops program execution while the peripheral circuits keep operating and minimizes power consumption. This operation mode can be released by a system reset or an interrupt request. • HOLD mode The HOLD mode stops program execution and all oscillation circuits : CF, RC and Crystal oscillations. This mode can be released by the following conditions. 1. Supply "L" level to the reset terminal (RES) 2. Supply the selected level to at lease one of INT0, INT1, INT2, INT4, INT5. 3. Supply an interrupt condition to Port 0. • X’tal HOLD mode The X’tal HOLD mode stops program execution and all peripheral circuits except for the base timer. The crystal oscillator maintains its state at HOLD mode inception. This mode can be released by the following conditions. 1. Supply "L" level to the reset terminal (RES). 2. Supply the selected level to at least one of INT0, INT1, INT2, INT4, INT5. 3. Supply an interrupt condition to Port 0. 4. Supply an interrupt condition to the base timer circuit. Shipping Form • QFP100E (Lead Free Product) • TQFP100 (Lead Free Product) Development Tools • Evaluation (EVA) chip : LC87EV690 • Emulator : EVA62S + ECB876600D + SUB875200 + POD100QFP or POD100SQFP Type B : ICE-B877300 + SUB875200 + POD100QFP or POD100SQFP Type B No.7972-4/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Package Dimensions unit : mm 3151A Package Dimensions unit : mm 3274 No.7972-5/25 LC875BP4A/875BM2A/875BJ0A/875BH4A SI2P2/SCK2 SI2P3/SCK20 PWM1 VDD2 PWM0 VSS2 P00 P01 P02 P03 P04 P05/CKO P06/T6O P07/T7O P20/INT4/T1IN P21/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN P24/INT4/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN P30/PWM4 P31/PWM5 P32/UTX1 P33/URX1 P34/UTX2 P35/URX2 P36 PB7 Pin Assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB6 81 50 SI2P1/SI2/SB2 PB5 82 49 SI2P0/SO2 PB4 83 48 PF7 PB3 84 47 PF6 PB2 85 46 PF5 PB1 86 45 PF4 PB0 87 44 PF3 VSS3 88 43 PF2 VDD3 89 42 PF1 PC7 90 41 PF0 PC6 91 40 VDD4 PC5 92 39 VSS4 PC4 93 38 PE7 PC3 94 37 PE6 PC2 95 36 PE5 PC1 96 35 PE4 PC0 97 34 PE3 PA0 98 33 PE2 PA1 99 32 PE1 PA2 100 31 PE0 LC875BP4A/ LC875BM2A/ LC875BJ0A/ LC875BH4A P17/T1PWMH/BUZ P15/SCK1 P16/T1PWML P14/SI1/SB1 P13/SO1 P12/SCK0 P11/Si0/SB0 P10/SO0 RES P87/AN7 P73/INT3/T0IN P86/AN6 P72/INT2/T0IN P85/AN5 P71/INT1/T0HCP/AN9 P84/AN4 P70/INT0/T0LCP/AN8 P83/AN3 PA5 P82/AN2 PA4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P81/AN1 8 P80/AN0 7 VDD1 6 CF2 5 CF1 4 VSS1 3 XT2/AN11 2 XT1/AN10 1 PA3 QIP100E Top view No.7972-6/25 PWM0 VDD2 VSS2 P00 P01 P02 P03 P04 P05/CKO P06/T6O P07/T7O P20/INT4/T1IN P21/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN P24/INT5/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN P30/PWM4 P31/PWM5 P32/UTX1 P33/URX1 P34/UTX2 P35/URX2 LC875BP4A/875BM2A/875BJ0A/875BH4A 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P36 76 50 PWM1 PB7 77 49 SI2P3/SCK20 PB6 78 48 SI2P2/SCK2 PB5 79 47 SI2P1/SI2/SB2 PB4 80 46 SI2P0/SO2 PB3 81 45 PF7 PB2 82 44 PF6 PB1 83 43 PF5 PB0 84 42 PF4 VSS3 85 41 PF3 VDD3 86 40 PF2 PC7 87 39 PF1 PC6 88 38 PF0 PC5 89 37 VDD4 PC4 90 36 VSS4 PC3 91 35 PE7 PC2 92 34 PE6 PC1 93 33 PE5 PC0 94 32 PE4 PA0 95 31 PE3 PA1 96 30 PE2 PA2 97 29 PE1 PA3 98 28 PE0 PA4 99 27 P17/T1PWMH/BUZ PA5 100 26 P16/T1PWML LC875BP4A/ LC875BM2A/ LC875BJ0A/ LC875BH4A XT2/AN11 VSS1 CF1 CF2 P15/SCK1 XT1/AN10 P14/SI1/SB1 RES P13/SO1 P73/INT3/T0IN P12/SCK0 P72/INT2/T0IN P11/SI0/SB0 P70/INT0/T0LCP/AN8 P10/SO0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P87/AN7 9 P86/AN6 8 P85/AN5 7 P84/AN4 6 P83/AN3 5 P82/AN2 4 P81/AN1 3 P80/AN0 2 VDD1 1 P71/INT1/T0HCP/AN9 TQFP100 Top view No.7972-7/25 LC875BP4A/875BM2A/875BJ0A/875BH4A PAD Coordinate Values QIP NAME TQFP QIP NAME 1 PA3 98 51 SI2P2/SCK2 TQFP 48 2 PA4 99 52 SI2P3/SCK20 49 3 PA5 100 53 PWM1 50 4 P70/INT0/T0LCP/AN8 1 54 PWM0 51 5 P71/INT1/T0HCP/AN9 2 55 VDD2 52 6 P72/INT2/T0IN 3 56 VSS2 53 7 P73/INT3/T0IN 4 57 P00 54 8 RES 5 58 P01 55 9 XT1/AN10 6 59 P02 56 10 XT2/AN11 7 60 P03 57 11 VSS1 8 61 P04 58 12 CF1 9 62 P05/CKO 59 60 13 CF2 10 63 P06/T6O 14 VDD1 11 64 P07/T7O 61 15 P80/AN0 12 65 P20/INT4/T1IN 62 16 P81/AN1 13 66 P21/INT4/T1IN 63 17 P82/AN2 14 67 P22/INT4/T1IN 64 18 P83/AN3 15 68 P23/INT4/T1IN 65 19 P84/AN4 16 69 P24/INT5/T1IN 66 20 P85/AN5 17 70 P25/INT5/T1IN 67 21 P86/AN6 18 71 P26/INT5/T1IN 68 22 P87/AN7 19 72 P27/INT5/T1IN 69 23 P10/SO0 20 73 P30/PWM4 70 24 P11/SI0/SB0 21 74 P31/PWM5 71 25 P12/SCK0 22 75 P32/UTX1 72 26 P13/SO1 23 76 P33/URX1 73 27 P14/SI1/SB1 24 77 P34/UTX2 74 28 P15/SCK1 25 78 P35/URX2 75 29 P16/T1PWML 26 79 P36 76 30 P17/T1PWMH/BUZ 27 80 PB7 77 31 PE0 28 81 PB6 78 32 PE1 29 82 PB5 79 33 PE2 30 83 PB4 80 34 PE3 31 84 PB3 81 35 PE4 32 85 PB2 82 36 PE5 33 86 PB1 83 37 PE6 34 87 PB0 84 38 PE7 35 88 VSS3 85 39 VSS4 36 89 VDD3 86 40 VDD4 37 90 PC7 87 41 PF0 38 91 PC6 88 42 PF1 39 92 PC5 89 43 PF2 40 93 PC4 90 44 PF3 41 94 PC3 91 45 PF4 42 95 PC2 92 46 PF5 43 96 PC1 93 47 PF6 44 97 PC0 94 95 48 PF7 45 98 PA0 49 SI2P0/SO2 46 99 PA1 96 50 SI2P1/SI2/SB2 47 100 PA2 97 No.7972-8/25 LC875BP4A/875BM2A/875BJ0A/875BH4A System Block Diagram IR Interrupt Control PLA ROM Standby Control RC Xtal Clock Generator CF PC MRC SIO0 Bus Interface ACC SIO1 Port 0 B Register SIO2 Port 1 C Register Timer 0 Port 3 ALU Timer 1 Port 7 Timer 4 Port 8 Timer 5 ADC PSW RAR PWM0 PWM1 INT0-3 Noise Rejection Filter Port 2 RAM INT4, 5 Stack Pointer Base Timer Port A Watch Dog Timer Timer 6 Port B Timer 7 Port C UART1 Port E UART2 Port F PWM5 PWM4 No.7972-9/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Pin Description Name I/O Function description Option VSS1, VSS2 VSS3, VSS4 - Power supply pin (-) No VDD1, VDD2 VDD3, VDD4 - Power supply pin (+) No • 8-bit I/O port Yes Port 0 I/O • I/O specifiable in 4-bit units P00 to P07 • Pull-up resistor can be turned on and off in 4-bit units • HOLD release input • Port 0 interrupt input • Pin functions P05 : System clock output P06 : Timer 6 toggle output P07 : Timer 7 toggle output Port 1 I/O Yes • 8-bit I/O port • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistor can be turned on and off in 1-bit units • Pin functions P10: SIO0 data output P11 : SIO0 data input, bus I/O P12 : SIO0 clock I/O P13 : SIO1 data output P14 : SIO1 data input, bus I/O P15 : SIO1 clock I/O P16 : Timer 1 PWML output P17 : Timer 1 PWMH output/buzzer output Port 2 I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units P20 to P27 • Pull-up resistor can be turned on and off in 1-bit units • Other functions P20 to P23 : INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/timer 0H capture input P24 to P27 : NT5 input/HOLD release input/timer 1 event input/timer 0L capture input/timer 0H capture input • Interrupt detection style Port 3 P30 to P36 I/O Rising Falling INT4 enable enable INT5 enable enable Rising/ H level L level enable disable disable enable disable disable falling • 7-bit I/O port Yes • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Pin functions P30 : PWM4 output P31 : PWM5 output P32 : UART1 transmit P33 : UART1 receive P34 : UART2 transmit P35 : UART2 receive Continued on next page. No.7972-10/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Continued from preceding page. Name Port 7 I/O I/O Function description Option • 4-bit I/O port No • I/O specifiable in 1-bit units P70 to P73 • Pull-up resistor can be turned on and off in 1-bit units • Other functions P70 : INT0 input/HOLD release input/timer 0L capture input/output for watchdog timer P71 : INT1 input/HOLD release input/timer 0H capture input P72 : INT2 input/HOLD release input/timer 0 event input/timer 0L capture input P73 : INT3 input with noise filter/timer 0 event input/timer 0H capture input • Interrupt acknowledge type Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising/ H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable falling • AD converter input port : AN8 (P70), AN9 (P71) Port 8 I/O • 8-bit I/O port No • I/O specifiable in 1-bit units P80 to P87 • Other functions P80 to P87 : AD converter input port Port A I/O • 6-bit I/O port Yes • I/O specifiable in 1-bit units PA0 to PA5 • Pull-up resistor can be turned on and off in 1-bit units Port B I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units PB0 to PB7 • Pull-up resistor can be turned on and off in 1-bit units Port C I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units PC0 to PC7 • Pull-up resistor can be turned on and off in 1-bit units Port E I/O • 8-bit I/O port No • I/O specifiable in 2-bit units PE0 to PE7 • Pull-up resistor can be turned on and off in 1-bit units Port F I/O • 8-bit I/O port No • I/O specifiable in 2-bit units PF0 to PF7 • Pull-up resistor can be turned on and off in 1-bit units SIO2 Port I/O • 4-bit I/O port No • I/O specifiable in 1-bit units SI2P0 to SI2P3 • Other functions SI2P0 : SIO2 data output SI2P1 : SIO2 data input, bus input/output SI2P2 : SIO2 clock input/output SI2P3 : SIO2 clock output PWM0 O • PWM0 output port No • General-purpose I/O available PWM1 O • PWM1 output port No • General-purpose I/O available RES I Reset pin No XT1 I • Input terminal for 32.768kHz X'tal oscillation No • Other function AN10 : AD converter input port General input port XT2 I/O When not in use, connect terminal to VDD1. • Output terminal for 32.768kHz X'tal oscillation No • Other function AN11 : AD converter input port General input port When not in use, set as oscillation and leave terminal open CF1 I Input terminal for ceramic resonator No CF2 O Output terminal for ceramic resonator No No.7972-11/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Port Output Configuration Output configuration and pull-up resistor options are shown in the following table. Input is possible even when a port is in output mode. Terminal P00 to P07 P10 to P17 Option applies to : Option 1 bit 1 CMOS Programmable (Note 1) 2 Nch-open drain None 1 bit P20 to P27 Output format Pull-up resistor 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable CMOS Programmable P30 to P36 PA0 to PA5 1 bit PB0 to PB7 PC0 to PC7 PE0 to PE7 - None PF0 to PF7 P70 - None Nch-open drain Programmable P71 to P73 - None CMOS Programmable P80 to P87 - None Nch-open drain None SI2P0, SI2P2 - None CMOS None - None CMOS (when used as general port) None SI2P3 PWM0, PWM1 SI2P1 Nch-open drain (when used for SIO2 data) XT1 - None Input only None XT2 - None Output for 32.768kHz crystal oscillation None Nch-open drain (when in general-purpose output mode) Note 1 Programmable pull-up resistor of Port 0 is specified in nibble units (P00 to P03, P04 to P07). Note : To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, VSS3 and VSS4 should connect to each other and they should also be grounded. Example 1 : During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 No.7972-12/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Example 2 : During backup in hold mode, output is not held high and its value in unsettled. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 No.7972-13/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Absolute Maximum Ratings / Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Limits Parameter Symbol Pins Conditions VDD[V] Supply voltage VDD max VDD1, VDD2, VDD1=VDD2 VDD3, VDD4 =VDD3=VDD4 min typ max unit -0.3 +6.5 Input voltage VI (1) XT1, XT2, CF1 -0.3 VDD+0.3 Output voltage VO (1) PWM0, PWM1 -0.3 VDD+0.3 Input/output VIO (1) • Ports 0, 1, 2 voltage V • Ports 3, 7, 8 -0.3 • Ports A, B, C, E, F VDD+0.3 • SI2P00 to SI2P03 • PWM0, PWM1 High Peak level output IOPH (1) • Ports 0, 1, 2, 3 • CMOS output output • Ports A, B, C, E, F • For each pin. current • SI2P00 to SI2P03 current -10 • PWM0, PWM1 IOPH (2) P71 to P73 For each pin. -5 Total ΣIOAH (1) P71 to P73 Total of all pins -5 output ΣIOAH (2) • Port 1 Total of all pins current • PWM0, PWM1 -30 • Port 3 • SI2P00 to SI2P03 ΣIOAH (3) Ports 0, 2 Total of all pins -20 ΣIOAH (4) Port B Total of all pins -20 ΣIOAH (5) Ports A, C Total of all pins -20 IOPL (1) • P02 to P07 For each pin. Low Peak level output • Ports 1, 2, 3 output current • Ports A, B, C, E, F current 20 mA • SI2P00 to SI2P03 • PWM0, PWM1 IOPL (2) P00, P01 For each pin. IOPL (3) Ports 7, 8 For each pin. Total ΣIOAL (1) Port 7 Total of all pins 15 output ΣIOAL (2) Port 8 Total of all pins 15 current ΣIOAL (3) • PWM0, PWM1 Total of all pins 30 5 40 • Port 3 • SI2P00 to SI2P03 Maximum power ΣIOAL (4) Ports 0, 2, 3 Total of all pins 80 ΣIOAL (5) Port B Total of all pins 40 ΣIOAL (6) Ports A, C Total of all pins 40 ΣIOAL (7) Port F Total of all pins 40 ΣIOAL (8) Port 1, E Total of all pins Pd max QIP100E Ta= -30 to +70°C consumption Operating temperature TQFP100 Topr range Storage temperature range 70 519 Tstg mW 363 -30 70 -55 125 °C No.7972-14/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Recommended Operating Range / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Operating Symbol VDD (1) supply voltage Pins VDD1=VDD2 =VDD3=VDD4 range HOLD voltage Input high voltage VHD VIH (1) VDD1=VDD2 =VDD3=VDD4 • Ports 1, 2, 3 Conditions Limits VDD[V] min typ max unit 0.294µs ≤ tCYC ≤ 200µs 4.5 5.5 0.588µs ≤ tCYC ≤ 200µs 2.5 5.5 2.0 5.5 RAM and register data are kept in HOLD mode. 2.5 to 5.5 • SI2P00 to 03 0.3VDD • P71 to P73 VDD +0.7 • P70 port input /interrupt VIH (2) • Ports 0, 8 2.5 to 5.5 0.3VDD +0.7 VDD 0.9VDD VDD 0.75VDD VDD VSS 0.1VDD +0.4 VSS 0.15VDD +0.4 VSS 0.8VDD -1.0 VSS 0.25VDD • Ports A, B, C, E, F VIH (3) Port 70 watchdog timer 2.5 to 5.5 VIH (4) XT1, XT2, CF1, 2.5 to 5.5 RES Input low VIL (1) voltage • Ports 1, 2, 3 V 2.5 to 5.5 • SI2P00 to 03 • P71 to P73 • P70 port input /interrupt VIL (2) • Ports 0, 8 2.5 to 5.5 • Ports A, B, C, E, F VIL (5) Port 70 Watchdog timer 2.5 to 5.5 VIL (6) XT1, XT2, CF1, 2.5 to 5.5 RES Operation tCYC cycle time External system FEXCF (1) CF1 clock frequency • Leave CF2 pin open 4.5 to 5.5 0.294 200 2.5 to 5.5 0.588 200 0.1 10 0.1 5 0.2 20.4 0.1 10 µs 4.5 to 5.5 • System clock divider set to 1/1 • External clock DUTY=50±5% • Leave CF2 pin open 2.5 to 5.5 • System clock divider set to 1/1 • External clock DUTY=50±5% • Leave CF2 pin open 4.5 to 5.5 • System clock divider set to 1/2 • Leave CF2 pin open 2.5 to 5.5 • System clock divider set to 1/2 Oscillation FmCF (1) CF1, CF2 10MHz ceramic resonator frequency oscillation Range Refer to figure 1 (Note1) FmCF (2) CF1, CF2 5MHz ceramic resonator MHz 4.5 to 5.5 10 2.5 to 5.5 5 oscillation Refer to figure 1 FmRC RC oscillation 2.5 to 5.5 FmMRC Frequency variable RC 2.5 to 5.5 oscillation source oscillation FsX’tal XT1, XT2 32.768kHz crystal resonator oscillation Refer to figure 2 2.5 to 5.5 0.3 1.0 2.0 50 32.768 kHz Note 1 : The oscillation parameters are shown on Tables 1 and 2. No.7972-15/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Electrical Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Input high Symbol IIH (1) current Pins Conditions • Ports 0, 1, 2 • Output disable • Ports 3, 7, 8 • Pull-up resistor OFF • Ports A, B, C • VIN=VDD • SI2P00 to SI2P03 (including the off-leak current • RES of the output Tr.) Limits VDD[V] min typ max unit 2.5 to 5.5 1 • PWM0, PWM1 IIH (2) XT1, XT2 • Using as an input port 2.5 to 5.5 1 • VIN=VDD Input low IIH (3) CF1 VIN=VDD 2.5 to 5.5 IIL (1) • Ports 0, 1, 2 • Output disable 2.5 to 5.5 • Ports 3, 7, 8 • Pull-up resistor OFF • Ports A, B, C, E, F • VIN=VSS current • SI2P00 to SI2P03 (including the off-leak current • RES of the output Tr.) 15 µA -1 • PWM0, PWM1 IIL (2) XT1, XT2 • Using as an input port 2.5 to 5.5 -1 • VIN=VSS Output high voltage IIL (3) CF1 VIN=VSS 2.5 to 5.5 -15 VOH (1) • Ports 0, 1, 2, 3 IOH= -1.0mA 4.5 to 5.5 VDD-1 IOH= -0.1mA 2.5 to 5.5 VDD-0.5 VDD-1 VOH (2) voltage Pull-up resistor • SI2P00 to SI2P03 VOH (3) Port 71, 72, 73 IOH= -1.5mA 4.5 to 5.5 VOH (4) PWM0, PWM1 IOH= -6.0mA 4.5 to 5.5 VDD-1 VOH (5) P30, P31 IOH= -1.6mA 4.5 to 5.5 VDD-0.4 IOH= -1.0mA 2.5 to 5.5 VDD-0.4 VOH (6) Output low • Ports A, B, C, E, F VOL (1) VOL (2) (PWM4, 5 output mode) • Ports 0, 1, 2, 3 • Ports A, B, C, E, F • SI2P00 to SI2P03 V IOL=10mA 4.5 to 5.5 1.5 IOL=1.6mA 4.5 to 5.5 0.4 2.5 to 5.5 0.4 VOL (3) • PWM0, PWM1 IOL=1.0mA VOL (4) P00, P01 IOL=30mA 4.5 to 5.5 1.5 VOL (5) Ports 7, 8 IOL=1.0mA 2.5 to 5.5 0.4 • Ports 0, 1, 2, 3 VOH=0.9VDD 2.5 to 5.5 Rpu • Port 7 15 40 70 kΩ • Ports A, B, C, E, F Hysteresis VHIS voltage 2.5 to 5.5 • RES • Port 1 • Port 2 • Port 3 0.1VDD V 10 pF • Port 7 • SIP00 to SIP03 Pin capacitance CP All pins • All pins except the measured terminal : VIN=VSS • f=1MHz 2.5 to 5.5 • Ta=25°C No.7972-16/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Serial Input/Output Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Limits Input clock Parameter Symbol Pins Conditions VDD [V] typ Cycle tSCK (1) SCK0 (P12), Low level tSCKL (1) SI2P2 pulse width tSCKLA (1) 1 High level tSCKH (1) 1 pulse width tSCKHA (1) Cycle tSCK (2) Low level tSCKL (2) Refer to figure 6 2.5 to 5.5 SCK1 (P15) Refer to figure 6 2.5 to 5.5 tSCKH (2) 1 Cycle tSCK (3) SCK0 (P12), • CMOS output Low level tSCKL (3) SI2P2 • Refer to figure 6 pulse width tSCKLA (2) SI2P3 2.5 to 5.5 4/3 1/2 SCK0 (P12) 3/4 SIO0 SI2P2, SI2P3 1 Output clock SIO2 tSCKH (3) pulse width tSCKHA (2) tSCK 1/2 SCK0 (P12) 2 SIO0 SI2P2, SI2P3 7/4 SIO2 Cycle Low level tSCK (4) SCK1 (P15) • CMOS output 2.5 to 5.5 2 tSCKL (4) 1/2 tSCK tSCKH (4) 1/2 pulse width Data set-up time Data hold time tsDI thDI tCYC • Refer to figure 6 pulse width High level tCYC 2 1 pulse width High level unit 4(SIO0) 5(SIO2) High level Serial input max 2 1 pulse width Serial clock min SB0 (P11), • Data set-up to SI0CLK SB1 (P14), • Data hold from SI0CLK SI2P1 • Refer to figure 6 2.5 to 5.5 0.03 SI0 0.03 SI1 Serial output Output delay time tdD0 SO0 (P10), • Data hold from SI0CLK SO1 (P13), • Time delay from SI0CLK SB0 (O11), trailing edge to the SO SB1 (P14), data change in the open SI2P0, drain SI2P1 µs 2.5 to 5.5 1/3tCYC +0.05 • Refer to figure 6 No.7972-17/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Pulse Input Conditions / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins Conditions High/low level tPIH (1) INT0 (P70), • Interrupt acceptable pulse width tPIL (1) INT1 (P71), • Timer 0 and 1 event INT2 (P72) Limits VDD [V] min typ max unit 2.5 to 5.5 input acceptable 1 INT4 (P20 to P23) INT5 (P24 to P27) tPIH (2) INT3 (P73) • Interrupt acceptable tPIL (2) (The noise rejection clock • Timer 0 event input is selected to 1/1.) 2 tCYC acceptable tPIH (3) INT3 (P73) • Interrupt acceptable tPIL (3) (The noise rejection clock • Timer 0 event input is selected to 1/32.) INT3 (P73) • Interrupt acceptable tPIL (4) (The noise rejection clock • Timer 0 event input is selected to 1/128.) RES 2.5 to 5.5 64 acceptable tPIH (4) tPIL (5) 2.5 to 5.5 2.5 to 5.5 256 acceptable Reset acceptable 2.5 to 5.5 µs 200 AD Converter Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins Resolution N AN0 (P80) Absolute precision ET to AN7 (P87) Conversion time TCAD AN8 (P70) AN9 (P71) AN10 (XT1) Limits Conditions VDD [V] 3.0 to 5.5 (Note 2) 4.5 to 5.5 (Note 3) AN11 (XT2) 3.0 to 5.5 AD conversion time=64 × tCYC (ADCR2=1) 4.5 to 5.5 (Note 3) 3.0 to 5.5 Analog input VAIN typ 3.0 to 5.5 voltage range Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 max unit 8 3.0 to 5.5 AD conversion time=32 × tCYC (ADCR2=0) min bit ±1.5 15.10 97.92 (tCYC= (tCYC= 0.588µs) 3.06µs) 31.36 97.92 (tCYC= (tCYC= 0.980µs) 3.06µs) 18.82 97.92 (tCYC= (tCYC= 0.294µs) 1.53µs) 62.72 97.92 (tCYC= (tCYC= 0.980µs) 1.53µs) VSS VDD 1 -1 LSB µs V µA Note 2 : Absolute precision excludes the quantizing error (±1/2 LSB). Note 3 : The conversion time is the time from executing the AD conversion instruction to setting the complete digital conversion value in the register. No.7972-18/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Current Dissipation Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins IDDOP (1) VDD1 • FmCF=10MHz by ceramic resonator during basic =VDD2 • FmX’tal=32.768kHz by crystal oscillation operation =VDD3 • System clock : CF oscillation (10MHz) (Note 4) =VDD4 • Internal RC oscillation stops Current drain Conditions Limits VDD [V] min typ max unit 4.5 to 5.5 10 15 10.5 16 5.5 8 3 6 0.7 4 0.3 1.5 2 6 0.7 3.5 27 60 • Frequency variable RC oscillation stops • 1/1 divided IDDOP (2) • CF1=20MHz by external clock 2.5 to 5.5 • FmX’tal=32.768kHz by crystal oscillation • System clock : CF1 oscillation (20MHz) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/2 divided IDDOP (3) • FmCF=5MHz by ceramic resonator 4.5 to 5.5 • FmX'tal=32.768kHz by crystal oscillation • System clock : CF oscillation (5MHz) IDDOP (4) • Internal RC oscillation stops mA 2.5 to 4.5 • Frequency variable RC oscillation stops • 1/1 divided IDDOP (5) • FmCF=0Hz 4.5 to 5.5 (when oscillation stops) • FmX'tal=32.768kHz by crystal oscillation IDDOP (6) • System clock : RC oscillation 2.5 to 4.5 • Frequency variable RC oscillation stops • 1/2 divided IDDOP (7) • FmCF=0Hz 4.5 to 5.5 (when oscillation stops) • FmX'al=32.768kHz by crystal oscillation IDDOP (8) • System clock : 1MHz with frequency variable RC oscilatin 2.5 to 5.5 • Internal RC oscillation stops • 1/2 divided IDDOP (9) • FmCF=0Hz 4.5 to 5.5 (when oscillation stops) • FmX'al=32.768kHz by crystal oscillation IDDOP (10) • System clock : X'tal oscillation (32.768kHz) • Internal RC oscillation stops µA 2.5 to 4.5 • Frequency variable RC oscillation stops 12 40 • 1/2 divided Note 4 : The current of the output transistors and pull-up MOS transistors are excluded. Continued on next page. No.7972-19/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Continued from preceding page. Parameter Symbol Pins Conditions VDD1 • HALT mode HALT mode =VDD2 • FmCF=10MHz by ceramic resonator (Note 4) =VDD3 • FmX’tal=32.768kHz by crystal oscillation =VDD4 • System clock : CF oscillation (10MHz) Current drain in IDDHALT (1) Limits VDD [V] min typ max unit 4.5 to 5.5 2.5 5 3.2 6 1.5 3 • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/1 divided IDDHALT (2) • HALT mode 4.5 to 5.5 • CF1=20MHz by external clock • FmX’tal=32.768kHz by crystal oscillation • System clock : CF1 oscillation (20MHz) • Internal RC oscillation stops • Frequency variable RC oscillation stops • 1/2 divided • HALT mode IDDHALT (3) 4.5 to 6.0 • FmCF=5MHz by ceramic resonator • FmX’tal=32.768kHz by crystal oscillation • System clock : CF oscillation (5MHz) IDDHALT (4) • Internal RC oscillation stops mA 2.5 to 4.5 0.7 1.5 0.3 1 0.15 0.5 1.6 2.5 0.6 1.8 16 40 5 25 4.5 to 5.5 0.015 10 2.5 to 4.5 0.001 5 14 35 3.8 20 • Frequency variable RC oscillation stops • 1/1 divided IDDHALT (5) • HALT mode 4.5 to 5.5 • FmCF=0Hz (when oscillation stops) • FmX’tal=32.768kHz by crystal oscillation IDDHALT (6) • System clock : RC oscillation 2.5 to 4.5 • Frequency variable RC oscillation stops • 1/2 divided IDDHALT (7) • HALT mode 4.5 to 5.5 • FmCF=0Hz (when oscillation stops) • FmX'tal=32.768kHz by crystal oscillation • System clock : 1MHz with frequency IDDHALT (8) 2.5 to 4.5 variable RC oscilatin • Internal RC oscillation stops • 1/2 divided • HALT mode IDDHALT (9) 4.5 to 5.5 • FmCF=0Hz (when oscillation stops) • FmX'tal=32.768kHz by crystal oscillation • System clock : X'tal oscillation (32.768kHz) IDDHALT (10) 2.5 to 4.5 • Internal RC oscillation stops • Frequency variable RC oscillation stops µA • 1/2 divided Current drain IDDHOLD (1) VDD1 during HOLD mode Current drain (when using external clock) VDD1 • Time-base clock HOLD mode 4.5 to 5.5 • CF1=VDD or leave it open during time-base clock HOLD mode • CF1=VDD or leave it open IDDHOLD (2) IDDHOLD (3) • HOLD mode IDDHOLD (4) (when using external clock) 2.5 to 4.5 • FmX'tal=32.768kHz by crystal oscillation Note 4 : The current of the output transistors and pull-up MOS transistors are excluded. No.7972-20/25 LC875BP4A/875BM2A/875BJ0A/875BH4A UART (full duplex) Operating Conditions / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins Limits Conditions VDD [V] Clock rate UBR, UBR2 UTX1 (P32), min typ max unit 2.5 to 5.5 RTX1 (P33), 16/3 UTX2 (P33), 8192/3 tCYC RTX2 (P34) Data length : Stop bits : Parity bits : 7, 8 and 9 bits (LSB first) 1-bit Non Continuous 8-bit data transmit mode (first transmit data = 55H) Start bit Beginning of transmission Stop bit End of transmittion Transmit data (LSB first) UBR, UBR2 Continuous 8-bit data receive mode (first transmit data = 55H) Stop bit Start bit Beginning of reception Received data (LSB first) End of reception UBR, UBR2 No.7972-21/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Main System Clock Oscillation Circuit Characteristics The characteristics in the table bellow is based on the following conditions : 1. Using the standard oscillation evaluation board SANYO has provided. 2. Using the external peripheral parts with the indicated value. 3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. Table 1. Recommended circuit parameters for the main system clock using the ceramic resonator Recommended circuit Frequency 10MHz 5MHz Manufacturer CSLS10M0G53-R0 MURATA MURATA Oscillation stabilizing Operating supply parameters Oscillator time voltage range typ Note C1 C2 Rd1 max (10pF) (10pF) 150Ω 4.5 to 5.5V Internal C1,C2 CSTLS10M0G52-B0 (10pF) (10pF) 100Ω 4.5 to 5.5V Internal C1,C2 CSTLS5M00G53-R0 (15pF) (15pF) 470Ω 2.5 to 5.5V Internal C1,C2 CSTLS5M00G53-B0 (15pF) (15pF) 470Ω 2.5 to 5.5V Internal C1,C2 *The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure 4) Subsystem Clock Oscillation Circuit Characteristics The characteristics in the table bellow is based on the following conditions : 1. Using the standard oscillation evaluation board SANYO has provided. 2. Using the external peripheral parts with the indicated value. 3. The recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. Table 2. Recommended circuit parameters for the subsystem clock using the crystal oscillation Recommended circuit Frequency 32.768kHz Manufacturer SEIKO EPSON MC-306 C3 C4 Rf Rd2 15pF 15pF OPEN 390kΩ Oscillation Operating supply Parameters Oscillator stabilizing time voltage range typ Note max 2.5 to 5.5V *The oscillation stabilizing time is the period until the oscillation becomes stable, after executing the instruction which starts the sub-clock oscillator or after releasing a HOLD mode. (Refer to Figure 4) Notes : Since the oscillation frequency precision is affected by the circuit pattern, place the oscillation related parts as close to the oscillation pins as possible, using the shortest possible pattern length. CF1 XT1 CF2 Rd1 XT2 Rf Rd2 C1 CF C2 C3 C4 X’tal Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit 0.5VDD Figure 3 AC timing point No.7972-22/25 LC875BP4A/875BM2A/875BJ0A/875BH4A VDD Power Supply VDD limit GND Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsXtal XT1, XT2 Operation mode Unfixed Reset Instruction execution Reset time and oscillation stabilizing time HOLD release signal HOLD release signal VALID Internal RC oscillation tmsCF CF1, CF2 tmsXtal XT1, XT2 Operation mode HOLD HALT HOLD release signal and oscillation stabilizing time Figure 4 Oscillation stabilizing time No.7972-23/25 LC875BP4A/875BM2A/875BJ0A/875BH4A VDD RRES (Note) Select CRES and RRES value to assure that at least 200µs reset time is generated after the VDD becomes higher than the minimum operating voltage. RES CRES Figure 5 Reset circuit SI0CLK : DATAIN : DI0 DI1 DI2 DI3 DI4 DI5 DI6 DATAOUT : DO0 DO1 DO2 DO3 DO4 DO5 DO6 DI7 DI8 DO7 DO8 Data RAM transmission period (only SIO0, 2) tSCK tSCKH tSCKL SI0CLK : tsDI thDI DATAIN : tdDO DATAOUT : Data RAM transmission period (only SIO0, 2) tSCKLA tSCKHA SI0CLK : tsDI thDI DATAIN : tdDO DATAOUT : Figure 6 Serial input/output test condition tPIL tPIH Figure 7 Pulse input timing condition No.7972-24/25 LC875BP4A/875BM2A/875BJ0A/875BH4A Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 2005. Specifications and information herein are subject to change without notice. PS No.7972-25/25