www.fairchildsemi.com FSDM1265RB Green Mode Fairchild Power Switch (FPSTM) Features • Internal Avalanche Rugged Sense FET • Advanced Burst-Mode operation that consumes less than 1 W at 240VAC and 0.5W load • Precision Fixed Operating Frequency (66kHz) • Internal Start-up Circuit • Improved Pulse by Pulse Current Limiting • Over-Voltage Protection (OVP) • Over-Load Protection (OLP) • Internal Thermal Shutdown Function (TSD) • Auto-Restart Mode • Under Voltage Lock Out (UVLO) with Hysteresis • Low Operating Current (2.5mA) • Built-in Soft Start Application • SMPS (Switch Mode Power Supplies) for LCD monitor and STB • Adapter Description The FSDM1265RB is an integrated Pulse-Width Modulator (PWM) and a SenseFET which is specifically designed for high performance offline SMPS with minimal external components. This device is an integrated high-voltage power switching regulator which combines a rugged avalanche Sense FET with a current mode PWM control block. The PWM controller includes integrated fixed frequency oscillator, under-voltage lockout, leading edge blanking (LEB), optimized gate driver, internal soft-start, and precise current sources that are temperature compensated for loop compensation and self protection circuitry. Compared with discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size, and weight, while simultaneously increasing efficiency, productivity, and system reliability. This device is a basic platform which is well suited for cost effective designs of flyback converters. OUTPUT POWER TABLE(4) 230VAC ±15%(3) PRODUCT Adapter(1) Open Frame(2) 85-265VAC Adapter(1) Open Frame(2) FSDM0565RB 60W 70W 50W 60W FSDM0565RBI 60W 70W 50W 60W FSDM07652RB 70W 80W 60W 70W FSDM1265RB 90W 110W 80W 90W Table 1. Maximum Output Power Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2. Maximum practical continuous power in an open- frame design at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. 4. The junction Temperature can limit the Maximum output power. Typical Circuit AC IN DC OUT Vstr Drain PWM Vfb Vcc Source Figure 1. Typical Flyback Application FPSTM is a trademark of Fairchild Semiconductor Corporation. ©2005 Fairchild Semiconductor Corporation Rev.1.0.0 FSDM1265RB Internal Block Diagram Vcc Vstr 6 3 N.C 5 Drain 1 Istart 0.38/ 0.49V + Vref 8V/12V Vcc Vcc good Internal Bias Vref OSC Idelay IFB 2.5R PWM S Q R Q FB 4 Soft start R Gate driver LEB VSD 2 GND Vcc S Q R Q Vovp TSD Vcc good Figure 2. Functional Block Diagram of FSDM1265RB 2 VCL FSDM1265RB Pin Definitions Pin Number Pin Name Pin Function Description 1 Drain This pin is the high voltage power Sense FET drain. It is designed to drive the transformer directly. 2 GND This pin is the control ground and the Sense FET source. Vcc This pin is the positive supply voltage input. During startup, the power is supplied by an internal high voltage current source that is connected to the Vstr pin. When Vcc reaches 12V, the internal high voltage current source is disabled and the power is supplied from the auxiliary transformer winding. 4 Vfb This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. Once the pin reaches 6.0V, the overload protection is activated resulting in the shutdown of the FPSTM. 5 N.C 3 6 Vstr This pin is connected directly to the high voltage DC link. At startup, the internal high voltage current source supplies internal bias and charges the external capacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal current source is disabled. Pin Configuration TO-220F-6L 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain Figure 3. Pin Configuration (Top View) 3 FSDM1265RB Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Parameter Drain-source Voltage Vstr Max. Voltage Pulsed Drain Current (Tc=25°C) (1) Continuous Drain Current(Tc=25°C) Symbol Value Unit VDSS 650 V VSTR 650 V IDM 15.9 ADC 5.3 A 3.4 A ID Continuous Drain Current(Tc=100°C) Supply Voltage VCC 20 V Input Voltage Range VFB -0.3 to VCC V Total Power Dissipation (Tc=25°C with Infinite Heat Sink) PD 50 W Operating Junction Temperature Tj Internally limited °C Operating Ambient Temperature TA -25 to +85 °C TSTG -55 to +150 °C ESD Capability, HBM Model (All Pins except for Vstr and Vfb) - 2.0 (GND-Vstr/Vfb=1.5kV) kV ESD Capability, Machine Model (All Pins except for Vstr and Vfb) - 300 (GND-Vstr/Vfb=225V) V Storage Temperature Range Notes: 1. Repetitive rating: Pulse width limited by maximum junction temperature Thermal Impedance Parameter Junction-to-Case Thermal Symbol Package Value Unit θJC(1) TO-220F-6L 2.5 °C/W Notes: 1. Infinite cooling condition - Refer to the SEMI G30-88. 4 FSDM1265RB Electrical Characteristics (Ta = 25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit BVDSS VGS = 0V, ID = 250µA 650 - - V VDS = 650V, VGS = 0V - - 500 µA IDSS VDS= 520V VGS = 0V, TC = 125°C - - 500 µA RDS(ON) VGS = 10V, ID = 2.5A - 0.75 0.9 Ω Output capacitance COSS VGS = 0V, VDS = 25V, f = 1MHz - 78 - pF Turn-on delay time TD(ON) - 42 - - 106 - TD(OFF) - 330 - TF - 110 - VFB = 3V 60 66 72 kHz 13V ≤ Vcc ≤ 18V 0 1 3 % -25°C ≤ Ta ≤ 85°C 0 ±5 ±10 % Sense FET SECTION Drain-source breakdown voltage Zero gate voltage drain current Static drain source on resistance Rise time Turn-off delay time Fall time TR VDD= 325V, ID= 5A ns CONTROL SECTION Initial frequency FOSC Voltage stability FSTABLE Temperature stability (1) ∆FOSC Maximum duty cycle DMAX - 77 82 87 % Minimum duty cycle DMIN - - - 0 % Start threshold voltage VSTART VFB=GND 11 12 13 V Stop threshold voltage VSTOP VFB=GND 7 8 9 V Feedback source current IFB VFB=GND 0.7 0.9 1.1 mA Soft-start time TS Vfb=3 - 10 15 ms - 250 - ns Leading edge blanking time - TLEB BURST MODE SECTION Burst mode voltages(1) VBURH Vcc=14V 0.3 0.38 0.46 V VBURL Vcc=14V 0.39 0.49 0.59 V 5 FSDM1265RB Electrical Characteristics (Continued) (Ta = 25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit 3.0 3.4 3.8 A 18 19 20 V 130 145 160 °C VFB ≥ 5.5V 5.5 6.0 6.5 V VFB=5V 2.8 3.5 4.2 µA - 2.5 5 mA PROTECTION SECTION Peak current limit (2) IOVER Over voltage protection (OVP) VOVP Thermal shutdown temperature (1) TSD Shutdown feedback voltage VSD Shutdown delay current IDELAY VFB=5V, VCC=14V - TOTAL DEVICE SECTION Operating supply current (3) IOP VFB=GND, VCC=14V IOP(MIN) VFB=GND, VCC=10V IOP(MAX) VFB=GND, VCC=18V Notes: 1. These parameters, although guaranteed at the design level, are not tested in mass production. 2. These parameters indicate the inductor current. 3. This parameter is the current flowing into the control IC. 6 FSDM1265RB Comparison of FS6M12653RTC and FSDM1265RB Function FS6M12653RTC Soft-Start Adjustable soft-start time using an external capacitor Burst Mode Operation FSDM1265RB FSDM1265RB Advantages Typical Internal soft- • Gradually increasing current limit start of 10ms (fixed) during soft-start reduces peak current and voltage component stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot • Built into controller • Built into controller • Improves ight-load efficiency • Output voltage fixed • Reduces no-load consumption • Output voltage drops to about half 7 FSDM1265RB Typical Performance Characteristics 1.2 1.2 1.0 1.0 Operating Frequency (Normalized to 25℃) Operating Current (Normalized to 25℃) (These Characteristic Graphs are Normalized at Ta= 25°C) 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0.0 0.0 -50 -25 0 25 50 75 100 -50 125 1.2 1.2 1.0 1.0 0.8 0.6 0.4 0.2 0.0 25 50 75 100 125 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 125 -50 Ju nc tion Te mperatu re (℃) -25 0 25 50 75 100 125 Junction Temperature(℃) Start Threshold Voltage vs. Temperature Stop Threshold Voltage vs. Temperature 1.2 1.2 1.0 1.0 FB Source Current (Normalized to 25℃) Maximum Duty Cycle (Normalized to 25℃) 0 Operating Freqency vs. Temperature Stop Threshold Voltage (Normalized to 25℃) Start Thershold Voltage (Normalized to 25℃) Operating Current vs. Temperature 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0.0 0.0 -50 -25 0 25 50 75 100 Junction Temperature(℃) Maximum Duty vs. Temperature 8 -25 Ju n ction Temperatu re(℃) Junc tion Temperature(℃) 125 -50 -25 0 25 50 75 100 125 Ju n c tio n T e mp e ra tu re (℃) Feedback Source Current vs. Temperature FSDM1265RB Typical Performance Characteristics (Continued) 1.2 1.2 1.0 1.0 Shutdown Delay Current (Normalized to 25℃) Shutdown FB Voltage (Normalized to 25℃) (These Characteristic Graphs are Normalized at Ta= 25°C) 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0.0 0.0 -50 -25 0 25 50 75 100 -50 125 -25 1.2 1.2 1.0 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 50 75 100 125 100 0.8 0.6 0.4 0.2 0.0 125 -50 -25 0 Ju n c tion Te mpe ra tu re (℃) 25 50 75 100 125 100 125 Ju n c tion T e mpe ra tu re (℃) Current Limit VS. Temperature Over Voltage Protection vs. Temperature 1.2 1.2 1.0 1.0 Burst Mode Disable Voltage (Normalized to 25℃) Current Limit (Normalized to 25℃) 25 ShutDown Delay Current vs. Temperature Burst Mode Enable Voltage (Normalized to 25℃) Over Voltage Protection (Normalized to 25℃) ShutDown Feedback Voltage vs. Temperature -50 0 Ju n c tion Te mpe ratu re (℃) Ju n c tion T e mpe ra tu re (℃) 0.8 0.6 0.4 0.2 0.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 Ju nc tion Te mpe ratu re (℃) Burst Mode Enable Voltage vs. Temperature 125 -50 -25 0 25 50 75 Ju n c tion T e mpe ratu re (℃) Burst Mode Disable Voltage vs. Temperature 9 FSDM1265RB Typical Performance Characteristics (Continued) (These Characteristic Graphs are Normalized at Ta= 25°C) 1.2 Soft Start Time (Normalized to 25℃) 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 Ju nc tion Te mpe ratu re (℃) Soft-start Time vs. Temperature 10 100 125 FSDM1265RB Functional Description 1. Star-tup: In previous generations of Fairchild Power Switches (FPSTM), the Vcc pin had an external start-up to the DC input voltage line. In the newer switches, the startup resistor is replaced by an internal high voltage current source. At startup, an internal high voltage current source supplies the internal bias and charges the external capacitor (Cvcc) that is connected to the Vcc pin as illustrated in Figure 4. When the Vcc pin reaches 12V, the FSDM1265RB begins switching and the internal high voltage current source is disabled. Then, the FSDM1265RB continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless Vcc goes below the stop voltage of 8V. VDC CVcc Vcc 3 6 2.1 Pulse-by-pulse current limit: Because current mode control is employed, the peak current through the Sense-FET is limited by the inverting input of PWM comparator (Vfb*) as shown in Figure 5. Assuming that the 0.9mA current source flows only through the internal resistor (2.5R +R= 2.8 kΩ), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (Vfb) exceeds 2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping Vfb*. Therefore, the peak value of the current through the Sense FET is limited. 2.2 Leading edge blanking (LEB): When the internal Sense FET is turned on, usually the reverse recovery of the primary-side capacitance and the secondary-side rectifier causes a high current spike through the SenseFET. causes Excessive voltage across the Rsense resistor can lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FSDM1265RB employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the SenseFET is turned on. Vstr Vcc Istart Vref 8V/12V Vref Idelay Vcc good 4 H11A817A D2 2.5R + Vfb* KA431 Gate driver R - VSD Figure 4. Internal startup circuit SenseFET OSC D1 CB Internal Bias IFB Vfb Vo OLP Rsense Figure 5. Pulse width modulation (PWM) circuit 2. Feedback Control: FSDM1265RB employs current mode control, as shown in Figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor in addition to the offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thereby pulling down the feedback voltage and reducing the duty cycle. Typically this happens when the input voltage is increased or the output load is decreased. 3. Protection Circuit: The FSDM1265RB has several self protective functions such as overload protection (OLP), over voltage protection (OVP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC without external components, the reliability can be improved without increasing cost. Once the fault condition occurs, switching is terminated and the SenseFET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage (8V), the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When the Vcc reaches the UVLO start voltage (12 V), the FSDM1265RB resumes its normal operation. Thus, the auto-restart alternately enables and disables the switching of the power SenseFET until the fault condition is eliminated (see Figure 6). 11 FSDM1265RB Vds Power on Fault occurs VFB Fault removed Over load protection 6.0V 2.5V Vcc T 12= Cfb*(6.0-2.5)/Idelay T1 12V T2 t Figure 7. Over Load Protection 8V t Normal operation Fault situation Normal operation Figure 6. Auto Restart Operation 3.1 Over Load Protection (OLP): Overload occurs when the load current exceeds a pre-set level due to an unexpected event. The protection circuit (OLP) is activated to protect the SMPS. However, even when the SMPS is operating normally, the OLP circuit can become activate during the load transition. To avoid this undesired operation, the OLP circuit is designed to become activate after a specified time to determine whether it is in a transient or an overload mode. Because of the pulse-by-pulse current limit capability, the maximum peak current through the SenseFET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked and the 3.5uA current source slowly starts to charge CB up to Vcc. In this condition, Vfb continues increasing until it reaches 6V. Then the switching operation terminates as shown in Figure 7. The delay time for shutdown is the time required to charge CB from 2.5V to 6.0V with 3.5uA. In general, a 10 ~ 50 ms delay is typical for most applications. 3.2 Over voltage Protection (OVP): If the secondary side feedback circuit malfunctions or a solder defect causes an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, Vfb climbs up in a similar manner to the over load situation forcing the pre-set maximum current to be supplied to the SMPS until the OLP is activated. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the OLP is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an OVP circuit is used. Generally, Vcc is proportional to the output voltage and the FSDM1265RB uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, an OVP circuit is activated resulting in the termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be designed to be below 19V. 3.3 Thermal Shutdown (TSD): The SenseFET and the control IC are built in one package making it easy for the control IC to detect the heat generated by the SenseFET. When the temperature exceeds approximately 150°C, the thermal shutdown is activated. 4. Soft Start: The FSDM1265RB has an internal soft-start circuit, which increases the PWM comparator and slowly inverts the input voltage together with the SenseFET current, after it starts up. The typical soft-start time is 10ms, The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased to smoothly establish the required output voltage. This also helps prevent transformer saturation and reduce the stress on the secondary diode during startup. 5. Burst operation: To minimize power dissipation in the standby mode, the FSDM1265RB enters burst mode operation. As the load decreases, the feedback voltage decreases. As shown 12 FSDM1265RB in Figure 8, the device automatically enters burst mode when the feedback voltage drops below VBURL(380mV). At this point switching stops and the output voltages start to drop at a rate dependent on the standby current load. This causes the feedback voltage to rise. Once it passes VBURH(490mV), switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power SenseFET, thereby reducing switching loss in the Standby mode. Vo Vose t VFB 0.49V 0.38V Ids Vds time T 1 Switching disabled T 2 T 3 Switching disabled T 4 Figure 8. Waveforms of BurstOperation 13 FSDM1265RB Typical Application Circuit Application Output Power LCD Monitor 62W Input Voltage Output Voltage (Max. Current) Universal input 5V (4.0A) (85-265Vac) 12V (3.5A) Features • • • • • • High efficiency (>81% at 85Vac input) Low zero-load power consumption (<300mW at 240Vac input) Low standby-mode power consumption (<800mW at 240Vac input and 0.3W load) Low component count Enhanced system reliability through several protection functions Internal soft-start (10ms) Key Design Notes • Resistors R102 and R105 are employed to prevent start-up at low input voltage. After start-up, there is no power loss in these resistors since the start-up pin is internally disconnected after start-up. • The delay time for OLP is designed to be about 50ms with C106 of 47nF. If you require a faster triggering of OLP , reduce the C106 to 10nF. • Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zener diode fails and remains short, which causes the fuse (F1) to blow and prevents explosion of the opto-coupler (IC301). The zener diode also increases immunity against a line surge. 1. Schematic D202 T1 EER3016 MBRF10100 10 1 C103 200uF 400V R105 40kΩ Ω BD101 2 2KBP06M3N257 1 R102 30kΩ Ω 3 R103 56kΩ Ω 2W C104 2.2nF 1kV 8 3 IC1 FSDM1265R B 6 Vstr 1 Drain 5 D201 MBRF1045 NC 4 C102 220nF 275VA C ZD102 10V C106 47nF 50V 12V, 3.5A C202 1000u F 25V C201 1000uF 25V 2 D101 UF 4007 L20 1 4 Vf b GND 2 Vcc 3 ZD101 22V C105 D102 47uF TVR10G 50V R104 5Ω Ω 4 L20 2 5V, 4A 7 C204 1000u F 10V C203 1000uF 10V 6 5 C301 4.7nF LF101 23mH R201 1kΩ Ω R101 560kΩ Ω 1W RT1 5D-9 14 C101 220nF 275VA C R202 1.2kΩ Ω F1 FUSE 250V 2A IC301 H11A817A IC201 KA431 R204 10kΩ Ω R203 12kΩ Ω C205 47nF R205 10kΩ Ω FSDM1265RB 2. Transformer Schematic Diagram EER3016 Np/2 Np/2 1 10 2 9 3 8 4 7 N 5V Na 5 N12V 6 3.Winding Specification No Na Pin (s→f) Wire Turns Winding Method 4→5 φ 8 Center Winding 18 Solenoid Winding 7 Center Winding 3 Center Winding 18 Solenoid Winding 0.2 × 1 Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 2→1 0.4φ × 1 Insulation: Polyester Tape t = 0.050mm, 2Layers N12V 10 → 8 0.3φ × 3 Insulation: Polyester Tape t = 0.050mm, 2Layers N5V 7→6 0.3φ × 3 Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 3→2 0.4φ × 1 Outer Insulation: Polyester Tape t = 0.050mm, 2Layers 4.Electrical Characteristics Pin Specifications Remarks Inductance 1-3 420uH ± 10% 100kHz, 1V Leakage Inductance 1-3 10uH Max. 2nd all short 5. Core & Bobbin Core: EER 3016 Bobbin: EER3016 Ae(mm2): 96 15 FSDM1265RB 6.Demo Circuit Part List Part Value Note Fuse F101 2A/250V RT101 5D-9 Part Value Note C301 4.7nF Polyester Film Cap. L201 5uH Wire 1.2mm L202 5uH Wire 1.2mm NTC Inductor Resistor R101 560K 1W R102 30K 1/4W R103 56K 2W R104 5 1/4W R105 40K 1/4W D101 UF4007 R201 1K 1/4W D102 TVR10G R202 1.2K 1/4W D201 MBRF1045 Diode R203 12K 1/4W D202 MBRF10100 R204 10K 1/4W ZD101 Zener Diode 22V R205 10K 1/4W ZD102 Zener Diode 10V Bridge Diode BD101 2KBP06M 3N257 Bridge Diode Capacitor 16 C101 220nF/275VAC Box Capacitor Line Filter C102 220nF/275VAC Box Capacitor C103 200uF/400V Electrolytic Capacitor C104 2.2nF/1kV Ceramic Capacitor IC101 FSDM1265RB FPSTM(12A,650V) C105 47uF/50V Electrolytic Capacitor IC201 KA431(TL431) Voltage reference C106 47nF/50V Ceramic Capacitor IC301 H11A817A Opto-coupler C201 1000uF/25V Electrolytic Capacitor C202 1000uF/25V Electrolytic Capacitor C203 1000uF/10V Electrolytic Capacitor C204 1000uF/10V Electrolytic Capacitor C205 47nF/50V Ceramic Capacitor LF101 23mH Wire 0.4mm IC FSDM1265RB 7. Layout Figure 9. Layout Considerations for FSDM1265RB Figure 10. Layout Considerations for FSDM1265RB 17 FSDM1265RB Package Dimensions TO-220F-6L(Forming) 18 FSDM1265RB Ordering Information Product Number Package Marking Code BVdss Rds(on)Max FSDM1265RBWDTU TO-220F-6L(Forming) DM1265RB 650V 0.9 Ω WDTu: Forming Type 19 FSDM1265RB DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 7/27/05 0.0m 001 2005 Fairchild Semiconductor Corporation