www.fairchildsemi.com FSCQ1565RP Green Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Switching Converter Features • Optimized for Quasi-Resonant Converter (QRC) • Advanced Burst-Mode operation for under 1 W standby power consumption • Pulse by Pulse Current Limit (11.5A) • Over load protection (OLP) - Auto restart • Over voltage protection (OVP) - Auto restart • Abnormal Over Current Protection (AOCP) - Latch • Internal Thermal Shutdown (TSD) - Latch • Under Voltage Lock Out (UVLO) with hysteresis • Low Startup Current (typical : 25uA) • Low Operating Current (typical : 7mA) • Internal High Voltage SenseFET • Built-in Soft Start (20ms) • Extended Quasi-resonant Switching for Wide Load Range Application OUTPUT POWER TABLE 230VAC ±15%(2) PRODUCT Open Frame(1) 85-265VAC Open Frame(1) FSCQ0765RT 100 W 85 W FSCQ1265RT 170 W 140 W FSCQ1565RT 210 W 170 W FSCQ1565RP 250 W 210 W Table 1. Notes: 1. Maximum practical continuous power in an open frame design at 50°C ambient. 2. 230 VAC or 100/115 VAC with doubler. Typical Circuit • CTV • DVD Receiver • Audio Power Supply Description In general, Quasi-Resonant Converter (QRC) shows lower EMI and higher power conversion efficiency compared to the conventional hard switched converter with a fixed switching frequency. Therefore, it is well suited for applications that are sensitive to the noise, such as color TV and audio. The FSCQ1565RP is an integrated Pulse Width Modulation (PWM) controller and Sense FET specifically designed for Quasi-resonant off-line Switch Mode Power Supplies (SMPS) with minimal external components. The PWM controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (LEB), optimized gate driver, internal soft start, temperature compensated precise current sources for a loop compensation and self protection circuitry. Compared with discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. This device is a basic platform well suited for cost effective designs of Quasi resonant switching flyback converters. Vo AC IN Drain FSCQ1565RP PWM Sync GND VFB Vcc Figure 1. Typical Flyback Application Rev.1.0.0 ©2005 Fairchild Semiconductor Corporation FSCQ1565RP Internal Block Diagram Vcc 3 Sync 5 Drain 1 + Threshold Quasi-resonant (QR) switching controller - + fs 9V/15V - Soft start Burst mode Controller VBurst Normal operation Vcc Auxiliary Vref OSC Burst Switching Vref Vref IBFB IFB Main bias Normal operation Vref Internal bias IB Idelay FB Vcc good 4.6V/2.6V : Normal QR 3.0V/1.8V : Extended QR PWM 4 2.5R S Q R Q Gate driver R LEB 600ns VSD Sync Vovp S Vcc good R Q Q AOCP Q S Q R 2 GND TSD Power off Reset Figure 2. Functional Block Diagram of FSCQ1565RP 2 Vocp FSCQ1565RP Pin Definitions Pin Number Pin Name 1 Drain 2 GND This pin is the control ground and the SenseFET source. Vcc This pin is the positive supply input. This pin provides internal operating current for both start-up and steady-state operation. Vfb This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 7.5V, the over load protection triggers resulting in shutdown of the FPS. Sync This pin is internally connected to the sync detect comparator for quasi resonant switching. In normal quasi-resonant operation, the threshold of the sync comparator is 4.6V/2.6V. Meanwhile, the sync threshold is changed to 3.0V/1.8V in extended quasi-resonant operation. 3 4 5 Pin Function Description High voltage power SenseFET drain connection. Pin Configuration TO-3PF-7L 5.Sync 4.Vfb 3.Vcc 2.GND 1.Drain Figure 3. Pin Configuration (Top View) 3 FSCQ1565RP Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Parameter Drain-Source (GND) Voltage (1) Drain-Gate Voltage (RGS=1MΩ) Gate-Source (GND) Voltage (2) Symbol Value Unit VDSS 650 V VDGR 650 V VGS ±30 V IDM 45 ADC EAS 1050 mJ Continuous Drain Current (Tc = 25°C) ID 8.3 ADC Continuous Drain Current (TC=100°C) ID 5.5 ADC VCC 20 V Drain Current Pulsed Single Pulsed Avalanche Energy (3) Supply Voltage Vsync -0.3 to 13V V VFB -0.3 to VCC V Total Power Dissipation PD 98 W Operating Junction Temperature TJ +150 °C Operating Ambient Temperature TA -25 to +85 °C Storage Temperature Range TSTG -55 to +150 °C Thermal Resistance Rthjc 1.28 °C/W ESD Capability, HBM Model (All pins excepts for Vfb) - 2.0 (Vfb=1.7kV) kV ESD Capability, Machine Model (All pins excepts for Vfb) - 300 (Vfb=170V) V Analog Input Voltage Range Notes: 1. Tj = 25°C to 150°C 2. Repetitive rating: Pulse width limited by maximum junction temperature 3. L = 21mH, VDD = 50V, RG = 25Ω, starting Tj = 25°C 4 FSCQ1565RP Electrical Characteristics (SenseFET Part) (Ta=25°C unless otherwise specified) Parameter Symbol Drain-Source Breakdown Voltage BVDSS Zero Gate Voltage Drain Current IDSS Static Drain-source on Resistance (Note) RDS(ON) Input Capacitance Coss Reverse Transfer Capacitance Crss Turn on Delay Time td(on) Turn Off Delay Time Fall Time VGS = 0V, ID = 250µA tr td (off) tf Total Gate Charge (Gate-Source+Gate-Drain) Qg Gate-Source Charge Qgs Gate-Drain (Miller) Charge Qgd Min. Typ. Max. Unit 650 - - V VDS = Max, Rating, VGS = 0V - - 200 µA VDS= 0.8*Max., Rating VGS = 0V, TC = 85°C - - 300 µA VGS = 10V, ID = 2.3A - 0.53 0.7 Ω - 3050 3965 Ciss Output Capacitance Rise Time Condition VGS = 0V, VDS = 25V, f = 1MHz VDD= 0.5BVDSS, ID= 7.0A (MOSFET switching times are essentially independent of operating temperature) VGS = 10V, ID = 7.0A, VDS = 0.5BVDSS (MOSFET Switching times are essentially independent of operating temperature) - 220 286 - 40 52 - 50 75 - 130 179 - 430 569 - 135 186 - 127 165 - 16 21 - 52 68 pF ns nC Note: 1. Pulse test : Pulse width ≤ 300µS, duty ≤ 2% 5 FSCQ1565RP Electrical Characteristics (Continued) (Ta=25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit UVLO SECTION Vcc Start Threshold Voltage VSTART VFB = GND 14 15 16 V Vcc Stop Threshold Voltage VSTOP VFB = GND 8 9 10 V Drain To PKG Breakdown Voltage (Note4) BVpkg 60HZ AC, Ta = 25°C 3500 - - V Drain To Source Breakdown Voltage BVdss Ta = 25°C 650 - - V Vdrain = 400V, Ta = 25°C - - 200 uA - SENSEFET SECTION Drain To Source Leakage Current Idss OSCILLATOR SECTION Initial Frequency FOSC Voltage Stability FSTABLE 18 20 22 kHz 12V ≤ Vcc ≤ 23V 0 1 3 % -25°C ≤ Ta ≤ 85°C 0 ±5 ±10 % Temperature Stability (Note2) ∆FOSC Maximum Duty Cycle DMAX - 92 95 98 % Minimum Duty Cycle DMIN - - - 0 % FEEDBACK SECTION Feedback Source Current IFB VFB = 0.8V 0.5 0.65 0.8 mA Shutdown Feedback Voltage VSD Vfb ≥ 6.9V 7.0 7.5 8.0 V IDELAY VFB = 5V 4 5 6 µA Shutdown Delay Current PROTECTION SECTION Over Voltage Protection VOVP Vsync ≥ 11V 11 12 13 V Over Current Latch Voltage (Note2) VOCL - 0.9 1.0 1.1 V TSD - 140 - °C Thermal Shutdown Temp (Note4) Note: 1. These parameters is the current flowing in the Control IC. 2. These parameters, although guaranteed, are tested only in EDS (wafer test) process. 3. These parameters indicate Inductor Current. 4. These parameters, although guaranteed at the design, are not tested in mass production. 6 FSCQ1565RP Electrical Characteristics (Continued) (Ta=25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Sync SECTION Sync Threshold in normal QR (H) VSH1 Vcc = 16V, Vfb = 5V 4.2 4.6 5.0 V Sync Threshold in normal QR (L) VSL1 Vcc = 16V, Vfb = 5V 2.3 2.6 2.9 V Sync Threshold in extended QR (H) VSH2 Vcc = 16V, Vfb = 5V 2.7 3.0 3.3 V Sync Threshold in extended QR (L) VSL2 Vcc = 16V, Vfb = 5V 1.6 1.8 2.0 V Extended QR enable frequency FSYH - 90 - kHz Extended QR disable frequency FSYL - 45 - kHz BURST MODE SECTION Burst Mode Enable Feedback Voltage VBEN 0.25 0.40 0.55 V Burst Mode Feedback Source Current IBFB 60 100 140 uA Burst Mode switching Time TBS VFB = 0V 1.2 1.4 1.6 ms Burst Mode Hold Time TBH VFB = 0V 1.2 1.4 1.6 ms 18 20 22 ms SOFTSTART SECTION Soft start Time (Note2) TSS CURRENT LIMIT(SELF-PROTECTION)SECTION Peak Current Limit (Note3) ILIM - Burst Mode Peak Current Limit (Note4) IBPK - 10.12 11.5 12.88 0.6 1.0 A 1.4 A TOTAL DEVICE SECTION ISTART VCC = VSTART-0.1V - 25 50 uA ISL VCC = VSTOP-0.1V - 50 100 uA - In normal operation IOP Vfb = 2V, VCC = 18V - 7 9 mA - In burst mode (without switching) IOB Vfb = GND, VCC = 18V - 0.25 0.50 mA Startup Current Sustain Latch Current Operating Supply Current (Note1) Note: 1. These parameters is the current flowing in the Control IC. 2. These parameters, although guaranteed, are tested only in EDS (wafer test) process. 3. These parameters indicate Inductor Current. 4. These parameters, although guaranteed at the design, are not tested in mass production. 7 FSCQ1565RP Comparison Between KA5Q1565RF and FSCQ1565RP Function KA5Q1565RF FSCQ1565RP Startup Current Max. 200uA Max. 50uA Lower standby power consumption Operating supply Current Typ. 10mA Typ. 7mA Operating current is reduced in burst operation to minimize standby power consumption - Normal operation : 7mA - Burst mode with switching : 7mA - Burst mode without switching : 0.25mA Switching in Burst mode Quasi-resonant switching Fixed frequency switching (20kHz) Output regulation in standby mode Vcc control with hysteresis Output voltage feedback control Output Voltage drop in burst mode about half Any level Primary side regulation Available N/A Soft start N/A Available Internal soft-start (20ms) Extended Quasiresonant switching N/A Available - Guarantees wide load range - Improved efficiency at high line input TO-3PF-5L TO-3PF-7L Package Type 8 FSCQ1565RP Advantages Easy to determine the output voltage in the standby mode Lower power consumption in the standby mode through larger output voltage drop FSCQ1565RP Electrical characteristics Burst-mode Supply Current( Non-Switching) Operating Supply Current 1.4 Normalized to 25℃ Normalized to 25℃ 1.2 1.0 0.8 -50 0 50 100 1.2 1.0 0.8 0.6 -50 150 0 50 Temp[℃ ] Normalized to 25℃ Normalized to 25℃ 1.10 1.2 1.0 0.8 0.6 0 50 Temp[℃ ] 100 1.05 1.00 0.95 0.90 -50 150 0 100 150 Initial Frequency 1.10 Normalized to 25℃ 1.10 Normalized to 25℃ 50 Temp[℃ ] Stop Threshold Voltage 1.05 1.00 0.95 0.90 -50 150 Start Threshold Voltage Start-Up Current 1.4 -50 100 Temp[℃ ] 0 50 Temp[℃ ] 100 150 1.05 1.00 0.95 0.90 -50 0 50 100 150 Temp[℃] 9 FSCQ1565RP Electrical characteristics (Continued) Maximum Duty Cycle Over Voltage Protection 1.10 Normalized to 25℃ Normalized to 25℃ 1.10 1.05 1.00 0.95 0.90 -50 0 50 100 1.05 1.00 0.95 0.90 -50 150 0 Temp[℃ ] Shutdown Delay Current Normalized to 25℃ Normalized to 25℃ 1.1 1.0 0.9 0 50 100 1.05 1.00 0.95 0.90 -50 150 0 50 100 150 Temp[℃ ] Temp[℃ ] Feedback Source Current Burst_mode Feedback Source Current 1.2 Normalized to 25℃ 1.2 Normalized to 25℃ 150 1.10 0.8 -50 10 100 Shutdown Feedback Voltage 1.2 1.1 1.0 0.9 0.8 -50 50 Temp[℃ ] 0 50 Temp[℃ ] 100 150 1.1 1.0 0.9 0.8 -50 0 50 Temp[℃ ] 100 150 FSCQ1565RP Electrical characteristics (Continued) Feedback Offset Voltage Burst_Mode Enable Feedback Voltage 1.4 1.2 Normalized to 25℃ Normalized to 25℃ 1.4 1.0 0.8 0.6 -50 0 50 Temp[℃ ] 100 1.2 1.0 0.8 0.6 -50 150 Normalized to 25℃ Normalized to 25℃ 150 1.10 1.05 1.00 0.95 0 50 100 1.05 1.00 0.95 0.90 -50 150 0 Temp[℃] 50 100 150 Temp[℃ ] Sync. Threshold in Extended QR(H) Sync. Threshold in Extended QR(L) 1.10 1.10 Normalized to 25℃ Normalized to 25℃ 100 Sync. Threshold in Normal QR(L) Sync. Threshold in Normal QR(H) 1.05 1.00 0.95 0.90 -50 50 Temp[℃] 1.10 0.90 -50 0 0 50 Temp[℃ ] 100 150 1.05 1.00 0.95 0.90 -50 0 50 100 150 Temp[℃ ] 11 FSCQ1565RP Electrical characteristics (Continued) Extended QR Disable Frequency 1.10 1.10 1.05 1.05 Normalized to 25℃ ℃ Normalized to 25℃ ℃ Extended QR Enable Freqency 1.00 0.95 0.90 -50 0 50 100 Temp[℃ ℃ ] 150 1.00 0.95 0.90 -50 50 100 150 Tem p[℃ ℃] Maximum Safe Operating Aree Pulse-by-pulse Current Limit 1.10 0 10 2 Normalized to 25℃ ℃ Operation in This Area is Limited by R DS(on) 100 us 1.05 ID, Drain Current [A] 10 1.00 0.95 1 1 ms 10 ms DC 10 0 ? Notes : o 1. T C = 25 C -1 10 o 2. T J = 150 C 3. Single Pulse -2 10 0.90 -50 0 50 100 0 1 10 150 Temp[℃ ℃]] [℃ 10 1200 AVALANCHE ENERGY, EAS[mJ] Z? JC(t), Thermal Response 3 10 Maximum Avalanch Energy Transieus Thermal Response 0 10 D=0.5 -1 ? Notes : 1. Z? JC(t) = 0.46 ? /W Max. 2. Duty Factor, D=t1/t2 3. TJM - TC = PDM * Z? JC(t) 0.2 10 0.1 0.05 0.02 0.01 -2 10 single pulse -5 10 -4 10 -3 10 -2 10 -1 10 t1, Square Wave Pulse Duration [sec] 12 2 10 VDS, Drain-Source Voltage [V] 0 10 10 1 1000 800 600 400 200 0 25 50 75 100 125 o Initial Junction Temperature, TJ [ C] 150 FSCQ1565RP Functional Description 1. Startup : Figure 4 shows the typical startup circuit and transformer auxiliary winding for FSCQ1565RP application. Before FSCQ1565RP begins switching, FSCQ1565RP consumes only startup current (typically 25uA) and the current supplied from the AC line charges the external capacitor (Ca1) that is connected to the Vcc pin. When Vcc reaches start voltage of 15V (VSTART), FSCQ1565RP begins switching, and the current consumed by FSCQ1565RP increases to 4mA. Then, FSCQ1565RP continues its normal switching operation and the power required for this device is supplied from the transformer auxiliary winding, unless Vcc drops below the stop voltage of 9V (VSTOP). To guarantee the stable operation of the control IC, Vcc has under voltage lockout (UVLO) with 6V hysteresis. Figure 5 shows the relation between the FSCQ1565RP operating supply current and the supply voltage (Vcc). The minimum average of the current supplied from the AC is given by min I sup avg 2 ⋅ V ac V start 1 - ⋅ ---------= ----------------------------- – ------------2 R str π where Vacmin is the minimum input voltage, Vstart is the FSCQ1565RP start voltage (15V) and Rstr is the startup resistor. The startup resistor should be chosen so that Isupavg is larger than the maximum startup current (50uA). Once the resistor value is determined, the maximum loss in the startup resistor is obtained as max 2 max 2 ) + V start 2 2 ⋅ V start ⋅ V ac 1 ( V ac - - – ----------------------------------------------------Loss = ---------- ⋅ -------------------------------------------------R str π 2 where Vacmax is the maximum input voltage. The startup resistor should have proper rated dissipation wattage. 2. Synchronization : FSCQ1565RP employs quasi-resonant switching technique to minimize the switching noise and loss. In this technique, a capacitor (Cr) is added between the MOSFET drain and source as shown in Figure 6. The basic waveforms of quasi-resonant converter are shown in Figure 7. The external capacitor lowers the rising slop of drain voltage to reduce the EMI caused when the MOSFET turns off. In order to minimize the MOSFET switching loss, the MOSFET should be turned on when the drain voltage reaches its minimum value as shown in Figure 7. C DC 1N4007 AC line (V acmin - V acmax) Isup Rstr Da Vcc FSCQ1565RP C a2 C a1 C DC + V DC - Np Ns Lm Vo Figure 1. Startup circuit Drain Cr Ids Sync Icc + V ds - GND V co V cc Da R cc C a1 C a2 Na D SY 4mA R SY1 Power Down Power Up C SY 25uA R SY2 Vcc Vstop=9V Vstart=15V Vz Figure 3. Synchronization circuit Figure 2. Relation between operating supply current and Vcc voltage 13 FSCQ1565RP Vds MOSFET off MOSFET on 2V R O Vgs TQ VRO Vs ync VRO Vds V sypk VDC Vrh (4 .6V) Vrf (2 .6V) TR Ids Ipk Figure 4. Quasi-resonant operation waveforms MOS FET Gate ON ON Figure 5. Normal quasi-resonant operation waveforms The minimum drain voltage is indirectly detected by monitoring the Vcc winding voltage as shown in Figure 6 and 8. The voltage divider RSY1 and RSY2 should be chosen so that the peak voltage of sync signal (Vsypk) is lower than the OVP voltage (12V) in order to avoid triggering OVP in normal operation. It is typical to set Vsypk to be lower than OVP voltage by 3-4 V. In order to detect the optimum time to turn on MOSFET, the sync capacitor (CSY) should be determined so that TR is the same with TQ as shown in Figure 8. The TR and TQ are given as, respectively Switching frequency Extended QR operation 90kHz Normal QR operation 45kHz TR V co R SY2 = R SY2 ⋅ C SY ⋅ ln --------- ⋅ ----------------------------------- 2.6 R SY1 + R SY2 T Q = π ⋅ L m ⋅ C eo N a ⋅ ( V o + V FO ) V co = ---------------------------------------- – V Fa Ns where Lm is the primary side inductance of the transformer, Ns and Na are the number of turns for the output winding and Vcc winding, respectively, VFo and VFa are the diode forward voltage drops of the output winding and Vcc winding, respectively, and Ceo is the sum of the output capacitance of MOSFET and external capacitor Cr. 14 Output power Figure 6. Extended quasi-resonant operation In general, quasi-resonant converter has a limitation in a wide load range application, since the switching frequency increases as the output load decreases, resulting in a severe switching loss in the light load condition. In order to get over this limitation, FSCQ1565RP employs extended quasiresonant switching operation. Figure 9 shows the mode change between normal quasi-resonant operation and extended quasi-resonant operation. In the normal quasiresonant operation, the FSCQ1565RP enters into the extended quasi-resonant operation when the switching frequency exceeds 90kHz as the load reduces. Then, the MOSFET is turned on, when the drain voltage reaches the second minimum level as shown in Figure 10, which reduces the switching frequency. FSCQ1565RP Once FSCQ1565RP enters into extended quasi-resonant operation, the first sync signal is ignored. After the first sync signal is applied, the sync threshold levels are changed from 4.6V and 2.6V to 3V and 1.8V, respectively, and the MOSFET turn-on time is synchronized to the second sync signal. The FSCQ1565RP goes back to its normal quasiresonant operation when the switching frequency reaches 45kHz as the load increases. internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by external resonant capacitor across the MOSFET and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FSCQ1565RP employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on. Vds Vcc 2VRO Vref Idelay IFB Vfb Vo 4 H11A817A CB D2 2.5R + Vfb* Vsync KA431 3V Gate driver R - 4.6V 2.6V SenseFET OSC D1 VSD OLP Rsense 1.8V Figure 8. Pulse width modulation (PWM) circuit MOSFET Gate ON ON Figure 7. Extended quasi-resonant operation waveforms 3. Feedback Control : FSCQ1565RP employs current mode control, as shown in Figure 11. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. 3.1 Pulse-by-pulse current limit: Because current mode control is employed, the peak current through the Sense FET is limited by the inverting input of PWM comparator (Vfb*) as shown in Figure 11. The feedback current (IFB) and internal resistors are designed so that the maximum cathode voltage of diode D2 is about 2.8V, which occurs when all IFB flows through the internal resistors. Since D1 is blocked when the feedback voltage (Vfb) exceeds 2.8V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping Vfb*. Therefore, the peak value of the current through the Sense FET is limited. 4. Protection Circuit : The FSCQ1565RP has several self protective functions such as over load protection (OLP), abnormal over current protection (AOCP), over voltage protection (OVP) and thermal shutdown (TSD). OLP and OVP are auto-restart mode protection, while TSD and AOCP are latch mode protection. Because these protection circuits are fully integrated into the IC without external components, the reliability can be improved without increasing cost. -Auto-restart mode protection: Once the fault condition is detected, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc falls down to the under voltage lockout (UVLO) stop voltage of 9V, the protection is reset and FSCQ1565RP consumes only startup current (25uA). Then, Vcc capacitor is charged up, since the current supplied through the startup resistor is larger than the current that FPS consumes. When Vcc reaches the start voltage of 15V, FSCQ1565RP resumes its normal operation. If the fault condition is not removed, the SenseFET remains off and Vcc drops to stop voltage again. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see Figure 12). -Latch mode protection: Once protection triggers, switching is terminated and the Sense FET remains off until the AC power line is un-plugged. Then, Vcc continues charging and discharging between 9V and 15V. The latch is reset only when Vcc is discharged to 6V by un-plugging the Ac power line. 3.2 Leading edge blanking (LEB) : At the instant the 15 FSCQ1565RP Vds Power on Fault occurs V FB Fault removed Over load protection 7.5V Vcc 2.8V 15V T12= CB*(7.5-2.8)/Idelay 9V T1 T2 t Figure 10. Over load protection Iop t Normal operation Fault situation Normal operation Figure 9. Auto restart mode protection 4.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger in order to protect the SMPS. However, even when the SMPS is in the normal operation, the over load protection circuit can be triggered during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to trigger after a specified time to determine whether it is a transient situation or an overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the Sense FET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes more than this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.8V, D1 is blocked and the 5uA current source starts to charge CB slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 7.5V, when the switching operation is terminated as shown in Figure 13. The delay time for shutdown is the time required to charge CB from 2.8V to 7.5V with 5uA. In general, a 20 ~ 50 ms delay time is typical for most applications. This protection is implemented in auto restart mode. 16 2.5R OSC PWM R S Q R Q Gate driver LEB Rsense 2 AOCP - 25uA 4.2 Abnormal Over Current Protection (AOCP) : When the secondary rectifier diodes or the transformer pins are shorted, a steep current with extremely high di/dt can flow through the SenseFET during the LEB time. Even though the FSCQ1565RP has OLP (Over Load Protection), it is not enough to protect the FSCQ1565RP in that abnormal case, since sever current stress will be imposed on the SenseFET until OLP triggers. The FSCQ1565RP has an internal AOCP (Abnormal Over Current Protection) circuit as shown in Figure 14. When the gate turn-on signal is applied to the power Sense FET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is then compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, the set signal is applied to the latch, resulting in the shutdown of SMPS. This protection is implemented in latch mode. + 4mA Vaocp GND Figure 11. AOCP block 4.3 Over voltage Protection (OVP) : If the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, Vfb climbs up in a similar manner to the over load situation, FSCQ1565RP forcing the preset maximum current to be supplied to the SMPS until the over load protection triggers. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the over load protection triggers, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, the peak voltage of the sync signal is proportional to the output voltage and the FSCQ1565RP uses sync signal instead of directly monitoring the output voltage. If sync signal exceeds 12V, an OVP is triggered resulting in a shutdown of SMPS. In order to avoid undesired triggering of OVP during normal operation, the peak voltage of sync signal should be designed to be below 12V. This protection is implemented in auto restart mode. V o2 5. Soft Start : The FSCQ1565RP has an internal soft start circuit that increases PWM comparator inverting input voltage together with the SenseFET current slowly after it starts up. The typical soft start time is 20msec. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. For a fast build up of the output voltage, an offset is introduced in the soft-start reference current. 6. Burst operation : In order to minimize the power consumption in the standby mode, FSCQ1565RP employs burst operation. Once FSCQ1565RP enters into burt mode, FSCQ1565RP allows all output voltages and effective switching frequency to be reduced. Figure 15 shows the typical feedback circuit for C-TV applications. In normal operation, the picture on signal is applied and the transistor Q1 is turned on, which de-couples R3, Dz and D1 from the feedback network. Therefore, only Vo1 is regulated by the feedback circuit in normal operation and determined by R1 and R2 as V o1 norm = V Z + 0.7 + 2.5 VO2 Linear Regulator VO1 (B+) RD R1 CF KA431 A Micom Dz Rbias C 4.4 Thermal Shutdown (TSD) : The SenseFET and the control IC are built in one package. This makes it easy for the control IC to detect the abnormal over temperature of the SenseFET. When the temperature exceeds approximately 150°C, the thermal shutdown triggers. This protection is implemented in latch mode. stby RF D1 R3 Q1 Picture ON R R2 Figure 12. Typical feedback circuit to drop output voltage in standby mode Figure 16 shows the burst mode operation waveforms. When the picture ON signal is disabled, Q1 is turned off and R3 and Dz are connected to the reference pin of KA431 through D1. Before Vo2 drops to Vo2stby, the voltage on the reference pin of KA431 is higher than 2.5V, which increases the current through the opto LED. This pulls down the feedback voltage (VFB) of FSCQ1565RP and forces FSCQ1565RP to stop switching. If the switching is disabled longer than 1.4ms, FSCQ1565RP enters into burst operation and the operating current is reduced from 4mA (IOP) to 0.35mA (IOB). Since there is no switching, Vo2 decrease until it reaches Vo2stby. As Vo2 reaches Vo2stby, the current through the opto LED decreases allowing the feedback voltage to rise. When the feedback voltage reaches 0.4V, FSCQ1565RP resumes switching with a predetermined peak drain current of 0.9A. After burst switching for 1.4ms, FSCQ1565RP stops switching and checks the feedback voltage. If the feedback voltage is below 0.4V, FSCQ1565RP stops switching until the feedback voltage increases to 0.4V. If the feedback voltage is above 0.4V, FSCQ1565RP goes back to the normal operation. R1 + R2 = 2.5 ⋅ --------------------- R2 In standby mode, the picture on signal is disabled and the transistor Q1 is turned off, which couples R3, Dz and D1 to the reference pin of KA431. Then, Vo2 is determined by the zener diode breakdown voltage. Assuming that the forward voltage drop of D1 is 0.7V, Vo2 in standby mode is approximately given by 17 FSCQ1565RP (a) (b) (c) Vo2 norm V o2 stby V FB 0.4V Iop I OP (4m A) I OB (0.35m A) Vds Picture On Picture On Picture Off Burst Mode 0.4V 0.4V 0.3V VFB 0.4V Vds 1.4ms Ids 1.4ms 0.9A 1.4ms 0.9A (a) M ode change to Burst operation (b) Burst operation (c) M ode change to Normal operation Figure 13. Waveforms of burst operation 18 FSCQ1565RP Typical application circuit Application Output power Input voltage Output voltage (Max current) 8.5V (1A) C-TV 210W Universal input 15V (1A) (85-265Vac) 126V (0.9A) 24V (2A) Features • • • • • • High efficiency (>80% at 85Vac input) Wider load range through the extended quasi-resonant operation Low standby mode power consumption (<1W) Low component count Enhanced system reliability through various protection functions Internal soft-start (20ms) Key Design Notes • 24V output is designed to drop to around 7V in standby mode 1. Schematic T1 EER4942 RT101 5D-11 3 R101 100kΩ Ω 0.25W BD101 R106 C104 1kΩ Ω 10uF 1W 50V SYNC 3 Vcc IC101 5 FSCQ1565RP GND 2 C103 10uF 50V FB 4 C106 47nF 50V C210 470pF 1kV D105 1N4937 8.5V, 1A 13 C107 1nF 1kV 12 C209 470pF 1kV C205 1000uF 35V D202 EGP30J D106 1N4148 R105 470Ω Ω 0.25W R104 D103 R103 6 1.5kΩ Ω 1N4937 5.1Ω Ω 0.25W 0.25W 14 15 16 C105 2.7nF 50V C207 470pF 1kV L202 C201 BEAD 220uF 160V 140V, 0.9A C202 100uF 160V D203 EGP30D 24V, 2A 17 7 LF101 18 OPTO101 817A C208 470pF 1kV R202 1kΩ Ω 0.25W C301 3.3nF C203 2200uF 35V VR201 30kΩ Ω R201 1kΩ Ω 0.25W C101 330nF 275VAC FUSE 250V 5.0A C204 1000uF 35V D204 EGP20D 4 1 Drain ZD102 18V 1W 11 BEAD101 R102 150kΩ Ω 0.25W 15V, 1A 10 1 C102 470uF 400V D205 EGP20D Q201 KA431 LZ C206 22nF 50V R203 39kΩ Ω 0.25W R205 240kΩ Ω D201 0.25W 1N4148 R204 4.7kΩ Ω 0.25W ZD201 5.1V 0.5W R208 1kΩ Ω 0.25W Q202 KSC945 SW201 R207 5.1kΩ Ω 0.25W R206 10kΩ Ω 0.25W 19 FSCQ1565RP 2. Transformer Schematic Diagram EE R 4245 EER4942 Np1 1 18 2 17 3 16 4 15 N 24V Np2 5 14 6 13 Na N 15V N8.5V N140V /2/2 N 125V N 140V /2 /2 NN140V 125V /2 NP 2 N 140V /2 N8.5V Na 7 12 8 11 9 10 NP 1 N24 N15V 3.Winding Specification No N24 Np1 Pin (s→f) Wire Turns Winding Method 18 - 17 φ 7 Space Winding 0.08 × 20 × 2 18 Center Winding 0.08φ × 20 × 2 20 Center Winding 0.08φ × 20 × 2 18 Center Winding 20 Center Winding 1-3 N140V/2 16 - 15 Np2 3-4 N140V/2 N8.5V N15V Na 15 - 14 0.65 × 2 φ φ 0.08 × 20 × 2 12 - 13 0.6φ ×1 3 Space Winding 11 - 10 φ 0.4 × 2 5 Space Winding 7-6 φ 12 Space Winding 0.3 × 1 4.Electrical Characteristics Inductance Leakage Inductance 5. Core & Bobbin Core : EER 4942 Bobbin : EER4942(18Pin) Ae : 231 mm2 20 Pin Specification 1-4 225uH ± 5% 1-4 10uH Max Remarks 1kHz, 1V 2nd all short FSCQ1565RP 6.Demo Circuit Part List Part Value Note Fuse FUSE 250V / 5A Part Value Note C210 470pF / 1kV Ceramic Capacitor C301 3.3nF / 1kV AC Ceramic Capacitor NTC RT101 Inductor 5D-11 Resistor BEAD101 BEAD BEAD201 5uH 3A R101 100kΩ 0.25 W Diode R102 150kΩ 0.25 W D101 1N4937 1A, 600V R103 5.1Ω 0.25 W D102 1N4937 1A, 600V R104 1.5kΩ 0.25 W D103 1N4148 0.15A, 50V R105 470Ω 0.25 W D104 Short R106 1kΩ 1W D105 Open R107 Open ZD101 1N4746 R201 1kΩ 0.25 W ZD102 Open R202 1kΩ 0.25 W ZD201 1N5231 5.1V, 0.5W R203 39kΩ 0.25 W D201 1N4148 0.15A, 50V R204 4.7kΩ 0.25 W , 1% D202 EGP30J 3A, 600V R205 240kΩ 0.25 W , 1% D203 EGP30D 3A, 200V R206 10kΩ 0.25 W D204 EGP20D 2A, 200V R207 5.1kΩ 0.25 W D205 EGP20D 2A, 200V R208 1kΩ 0.25 W VR201 30kΩ C101 330n/275Vac Box Capacitor C102 470uF / 400V Electrolytic C103 10uF / 50V Electrolytic C104 10uF / 50V Electrolytic C105 2.7nF / 50V Film Capacitor C106 47nF / 50V Film Capacitor C107 1nF / 1kV Film Capacitor C108 Open C201 220uF / 200V C202 100uF / 200V C203 2200uF / 35V C204 1000uF / 35V Electrolytic C205 1000uF / 35V Electrolytic C206 22nF / 50V Film Capacitor C207 470pF / 1kV Ceramic Capacitor C208 470pF / 1kV Ceramic Capacitor C209 470pF / 1kV Ceramic Capacitor 18V, 1W Bridge Diode Capacitor BD101 GSIB660 6A, 600V Line Filter LF101 14mH Transformer T101 EER4942 SW201 ON/OFF Switch For MCU Signal IC IC101 FSCQ1565RP OPT101 817A Electrolytic Q201 KA431LZ Electrolytic Q202 KSC945 Electrolytic TO220F-5L TO-92 21 FSCQ1565RP 7. Layout Figure 14. Layout Considerations for FSCQ1565RP Figure 15. Layout Considerations for FSCQ1565RP 22 FSCQ1565RP Package Dimensions Dimensions in Millimeters TO-3PF-7L(Forming) 6.05 5.65 15.70 15.30 3.55 3.15 9.70 9.30 (1.65) 4.70 4.30 10.20 9.80 2.10 1.70 23.20 22.80 24.70 24.30 36.50 35.50 1.70 1.30 4.30 3.70 (1.00) 2.55 2.15 3.65 3.05 3.06 2.46 R0.90 MAX 1.00 12.00 11.00 R0.90 0.90 0.70 MAX 2.00 2.80 2.20 R0.90 5.30 4.70 2.54 0.80 0.50 3.48 2.88 1.50 4.50 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE DOES NOT COMPLY TO ANY CURRENT PACKAGING STANDARD. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. MKT-TO3PFC05revA 23 FSCQ1565RP Ordering Information Product Number Package Marking Code BVdss Rds(ON) Max. FSCQ1565RPSYDTU TO-3PF-7L(Forming) CQ1565RP 650V 0.7 Ω SYDTU : Forming Type DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 1/11/05 0.0m 001 2005 Fairchild Semiconductor Corporation