www.fairchildsemi.com
FSDM311
Green Mode Fairchild Power Switch (FPSTM)
Features
• Internal Avalanche Rugged Sense FET
• Precision Fixed Operating Frequency (67kHz)
• Advanced Burst-Mode operation Consumes under 0.2W
at 265Vac and no load
• Internal Start-up Switch and Soft Start
• Under Voltage Lock Out (UVLO) with Hysteresis
• Pulse by Pulse Current Limit
• Over Load Protection (OLP)
• Over Voltage Protection (OVP)
• Internal Thermal Shutdown Function (TSD)
• Secondary Side Regulation
• Auto-Restart Mode
Applications
TYPICAL POWER CAPABILITY
PRODUCT
Open Frame
230VAC ±15%(1)
85-265VAC
FSDM311
20W
12W
FSDM311L
20W
12W
Table 1. Notes: 1. 230 VAC or 100/115 VAC with doubler.
Typical Circuit
AC
IN
DC
OUT
• Charger & Adaptor for Mobile Phone, PDA & MP3
• Auxiliary Power for White Goods, PC, C-TV & Monitor
Vstr
Description
The FSDM311 is an integrated Pulse Width Modulator
(PWM) and Sense FET specially designed for high performance off-line Switch Mode Power Supplies (SMPS) with
minimal external components. This device is a monolithic
high voltage power switching regulator which combines an
VDMOS Sense FET with a voltage mode PWM control
block. The integrated PWM controller features include: a
fixed oscillator, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), optimized gate turn-on/
turn-off driver, thermal shut down protection (TSD), temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a
discrete MOSFET and controller or RCC switching converter solution, the FSDM311 reduces total component
count, design size, weight and at the same time increases
efficiency, productivity, and system reliability. This device is
a basic platform well suited for cost effective designs of flyback converters.
Drain
PWM
Vfb
Vcc
Source
Figure 1. Typical Flyback Application using FSDM311
Rev.1.0.5
©2004 Fairchild Semiconductor Corporation
FSDM311
Internal Block Diagram
Vstr
5
6,7,8
L
Vcc 2
Internal
Bias
Voltage
Ref
UVLO
Drain
H
8.7/6.7V
Vck
OSC
5uA
400uA
SFET
DRIVER
PWM
S
Vfb 3
Q
R
S/S
15mS
BURST
LEB
VBURST
NC 4
OLP
Iover
Reset
S
V SD
Min.20V
Q
Rsense
Vth
R
OVP
TSD
A/R
1
Figure 2. Functional Block Diagram of FSDM311
2
GND
FSDM311
Pin Definitions
Pin Number
Pin Name
1
GND
Sense FET source terminal on primary side and internal control ground.
Vcc
Positive supply voltage input. Although connected to an auxiliary
transformer winding, current is supplied from pin 8 (Vstr) via an internal
switch during startup (see Internal Block Diagram section). It is not until Vcc
reaches the UVLO upper threshold (8.7V) that the internal start-up switch
opens and device power is supplied via the auxiliary transformer winding.
Vfb
The feedback voltage pin is the inverting input to the PWM comparator with
nominal input levels between 0.5Vand 2.5V. It has a 0.40mA current source
connected internally while a capacitor and opto coupler are typically
connected externally. A feedback voltage of 4.5Vtriggers overload
protection
(OLP). There is a time delay while charging between 3V and 4.5V using an
internal 5uA current source, which prevents false triggering under transient
conditions but still allows the protection mechanism to operate under true
overload conditions.
Vstr
The startup pin connects directly to the rectified AC line voltage source for
FSDM311. For the FSDM311, at start up the internal switch supplies internal
bias and charges an external storage capacitor placed between the Vcc pin
and ground. Once this reaches 9V, the internal current source is disabled.
Drain
The Drain pin is designed to connect directly to the primary lead of the
transformer and is capable of switching a maximum of 650V. Minimizing the
length of the trace connecting this pin to the transformer will decrease
leakage inductance.
2
3
5
6, 7, 8
Pin Function Description
Pin Configuration
8DIP
8LSOP
GND 1
8 Drain
Vcc 2
7 Drain
Vfb 3
6 Drain
Ipk 4
5 Vstr
Figure 3. Pin Configuration (Top View)
3
FSDM311
Absolute Maximum Ratings
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Value
Unit
VSTR,MAX
650
V
VDRAIN,MAX
650
V
VDGR
650
V
Gate-Source (GND) Voltage
VGS
±20
V
Drain Current Pulsed (1)
IDM
1.5
ADC
Continuous Drain Current (Tc=25°C)
ID
0.5
ADC
Continuous Drain Current (Tc=100°C)
ID
0.32
ADC
EAS
10
mJ
Maximum Vstr Pin Voltage
Maximum Drain Pin Voltage
Drain-Gate Voltage (RGS=1MΩ)
Single Pulsed Avalanche
Energy (2)
VCC,MAX
20
V
Input Voltage Range
VFB
−0.3 to Vstop
V
Total Power Dissipation
PD
1.25
W
Operating Junction Temperature.
TJ
+150
°C
Operating Ambient Temperature.
TA
-25 to +85
°C
TSTG
-55 to +150
°C
Symbol
Value
Unit
θJA(1)
θJA(1)
θJC(2)
?(3)
°C/W
?(4)
°C/W
Maximum Supply Voltage
Storage Temperature Range.
1. Repetitive rating: Pulse width limited by maximum junction temperature
2. L=24mH, starting Tj=25°C
Thermal Impedance
Parameter
8DIP
Junction-to-Ambient Thermal
Junction-to-Case Thermal
Note:
1. Free standing without heatsink.
2. Measured on the GND pin close to plastic interface.
3. Soldered to 100mm2 copper clad.
4. Soldered to 300mm2 copper clad.
4
°C/W
FSDM311
Electrical Characteristics (Sense FET Part)
(Ta = 25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
VGS=0V, ID=50µA
650
720
-
V
VDS=Max. Rating,
VGS=0V
-
-
25
µA
VDS=0.8Max. Rating,
VGS=0V, TC=125°C
-
-
200
µA
RDS(ON)
VGS=10V, ID=0.5A
-
14
19
Ω
gfs
VDS=50V, ID=0.5A
1.0
1.3
-
S
-
162
-
VGS=0V, VDS=25V,
f=1MHz
-
18
-
-
3.8
-
-
9.5
-
-
19
-
-
33
-
-
42
-
-
7.0
-
-
3.1
-
-
0.4
-
Sense FET SECTION
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Static Drain-Source on Resistance
(Note)
Forward Trans conductance (Note)
BVDSS
IDSS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Turn on Delay Time
td(on)
Rise Time
Turn Off Delay Time
Fall Time
tr
td(off)
tf
Total Gate Charge
(Gate-Source + Gate-Drain)
Qg
Gate-Source Charge
Qgs
Gate-Drain (Miller) Charge
Qgd
VDD=0.5B VDSS,
ID=1.0A
(MOSFET switching time
is essentially
independent of
operating temperature)
VGS=10V, ID=1.0A,
VDS=0.5B VDSS
(MOSFET switching time
is essentially
independent of operating
temperature)
pF
ns
nC
Note:
1. Pulse test: Pulse width ≤ 300µS, duty ≤ 2%
2.
1
S = ---R
5
FSDM311
Electrical Characteristics (Control Part) (Continued)
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
UVLO SECTION
Start Threshold Voltage
VSTART
VFB=GND
8
9
10
V
Stop Threshold Voltage
VSTOP
VFB=GND
6
7
8
V
61
67
73
kHz
OSCILLATOR SECTION
Initial Accuracy
FOSC
Frequency Change With Temperature
(2)
Maximum Duty Cycle
∆F/∆T
-25°C ≤ Ta ≤ +85°C
-
±5
±10
%
60
67
74
%
0.35
0.40
0.45
mA
4.0
4.5
5.0
V
4
5
6
µA
0.6
0.70
0.8
V
0.45
0.55
0.65
V
-
150
-
mV
4.20
4.50
4.80
V
-
0.3
0.6
mV/°C
IOVER
0.475
0.55
0.625
A
TSOFT
10
15
20
ms
125
145
-
°C
20
-
-
V
450
550
650
µA
-
1.5
3.0
mA
Dmax
FEEDBACK SECTION
Feedback Source Current
IFB
Shutdown Feedback Voltage
VSD
Shutdown Delay Current
IDELAY
Ta=25°C, 0V ≤ Vfb ≤ 3V
Ta=25°C, 3V ≤ Vfb ≤ VSD
BURST MODE SECTION
VBURH
Burst Mode Voltage
VBURL
Tj = 25°C
Hysteresis
REFERENCE SECTION
Output Voltage (1)
Temperature Stability
Vref
(1)(2)
Vref/∆T
Ta=25°C
-25°C ≤ Ta ≤ +85°C
CURRENT LIMIT(SELF-PROTECTION)SECTION
Peak Current Limit
SOFT START SECTION
Soft Start Time
PROTECTION SECTION
Thermal Shutdown Temperature (1)
Over Voltage Protection
TSD
-
VOVP
TOTAL STANDBY CURRENT SECTION
Start-up Current
ISTR
VCC=0V, VSTR=50V
Operating Supply Current
(Control Part Only)
IOP
VCC ≤ 16
Note:
1. These parameters, although guaranteed, are not 100% tested in production
2. These parameters, although guaranteed, are tested in EDS (wafer test) process
6
FSDM311
Comparison Between FSDH0165 and FSDM311
Function
7
FSDH0165
FSDM311
FSDM311 Advantages
Soft-Start
not applicable
15mS
• Gradually increasing current limit
during soft-start further reduces peak
current and voltage component
stresses
• Eliminates external components used
for soft-start in most applications
• Reduces or eliminates output
overshoot
Burst Mode Operation
not applicable
Yes-built into
controller
• Improve light load efficiency
• Reduces no-load consumption
• Transformer audible noise reduction
Drain Creepage at
Package
1.02mm
3.56mm DIP
3.56mm LSOP
• Greater immunity to arcing as a result
of build-up of dust, debris and other
contaminants
FSDM311
Typical Performance Characteristics
1.15
1.15
1.10
1.10
1.05
1.05
1.00
1.00
Iop
Vref
(These characteristic graphs are normalized at Ta=25°C)
0.95
0.95
0.90
0.90
0.85
0.85
-50
0
50
100
150
-50
0
Temperature('C)
1.15
1.15
1.10
1.10
1.05
1.05
1.00
150
1.00
0.95
0.95
0.90
0.90
0.85
0.85
-50
0
50
100
-50
150
0
50
100
150
Temperature('C)
Temperature('C)
Start Threshold Voltage vs. Temp
Stop Threshold Voltage vs. Temp
1.15
1.15
1.10
1.10
1.05
1.05
Dmax
Fosc
100
Operating Current vs. Temp
Vstop
Vstart
Reference Voltage vs. Temp
1.00
1.00
0.95
0.95
0.90
0.90
0.85
0.85
-50
0
50
100
Temperature('C)
Frequency vs. Temp
8
50
Temperature('C)
150
-50
0
50
100
Temperature('C)
Maximum Duty vs. Temp
150
FSDM311
Typical Performance Characteristics (Continued)
1.15
1.15
1.10
1.10
1.05
1.05
1.00
1.00
Ifb
Iover
(These characteristic graphs are normalized at Ta=25°C)
0.95
0.95
0.90
0.90
0.85
0.85
0
50
100
150
-50
0
50
100
Temperature('C)
Temperature('C)
Peak Current Limit vs. Temp
Feedback Source Current vs. Temp
1.15
1.15
1.10
1.10
1.05
1.05
1.00
1.00
Vsd
Idelay
-50
0.95
0.95
0.90
0.90
150
0.85
0.85
-50
0
50
100
150
-50
0
50
100
Temperature('C)
Temperature('C)
ShutDown Delay Current vs. Temp
ShutDown Feedback Voltage vs. Temp
150
1.15
1.10
Vovp
1.05
1.00
0.95
0.90
0.85
-50
0
50
100
150
Temperature('C)
Over Voltage Protection vs. Temp
9
FSDM311
Functional Description
Figure 5. Charging the Vcc capacitor through Vstr
1. Startup : At startup, the internal high voltage current
source supplies the internal bias and charges the external
Vcc capacitor as shown in Figure 4. In the case of the
FSDM311, when Vcc reaches 9V the device starts switching
and the internal high voltage current source is disabled. The
device continues to switch provided that Vcc does not drop
below 7V. After startup the bias is supplied from the auxiliary transformer winding.
Vin,dc
2. Feedback Control : The FSDM311 are the voltage mode
devices as shown in Figure 6. Usually, an opto-coupler and
KA431 type voltage reference are used to implement the
feedback network. The feedback voltage is compared with
an internally generated sawtooth waveform. This directly
controls the duty cycle. When the KA431 reference pin voltage exceeds the internal reference voltage of 2.5V, the optocoupler LED current increase pulling down the feedback
voltage and reducing the duty cycle. This will happen when
the input voltage increases or the output load decreases.
Istr
Vstr
Vcc
L
H
9V/
7V
FSDM311
Figure 4. Internal startup circuit
Calculating the Vcc capacitor is an important step to designing in the FSDM311. At initial start-up in the FSDM311, the
stand-by maximum current is 100uA, supplying current to
UVLO and Vref Block. The charging current (i) of the Vcc
capacitor is equal to Istr - 100uA. After Vcc reaches the
UVLO start voltage only the bias winding supplies Vcc current to device. When the bias winding voltage is not sufficient, the Vcc level decreases to the UVLO stop voltage. At
this time Vcc oscillates. In order to prevent this ripple it is
recommended that the Vcc capacitor be sized between 10uF
and 47uF.
3. Leading edge blanking (LEB) : When the MOSFET is
turned on, there usually exists a high current spike through
the MOSFET. This is caused by primary side capacitance
and secondary side rectifier reverse recovery. This could
cause premature termination of the switching pulse if it
exceeded the over-current threshold. Therefore, the FPS
employs the leading edge blanking (LEB) circuit. This circuit inhibits the over current comparator for a short time
after the MOSFET is turned on.
Vcc
5uA
Vfb
Vo
OSC
Vref
0.40mA
Gate
driver
FB
4
Cfb
R
Vin,dc
Istr
KA431
VSD
Vstr
i = Istr-max current
i = Istr-max current
Vcc
J-FET
Figure 6. PWM and feedback circuit
max
current
UVLO
Vref
FSDM311
Vcc
UVLO
start
Vcc must not drop
to UVLO stop
UVLO
stop
Auxiliary winding
voltage
t
10
OLP
4. Protection Circuit : The FSDM311 has 3self protection
functions: over-load protection (OLP), thermal shutdown
(TSD) and over-voltage protection. Because these protection
circuits are fully integrated into the IC with no external components, system reliability is improved without cost increase.
If either of these functions are triggered, the FPS starts an
auto-restart cycle. Once the fault condition occurs, switching
is terminated and the MOSFET remains off. This cause Vcc
to fall. When Vcc reaches the UVLO stop voltage (7V), the
protection is reset and the internal high voltage current
source charges the Vcc capacitor. When Vcc reaches the
UVLO start voltage (9V), the device attempts to resume normal operation. If the fault condition is no longer present start
up will be successful. If it is still present the cycle is
repeated. This is shown in Figure 7.
FSDM311
Vfb
OSC
5uA
400uA
Vfb
4
R
Cfb
S
+
-
Q
R
OLP
4.5V
GATE
DRIVER
3V
3V
FPS Switching Area
OLP
S
RESET
Vth 4.5V
R
TSD
A/R
Q
FSDM311
OLP, TSD
Protection Block
Idelay (5uA) charges Cfb
IC Reset
t
Figure 7. Protection block
4.1 Over Load Protection (OLP) : Overload is a load current that exceeds a pre-set level due to an abnormal situation.
If this occurs, the protection circuit should be triggered to
protect the SMPS. It is possible that a short term load transient can occur under normal operation. If this occurs the
system should not shut down. In order to avoid false shutdowns, the over load protection circuit is designed to trigger
after a delay. Therefore the device can discriminate between
transient overloads and true fault conditions. The device is
pulse-by-pulse current limited and therefore, for a given
input voltage, the maximum input power is limited. If the
load tries to draw more than this, the output voltage will drop
below its set value. This reduces the opto-coupler LED current which in turn will reduce the photo-transistor current.
Therefore, the 400uA current source will charge the feedback pin capacitor, Cfb, and the feedback voltage, Vfb, will
increase. The input to the feedback comparator is clamped at
around 3V. Therefore, once Vfb reaches 3V, the device is
switching at maximum power. At this point the 400uA current source is blocked and the 5uA source continues to
charge Cfb. Once Vfb reaches 4.5V, switching stops. Therefore the shutdown delay time is set by the time required to
charge Cfb from 3V to 4.5V with 5uA as shown in Fig. 5.
t1
t2
t1<<t2, t3
t1 = -1/RCΧ ln( 1-v(t1)/R )
t2 = CΧ [v(t1+t2)-v(t1)] Χ Idelay
t3
v(t1)=3V
Figure 8. Over load protection delay
5. Soft Start : The FPS has an internal soft start circuit that
increases the drain current limit together with the MOSFET
current slowly after it starts up. The soft start time is typical
15msec as shown in figure 9. It progressively increases during the start-up phase. The pulse width to the power switching devices is progressively increased to establish the correct
working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively
increased with the intention of smoothly establishing the
required output voltage. Consequently it prevents the transformer’s saturation and the secondary diodes’s stress.
Drain current
[A]
0.55A
2mS
7steps
0.31A
4.2 Thermal Shutdown (TSD) : The Sense FET and the
control IC are assembled in one package. This makes it easy
for the control IC to detect the temperature of the Sense FET.
When the temperature exceeds approximately 145°C, thermal shutdown is activated.
t
Figure 9. Internal Soft Start
11
FSDM311
6. Burst operation : In order to minimize the power dissipation in standby mode, the FSDM311 implements burst mode.
OSC
S
5uA
400uA
Q
GATE
DRIVER
R
4
on/off
Vfb
0.70V
/0.55V
FSDM311
Burst operation Block
Figure 10. Circuit for burst operation
As the load decreases, the feedback voltage decreases. The
device automatically enters burst mode when the feedback
voltage drops below VBURL(0.55V). At this point switching
stops and the output voltages start to drop. This causes the
feedback voltage to rise. Once is passes VBURH(0.70V)
switching starts again. The feedback voltage falls and the
process repeats. Burst mode operation alternately enables
and disables switching of the power MOSFET to reduce the
switching loss in the standby mode.
Vo
Vo
set
V FB
0.7V
0.55V
Ids
Vds
time
Figure 11. Burst mode operation
12
FSDM311
Package Dimensions
8DIP
13
FSDM311
Package Dimensions (Continued)
8LSOP
14
FSDM311
Ordering Information
Product Number
Package
Marking Code
Topr (°C)
FSDM311
8DIP
DM311
650V
FSDM311L
8LSOP
DM311
650V
15
FSDM311
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
10/1/04 0.0m 001
2004 Fairchild Semiconductor Corporation