TOSHIBA TA1383AFG

TA1383AFG
TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic
TA1383AFG
NTSC Chroma Decoder, Multi-Point Scan Sync Processor,
H/V Frequency Counter IC for Color TV
TA1383AFG integrates an NTSC chroma decoder, multi-point
scan sync processor (equivalent to pin D4), and H/V frequency
counter in a 30-pin flat package. The IC is ideal for double scan
TVs.
The baseband signal processing block incorporates sub
adjustment circuits and a RGB/Y color difference matrix. The
sync processor block supports 525I/P, 750P, and 1125I.
TA1383AFG incorporates the I2C bus. The device can control
various functions via the bus line.
Weight: 0.63 g (typ.)
Features
Luminance block
• Chroma trap
•
Y delay line
Chroma block
• NTSC decoder
•
TOF
Baseband block
• Sub contrast
•
Sub tint
•
Sub color
•
Y delay line
•
Offset adjustment
•
ADC pre-filter (LPF)
•
+6dB amp (ON/OFF)
•
YCbCr/YPbPr/RGB input supported
•
YCbCr/YPbPr output switchable
Sync block
• High-performance sync separator (at NTSC (525I) )
•
Horizontal sync (15.734 k, 31.5 k, 33.75 k, 45 kHz)
•
Vertical sync playback function (525I/P, 750P, 1125I)
•
2- and 3-level sync separator circuit
•
HD/VD input (positive and negative polarities)
•
HD/VD output (positive and negative polarities switchable)
•
Horizontal/vertical frequency counting function
•
Copy guard
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TA1383AFG
TEST
fsc
CW
22
21
20
19
3.58
VCXO
APC
C
SW
DEMO
TOF
ACC
C1 IN
23
HD OUT
24
DIGITAL GND
25
C2 IN
26
APC FILTER
27
3.58 X’tal
28
Cr/Pr OUT
Cb/Pb OUT
CLAMP
Y OUT
CLAMP
VCC2 (5 V)
CLAMP
fsc OUT
29
GND2
Cb/Pb/B IN
30
Cr/Pr/R IN
D-SYNC1/Y3/G IN
Block Diagram
18
17
16
HD OUT
SW
TEST
U
SW
V
YUV MATRIX
V
U
LPF
SUB-CONT
/AMP
SUB-COLOR
/AMP
OFFSET
OFFSET
HD
PHASE
Y
Y-DL1
LPF
YCbCr/
YPbPr
MATRIX
SUB TINT
INTEG
H/V-FREQ
COUNTER
SW
HD (RGB MODE)
NTSC
SYNC SEPA
NOISE
DET
525i: 8fH
OTHERS:2fH
V SW
H-RAMP
SYNC
SEPA
H-AFC
1
2
3
4
5
6
7
SYNC OUT
Y2/SYNC2 IN
VD IN
D-SYNC2 IN
(for freq. det.)
HD IN
SYNC TIP
CLAMP
2
I C BUS
MONITOR
OUT
2
VCO
8
9
10
11
12
13
14
15
VD OUT
SYNC TIP
CLAMP
SCL
SYNC
OUT
H-C/D
SDA
SYNC TIP
CLAMP
Y1/SYNC1 IN
PULSE
REMAKE
VCC1 (9 V)
PULSE
REMAKE
ADDRESS
Y SW
525i
GND1
SYNC
SW
VD OUT
SW
V-C/D
HVCO
C
TRAP
TEST
H SW
AFC FILTER
525p
750p
1125i
H/
V-SEPA
MONITOR OUT
Y-DL2
2005-09-05
TA1383AFG
Pins (unless otherwise specified, VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C)
Pin
No.
1
Symbol
VCC1 (9 V)
Function
Interface
I/O Signal
⎯
⎯
VCC for sync separation block,
outputs, and interface. Connects 9 V
(typ.).
Y signal input pin.
30 kΩ
9 pF
1 Vp-p (with Sync)
1
Inputs NTSC (525I) signal via clamp
capacitor.
Sync signal is separated from Y signal
input to this pin.
1 kΩ
Y2/SYNC2 IN
2
4
1 kΩ
1 kΩ
Can also be used for sync-only input
pins.
When not used, leave open.
1 kΩ
2V
Y1/SYNC1 IN
4
1 kΩ
5 µA
2
Sync-Tip: 2.0 V
11
1
3
SYNC OUT
100 Ω
Outputs sync-separated C-SYNC.
Open collector output.
High/Low
3
11
25 µA
1
Th: 0.7 V
Inputs vertical sync VD signal.
VD IN
Inputs positive- and negative-polarity
signals.
or
1 kΩ
5
45 kΩ
When not used, leave open.
1.5 V
5
Th: 0.7 V
11
1 Vp-p (with Sync)
Sync-Tip: 2.0 V
1
D-SYNC2 IN
(for freq. det.)
Inputs Y signals such as 525IP, 720P,
and 1125I via clamp capacitor.
1 kΩ
6
1 kΩ
6
1 kΩ
Inputs Y signal for identifying
frequency.
When not used, leave open.
or
11
1
Th: 0.7 V
Inputs horizontal sync HD signal.
HD IN
Inputs positive- and negative-polarity
signals.
When not used, leave open.
500 Ω
or
7
50 kΩ
7
Th: 0.7 V
11
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2005-09-05
TA1383AFG
Pin
No.
Symbol
Function
Interface
I/O Signal
500 Ω
1
Monitor output pin.
8
MONITOR OUT
Emitter follower output.
500 Ω
⎯
8
5 kΩ
Selects output signal according to bus
setting.
11
1
Connects horizontal AFC filter.
Voltage of this pin determines
horizontal output frequency.
300 Ω
9
⎯
36 kΩ
AFC FILTER
6.3 V
9
11
1
Connects ceramic oscillator for
horizontal oscillation.
4 kΩ
HVCO
Use Murata CSBLA503KECZF30 or
CSBFB503KJCZF60.
⎯
1 kΩ
2 kΩ
10
1 kΩ
10
10 kΩ
11
11
GND1
⎯
GND pin for 9-V block.
⎯
Switches slave addresses. Slave
addresses are set according to
voltage of this pin.
12
ADDRESS
VCC (9 V): DEH/DFH
7.5 V
1 kΩ
4.5 V
12
1.5 V
6 V: DCH/DDH
3 V: DAH/DBH
GND: D8H/D9H
30 kΩ 60 kΩ 60 kΩ 15 kΩ
1
VCC: DEH/DFH
6 V: DCH/DDH
3 V: DAH/DBH
GND: D8H/D9H
VCC (9 V)
7.5 V
4.5 V
1.5 V
GND
11
1
SDA
2
I C bus SDA pin.
50 Ω
5 kΩ
SDA
13
⎯
2.25 V
13
ACK
11
1
SCL
2
I C bus SCL pin.
5 kΩ
14
SCL
⎯
2.25 V
14
11
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TA1383AFG
Pin
No.
Symbol
Function
Interface
I/O Signal
500 Ω
1
Vertical sync VD output pin.
Emitter follower output.
or
15
Sets polarity of output signal
according to bus setting.
5 kΩ
VD OUT
50 kΩ 50 kΩ
15
11
25
16
19
C2 IN
Burst: 300 mVp-p
1 kΩ
1 kΩ
19
When not used, leave open.
18 kΩ
C1 IN
18 kΩ
16
Inputs chroma signal via clamp
capacitor.
27
500 Ω
1
Horizontal sync HD output pin.
Emitter follower output.
or
17
Sets polarity of output signal
according to bus setting.
5 kΩ
HD OUT
50 kΩ 50 kΩ
17
11
⎯
GND pin for digital block.
25
1 kΩ
⎯
20
3 kΩ
Connects APC filter for chroma
demodulation.
2.4 V
APC FILTER
APC
Del
2 kΩ
20
⎯
2.4 V
DIGITAL GND
1.8 kΩ
18
27
21
3.58 MHz X’tal
Connects recommended 3.58-MHz
oscillator for chroma demodulation.
2.5 kΩ
25
21
⎯
500 Ω
27
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TA1383AFG
Pin
No.
Symbol
Function
Interface
I/O Signal
1
Output Y, Cb, and Cr, or Y, Pb, and Pr
signals.
23
Cb/Pb OUT
Emitter follower output.
24
Y OUT
Set output format and amplitude
according to bus setting.
500 Ω
Cr/Pr OUT
Cb/Pb
22
23
24
2 mA
22
Cr/Pr
Y
11
25
VCC2 (5 V)
VCC for Y, chroma, and baseband
processing block. Connects 5 V (typ.).
⎯
⎯
200 Ω
25
200 Ω
fsc carrier wave (CW) output pin.
26
CW OUT
Emitter follower output.
AC: 600 mVp-p
Color: 3.0 V
26
1 mA
B/W: 1.3 V
27
27
GND2
⎯
GND pin for 5-V block
⎯
1
700 mVp-p
Cr/Pr/R IN
29
Cb/Pb/B IN
Set input format according to bus
setting.
28
29
Cr/Pr
1 kΩ
1 kΩ
28
1 kΩ
Inputs 525I/P, 1125I, and 750P
Cr/Pr/R and Cb/Pb/B signal via clamp
capacitor.
Cb/Pb
2.3 V
When not used, connect 0.1 µF
between this pin and GND.
11
1
Inputs 525I/P, 750P, and 1125I Y
signal or G signal via clamp capacitor.
30
Y
1 kΩ
2V
2.3 V
When not used, connect 0.1 µF
between this pin and GND.
5 µA
1 kΩ
1 kΩ
Set input format according to bus
setting.
1 kΩ
Sync signal is separated from Y (G)
signal input to this pin.
1 kΩ
D-SYNC1/Y3/G
IN
1 kΩ
30
1 Vp-p (with Sync)
11
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TA1383AFG
Bus Control Map
Write Data
Slave Address: D8/DA/DC/DEH
SA
D7
00
READ SW
01
D6
D5
525I-SEP
04
GAIN SW
D2
V-SEP LVL
HD-POL
VD-POL
V-MODE
C-TRAP
TOF f0
TOF Q
SUB-TINT
08
TEST
HD POSI
SUB-COLOR
07
AFC-RAN
MONITOR
BANDWIDTH
SUB-CONT
06
D0
D-SY2 SEP LVL
NOISE LVL
MATRIX SW
05
D1
H/V FREQ
H-SEP LVL
AFC-MODE
03
D3
INPUT SW
FREQ DET SW
02
D4
Y-DL1
Y-DL2
Y BLACK ADJ
Preset
1000
0000
1000
0000
1000
0000
1000
0000
1000
0000
1000
0000
1000
0000
1000
0000
1000
0000
09
Cr BLACK ADJ
1000
0000
0A
Cb BLACK ADJ
1000
0000
Note 1: SA: Sub-Address
Read Data
Slave Address: D9/DB/DD/DFH
Read Mode 1 (read SW = 1)
D7
D6
D5
D4
D3
D2
D1
D0
0
POR
COLOR
C-GUARD
N-DET
V-STD
H-LOCK
HD-OUT
VD-OUT
1
SYNC-IN
Y1/2-IN
Y3-IN
D-SYNC2
H-STAB
V-SYNC
ACC
V-SKEW
D5
D4
D3
D2
D1
D0
Read Mode 2 (read SW = 0)
D7
0
1
C-SYNC
D6
V FREQUENCY DET
H FREQUENCY DET
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TA1383AFG
Bus Control Functions
Write Function
Signal
READ SW
Function
Switches Read Mode.
Switches Read Mode.
Power-On Initial Value
Self diagnosis
0: READ MODE 2 (counts frequency)
1: READ MODE 1 (self diagnosis)
(1)
Switches luminance, chroma, and sync signals.
INPUT SW
000: SYNC1/Y1/C1
001: SYNC2/Y1/C1
010: SYNC2/Y2/C2
011: SYNC2/Y3/CbCr (PbPr)
100: D-SYNC1/Y3/CbCr (PbPr)
101: D-SYNC1/RGB
110: HD/VD/Y3/CbCr (PbPr)
111: HD/VD/RGB
SYNC1/Y1/C1
(000)
Switches horizontal oscillation frequency and vertical pull-in range.
000: Horizontal oscillation frequency 15.734 kHz, vertical pull-in range
224.5H to 297H (262.5H at quiescent)
001: Horizontal oscillation frequency 31.5 kHz, vertical pull-in range 48H to
612H (525H at quiescent)
010: Horizontal oscillation frequency 33.75 kHz, vertical pull-in range 48H to
636H (562.5H at quiescent)
011: Horizontal oscillation frequency 45 kHz, vertical pull-in range 48H to
848H (750H at quiescent)
100: Horizontal oscillation frequency 15.734 kHz, forced vertical pull-in
range 262.5H
101: Horizontal oscillation frequency 15.734 kHz, vertical pull-in range
32.5H to 297H (at multi-windows)
H/V FREQ
110: D5 (1125P/60 Hz) input mode (H: 33.75 kHz Free-run, V: 48H to
636H)
Internal clamping pulse, internal H-BLK and HD output are generated
by inputted sync.
When no-signal inputted, the clamp pulse, the H-BLK and VD output
are switched to free-run signals of 33.75 kHz/562.5H. And then, HD
output is gone.
Set AFC-Mode = (111) and INPUT SW = (100), when this mode used.
H: 15.734 kHz
V: 224.5H to 297H
(000)
111: RGB Input Mode (H frequency 33.75 kHz Free-run, V pull-in range
48H to 740H)
Input HD signal is used as clamp pulse. HD/VD-OUT outputs are
remade of input signals. (H-pull-in range: 5.7 kHz to 120 kHz, V-pull-in
range: 47 Hz to 688 Hz, HD input width: 0.2 µs to 10 µs, VD input
width: 3 µs to 1.45 ms)
When no-signal inputted, the clamp pulse, the H-BLK and VD output
are switched to free-run signals of 33.75 kHz/562.5 H. And then, HD
output is gone.
Set AFC-Mode = (111) and INPUT SW = (111), when this mode used.
In this mode, when TEST = 01, V-pull-in range becomes 0 to 688 Hz.
Then, VD output is gone when no-input.
AFC-RAN
Switches horizontal AFC pull-in range.
Switches pull-in range of 525I/P, 750P, and 1125I horizontal frequencies.
0: NORMAL
NORMAL
(0)
1: Narrow
Switches frequency counting input.
Switches input pin for counting frequency.
00: 525I1 (rejects pulse of 1.75 µs or less.) (pins 2, 4, and 30)
01: 525I2 (inputs H-sync for AFC. (and rejects pulse of 0.3 µs or less.) )
(pins 2, 4, and 30)
FREQ DET SW
10: D-SYNC2 (pin 6)
D-SYNC2
(10)
11: HD/VD (pins 5 and 7)
Note: To count frequency, use Bus Mode (10/11). However, note that in Bus
Mode (00/01), frequencies such as 525P, 750P, and 1125I cannot be
counted. In this mode (00/01), frequencies may not be counted accurately
due to weak electric fields or ghosts.
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TA1383AFG
Signal
Function
Power-On Initial Value
Switches sync separation level of horizontal sync signal.
Switches sync separation level of horizontal sync signal input to sync input
pins.
H-SEP LVL
At 525I
00: 20% 01: 27% 10: 34% 11: 40%
At 525P
00: 20% 01: 30% 10: 40% 11: 50%
20%
(00)
Three-level sync 00: 25% 01: 35% 10: 45% 11: 55%
Switches sync separation level of vertical sync signal.
Switches sync separation level of vertical sync signal input to sync input pins.
40%
V-SEP LVL
At 525I
00: 40% 01: 50%
10: 60% 11: 70%
At 525P
00: 20% 01: 30%
10: 40% 11: 50%
Three-level sync
00: 25% 01: 35%
10: 45% 11: 55%
Switches sync separation level of D-SYNC2 IN (pin 6).
D-SY2 SEP LVL
Switches sync separation level of sync signal input to pin 6.
00: 20% 01: 30% 10: 40%
(00)
20%
(00)
11: 50%
Switches AFC gain.
Switches AFC gain setting mode.
000: AUTO1 (normal: 0dB, at skew: +6dB, at noise: −12dB)
001: AUTO2 (AUTO1 + prevention against AFC disoperation at noise +
stabilization of AFC in weak electric field + ghost prevention)
010: AUTO3 (Video input mode: AUTO2 + 0dB at V-SKEW detected)
AFC-MODE
011: AUTO4 (RF input mode: AUTO2 + 0dB at V-SKEW detected, however,
−12dB at normal. Also, AFC gain is not controlled by noise detection
result)
Forced +6dB
(100)
100: Forced +6dB
101: Forced 0dB
110: Forced −12dB
111: Forced Off (horizontal free running)
Note: Set AUTO1 to 4 according to input signal status.
Switches noise detection level.
NOISE LVL
Switches noise detection level. Noise is detected only in NTSC signals (525I).
Noise detection result is reflected in BUS READ and AFC-GAIN operation (as
in AUTO1 to 3 modes).
00: max
max
(00)
11: min
Switches MONITOR output.
Switches signal output from MONITOR OUT (pin 8).
Field identification output is valid for 525I and 1125I standard signal.
000: 1-bit DAC output (high)
001: 1-bit DAC output (low)
MONITOR
DAC HIGH
010: Field identification output (ODD: low, EVEN: high)
(000)
011: Noise detection output
100: V sync separation output at 525I
101: Skew detection output
110: Clamp pulse output
111: H/V-SYNC at D-SYNC2 input
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TA1383AFG
Signal
Function
Power-On Initial Value
Switches 525I SEP Mode
Switches H-SEP Mode. (Countermeasure ghost signal)
525I-SEP
0: ON
Automatically controls that H-SEP level does not go higher than V-SEP
level, the initial value is 40%.
(1)
OFF
1: OFF
Switches matrix.
Sets I/O signal format for input pins (28, 29, and 30) and output pins (22, 23,
and 24).
00: MODE-1 (YC1/YC2 → YCbCr, Y3/CbCr → YCbCr, RGB → YCbCr)
MATRIX SW
01: MODE-2 (YC1/YC2 → YCbCr, Y3/PbPr → YCbCr, RGB → YCbCr)
(00)
10: MODE-3 (YC1/YC2 → YPbPr, Y3/CbCr → YPbPr, RGB → YPbPr)
11: MODE-4 (YC1/YC2 → YPbPr, Y3/PbPr → YPbPr, RGB → YPbPr)
Note: Set this function together with INPUT SW, H/V FREQUENCY for each
input signal.
Switches bandwidth limiting filter (ADC pre-filter).
Sets bandwidth of bandwidth limiting filter and image mute.
BANDWIDTH
00: OFF (through)
OFF
01: Filter 1 (Y: 10.3 MHz/−3dB, Cb/Cr: 4.2 MHz/−3dB)
(00)
10: Filter 2 (Y: 14.6 MHz/−3dB, Cb/Cr: 6.5 MHz/−3dB)
11: Image mute (Y: −20IRE, CbCr: 0IRE)
Switches vertical sync playback mode.
Switches VD OUT (pin 15) sync playback mode.
0: PLL Mode for standard signals
V-MODE
1: Direct Sync Mode
Note 1: Setting 0 is valid only for standard signals. For other signals, set to Direct
Sync Mode.
In PLL Mode for standard signals, VD output starts with 4-µs delay in
relation to V-SYNC.
For other signals, 0.25-H delay.
PLL for standard
signals
(0)
Note 2: Set this register to (1) except inputting the NTSC and 525I composite
sync format.
TEST
Shipment Test Mode. When TEST = 01 and H/V FREQ = 111, V-pull-in range is
expanded (Refer to H/V FREQ function explanation). In other case, set to 00.
(00)
Switches output gain.
0dB
GAIN SW
Sets output amp gain for pins 22, 23, and 24.
0: +6dB
Switches HD output polarity.
HD-POL
Positive polarity
Sets HD OUT (pin 17) polarity.
0: Positive polarity
(0)
1: Negative polarity
Switches VD output polarity.
VD-POL
Positive polarity
Sets VD OUT (pin 15) polarity.
0: Positive polarity
(0)
1: Negative polarity
Switches chroma trap.
C-TRAP
(1)
1: 0dB
OFF
Switches chroma trap for image signals input to pins 2 and 4.
(0)
0: OFF
1: ON
Adjusts HD output phase.
Sets output phase of HD OUT (pin 17).
HD POSI
0000: 800 ns (2.7% of H cycle) ahead of sync center
(0000)
1111: Sync center
Note: Sync center is based on 33.75 kHz/3-level sync.
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TA1383AFG
Signal
Function
Power-On Initial Value
Adjusts subcontrast.
SUB-CONT
CENTER
Adjusts amplitude of output Y signal (pin 24).
00000: min (−3dB)
(10000)
11111: max (+3dB)
Switches TOF center frequency.
Controls center frequency of chroma filter for chroma signals input to pins 16
and 19.
TOF f0
000: OFF
001: min (0.56 fsc)
(000)
111: max (1.05 fsc)
Adjusts sub color.
SUB-COLOR
OFF
CENTER
Adjusts amplitude of output Cb/Cr (Pb/Pr) signals (pins 22 and 23).
00000: min (−3dB)
(10000)
11111: max (+3dB)
Switches TOF Q characteristic.
Controls center frequency of chroma filter for chroma signals input to pins 16
and 19.
TOF Q
000: min (0.6)
min
(000)
111: max (1.2)
Adjusts sub tint.
CENTER
SUB-TINT
Adjusts tint for output Cb/Cr (Pb/Pr) signals (pins 22 and 23).
0000: min (−7 deg)
(1000)
1111: max (+7 deg)
Adjusts Y delay time 1 (baseband block).
Switches delay amount of Y signal in baseband block.
Y-DL1
00: −10 ns
01: 0 ns
10: +10 ns
11: +10 ns
−10 ns
(00)
Note: Sets delay amount according to settings such as BANDWIDTH.
Adjusts Y delay time 2 (NTSC Y processing block).
Switches delay amount of Y signal in NTSC Y processing block.
Y-DL2
00: OFF
01: +40 ns
10: +80 ns
11: +120 ns
OFF
(00)
Note: Sets delay amount according to settings such as TOF f0/Q.
Adjusts Y black level.
Y BLACK ADJ
Adjusts black level offset of Y OUT (pin 24).
CENTER
00000000: OFF
00000001: min (−140 mV)
(10000000)
11111111: max (+140 mV)
Adjusts Cb (Pb) black level.
Cb BLACK ADJ
Adjusts black level offset of Cb (Pb) OUT (pin 23).
00000000: OFF
00000001: min (−140 mV)
CENTER
(10000000)
11111111: max (+140 mV)
Adjusts Cr (Pr) black level.
Adjusts black level offset of Cr (Pr) OUT (pin 22).
CENTER
Cr BLACK ADJ
00000000: OFF
00000001: min (−140 mV)
(10000000)
11111111: max (+140 mV)
Read Function
Signal
Function
Power-on reset
POR
0: RESISTER PRESET
1: NORMAL
After power on, 0 is returned at first read; 1, at second and subsequent reads.
Detects NTSC color or BW (Black and White).
COLOR
0: BW
1: NTSC color
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TA1383AFG
Signal
Function
Detects copy guard (pseudo SYNC).
C-GUARD
0: No copy guard detected
1: Copy guard detected
Detects whether input signal has copy-guard signal in the systems of 60-Hz 525 I/P, 60-Hz 1125 I, and
60-Hz 750 P, but does not detect copy-guard of HD/VD input signal.
Detects noise.
N-DET
0: Small amount detected
1: Large amount detected
Set noise detection level in NOISE LEVEL.
N-DET is detected only when 525I Y or CVBS signal is input.
Detects NTSC standard/non-standard.
V-STD
0: Standard detected
1: Non-standard detected
Detects vertical-sync-signal input in standard cycle. V-STD is detected only when 525I Y or CVBS
signal is input.
Detects H-LOCK.
0: Unlock detected
H-LOCK
1: Lock detected
Detects lock/unlock of input signal and H-AFC.
H-LOCK is detected in the systems of 60-Hz 525 I/P, 60-Hz 1125 I, and 60-Hz 750 P.
Note: This register may show UN-LOCK, when H-SYNC width of 525I Y or CVBS input is narrow.
HD-OUT
Detects HD-OUT (pin 17) self-diagnosis.
0: NG (no signal)
1: OK (signal detected)
Detects VD-OUT (pin 15) self-diagnosis.
VD-OUT
0: NG (no signal)
1: OK (signal detected)
Detects SYNC IN (pins 2 and 4 or 30) self-diagnosis.
SYNC-IN
0: NG (no signal)
1: OK (signal detected)
At small signal, NG.
Detects Y1/2 IN (pin 2 or 4) self-diagnosis.
Y1/2-IN
0: NG (no signal)
1: OK (signal detected)
At small signal, NG.
Detects Y3 IN (pin 30) self-diagnosis.
Y3-IN
0: NG (no signal)
1: OK (signal detected)
At small signal, NG.
Detects D-SYNC2 IN (pin 6) self-diagnosis.
D-SYNC2
0: NG (no signal)
1: OK (signal detected)
At small signal, NG.
Detects stability of horizontal signal.
H-STAB
0: Stable
1: Not stable
Determines not stable when fluctuation of horizontal signal is detected within one field.
H-STAB is detected only when 525I Y or CVBS signal is input.
Detects vertical sync of input signal.
V-SYNC
0: No vertical sync detected
1: Vertical sync detected
Detects whether input signal has vertical sync.
V-SYNC is detected in the systems of 60-Hz 525 I/P, 60-Hz 1125 I, and 60-Hz 750 P.
Detects status of automatic color control (ACC) circuit.
ACC
0: Maximum
1: Other
ACC is detected only when NTSC signal is input.
12
2005-09-05
TA1383AFG
Signal
Function
Detects vertical skew of VCR.
V-SKEW
0: no skew
1: skew
V-SKEW is detected only when NTSC signal is input.
Detects 2-/3-level sync of D-SYNC2 IN (pin 6).
0: 2-level sync
C-SYNC
1: 3-level sync
Detects sync width per 1H.
Note: If 525I/P 60-Hz signal has half SYNC width or less, 3-level sync may be determined.
Counts vertical frequency of signal selected by FREQ DET SW.
0000000 to 0011100: No VD
0011101: Vicinity of 195 Hz
1111111: Vicinity of 44.6 Hz
How to calculate vertical frequency (X);
V FREQUENCY DET
Converts data read from V-FREQ DET into decimal value and calls value Y. Z = 176.54 µs.
Vertical frequency (X) = 1 ÷ (Y × Z) [Hz]
Vertical frequency error is Y = −1 to +1. When vertical frequency is 195 Hz or more, frequency cannot be
counted accurately. Note that time constant used to integrate C.SYNC then separate V-SYNC is 9 µs
(error ±1 µs).
Data read first time after power on are undefined.
Counts horizontal frequency of signal selected by FREQ DET SW.
00000000: Quiescent
11111111: 120 kHz or more
How to calculate horizontal frequency (X);
X, Y, and Z are defined the same as those for vertical frequency.
Horizontal frequency (X) = Y ÷ (12 × Z)
H FREQUENCY DET
[kHz]
Horizontal frequency error is Y = −1 to +2. When horizontal frequency is 120 kHz or more, frequency
cannot be counted accurately. When horizontal frequency is approx. 142 kHz to approx. 200 kHz, data are
read as 00000000 by the timing of counting.
When V-SYNC or VD is not input, horizontal frequency cannot be counted. Data are read as 00000000.
Data read first time after power on are undefined.
Note 1: To count horizontal or vertical frequency, data are read between the first V-SYNC/VD and the second
V-SYNC/VD following the reset pulse generated at the second byte as the start trigger. To stabilize data, set
the bus read interval to 3 V or longer. Discard the data read the first time because they are undefined.
However the frequency is counted when BUS is read at Read Mode 1. Therefore the data that is BUS read
at Read Mode 2 is valid.
Note 2: Even when Read Mode 1 is switched to Read Mode 2, set the BUS read interval to 3 V or longer.
Figures of BUS read interval at Read Mode 2
Data 1 and
Start trigger 2
Start trigger 1
Read Timing
Data 2 and
Start trigger 3
More than 3 V
V-SYNC or VD
Counting period 1
(to data 1)
Counting period 2
(to data 2)
Figures of BUS read interval at Read Mode 2
Note 3: Though there is no restriction for setting BUS read interval at Read Mode 1, set the interval to 1 V per one
period at shortest to read the data accurately.
Decision algorithm (detection range, detection times and so on) for H/V frequency detection should be
determined under consideration of forward Notes and the other factors such as signal strength, existence of
ghost signal, APC stability, I2C BUS data transmission and so on via prototype TV set evaluation.
13
2005-09-05
TA1383AFG
2
How To Start I C Bus
After power on, TA1383FG pins 28 and 29 (Cr/Pr/R IN, Cb/Pb/B IN) are in Full-Field Clamp Mode.
Full-Field Clamp Mode is released by writing or reading. And then, clamp is performed only during the
clamp pulse period.
Described below is how to send bus data after power on. Use software to handle the procedure.
1. Turn power on.
2. Transmit all write data.
2
How To Transmit/Receive Via I C Bus
Slave Address: Can Be Changed Using Pin 12. (VCC1 = 9 V, VCC2 = 5 V)
Pin 12-GND (GND to 1.2 V): D8H/D9H
Pin 12-3 V (1.8 to 4.2 V): DAH/DBH
A6
A5
A4
A3
A2
A1
A0
W/R
A6
A5
A4
A3
A2
A1
A0
W/R
1
1
0
1
1
0
0
0/1
1
1
0
1
1
0
1
0/1
Pin 12-6 V (4.8 to 7.2 V): DCH/DDH
Pin 12-VCC1 (7.8 to VCC1) DEH/DFH
A6
A5
A4
A3
A2
A1
A0
W/R
A6
A5
A4
A3
A2
A1
A0
W/R
1
1
0
1
1
1
0
0/1
1
1
0
1
1
1
1
0/1
Start and Stop Conditions
SDA
SCL
S
P
Start condition
Stop condition
Bit Transmission
SDA
SCL
SDA must not be changed
SDA may be changed
Acknowledgement
SDA from
transmitter
High impedance at bit 9
SDA from receiver
Low impedance at bit
9 only
SCL from master
1
8
9
S
Clock pulse for acknowledgement
14
2005-09-05
TA1383AFG
Data Transmit Format 1
S
Slave address
7-bit
0 A
MSB
Sub address
8-bit
A
MSB
S: Start condition
Transmit data
8-bit
A P
MSB
A: Acknowledgement
P: End condition
Data Transmit Format 2
S
Slave address
0 A
Sub address
･･････
A
Transmit data 1
Sub address
A
A
･･････
Transmit data n
A P
Data Receive Format
S
Slave address
7-bit
1 A
Receive data 1
8-bit
Receive data 2
A P
MSB
MSB
MSB
A
To receive data, the master transmitter changes to the receiver immediately after the first
acknowledgement. The slave receiver changes to the transmitter.
The end condition is always created by the master.
Optional Data Transmit Format
Auto Increment Mode 1
S
Slave address
7- bit
0 A 1
MSB
Sub address
7-bit
A
Transmit data
8-bit
MSB
MSB
Auto Increment Mode 2
S
Slave address
7-bit
MSB
0 A 1
MSB
Sub address
7-bit
A
Transmit data 1
8-bit
MSB
････
Transmit data n
8-bit
A P
MSB
In this way, sub addresses are automatically incremented from the specified sub address and data are
set.
15
2005-09-05
TA1383AFG
I2C BUS Conditions
Characteristics
Symbol
Min
Typ.
Max
Unit
Low level input voltage
VIL
0
⎯
1.0
V
High level input voltage
VIH
1.8
⎯
Vcc
V
VOL1
0
⎯
0.4
V
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Ii
−10
⎯
10
µA
Capacitance for each I/O pin
Ci
⎯
⎯
10
pF
Low level output voltage at 3 mA sink current
fSCL
0
⎯
100
kHz
tHD;STA
4.0
⎯
⎯
µs
Low period of SCL clock
tLOW
4.7
⎯
⎯
µs
High period of SCL clock
tHIGH
4.0
⎯
⎯
µs
SCL clock frequency
Hold time START condition
Set-up time for a repeated START condition
tSU;STA
4.7
⎯
⎯
µs
Data hold time
tHD;DAT
350
⎯
⎯
ns
Data set-up time
tSU;DAT
250
⎯
⎯
ns
Set-up time for STOP condition
tSU;STO
4.0
⎯
⎯
µs
tBUF
4.7
⎯
⎯
µs
Bus free time between a STOP and START condition
16
2005-09-05
TA1383AFG
Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
VCCmax
12
V
Input pin voltage
Vin
GND − 0.3 to VCC + 0.3
V
Power dissipation
PD
(Note 4)
1471
mW
Supply voltage
Power dissipation reduction rate
depending on temperature
1/θja
11.8
mW/°C
Operating temperature
Topr
−20~65
°C
Storage temperature
Tstg
−55~150
°C
Note 4: See the figure below. (the figure is based on when the IC is mounted on a board of 50 × 50 × 1.6 mm and
30% Cu area. this is the minimum board size.)
Note 5: Misoperation may be caused in the IC due to leakage from high electric fields generated by the CRT. Install
the IC at least 20 cm from the CRT. If not possible, use a shield to shield electric fields.
1000
Power dissipation
PD
(mW)
1471
0
0
25
65
Ambient temperature
Figure
150
Ta
(°C)
Power dissipation reduction curve
17
2005-09-05
TA1383AFG
Operating Conditions
Characteristic
Min
Typ.
Max
pin 1
8.5
9.0
9.5
pin 25
4.7
5.0
5.3
Y signal input amplitude
pins 2, 4, 6, 30 including sync
⎯
1.0
⎯
Vp-p
Chroma signal input amplitude
pins 16, 19 burst signal amplitude
⎯
300
⎯
mVp-p
Cb, Cr (Pb, Pr) signal input amplitude
pins 28, 29 100% color bar signal
⎯
700
⎯
mVp-p
Supply voltage (VCC)
Description
Unit
V
R, G, B signal input amplitude
pins 28, 29, 30 100% white signal
⎯
700
⎯
mVp-p
HD, VD signal amplitude
pins 5, 7
1.2
5
6
Vp-p
0.5 µs
⎯
0.2 H
⎯
0.2
⎯
10
µs
0.2 µs
⎯
0.2 H
(Note 6)
⎯
HD input width
Syncronization
Pin 7, H/V FREQ = 000 to 101
RGB mode
Pin 7, H/V FREQ = 111
Frequency detection
Pin 7
Syncronization
Pin 5, H/V FREQ = 000 to 101
3 µs
⎯
31 H
⎯
Pin 5, H/V FREQ = 111
3 µs
⎯
1.45 ms
⎯
VD input width RGB mode
3
⎯
400
µs
HD input frequency
Pin 7, H/V FREQ = 111
5.7
⎯
120
kHz
VD input frequency
Pin 5, H/V FREQ = 111
47
⎯
688
Hz
SYNC OUT input current
Pin 3
mA
Frequency detection
Address switching voltage
Pin 5
Pin 12
⎯
⎯
1.6
DE/DFH
8.25
9
9
DC/DDH
5.25
6
6.75
DA/DBH
2.25
3
3.75
V
D8/D9H
0
0
0.75
SCL/SDA pull-up voltage
Pin 13,14
2.5
5
7.5
V
SDA input current
Pin 13
⎯
⎯
2
mA
Note 6: The ratio of H-cycle for HD input for frequency detection.
Electrical Characteristics
(unless otherwise specified, VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C ± 3°C, bus data: preset
values)
Current Dissipation
Symbol
Test
Circuit
Min
Typ.
Max
Unit
VCC1 (9 V)
ICC1
⎯
29.3
36.5
44.4
mA
VCC2 (5 V)
ICC2
⎯
52.9
66.0
80.2
mA
Pin Name
Pin Voltage
Pin
No.
Pin Name
Symbol
Test
Circuit
Min
Typ.
Max
Unit
2
Y1/SYNC1 IN
V2
⎯
1.7
2.0
2.3
V
4
Y2/SYNC2 IN
V4
⎯
1.7
2.0
2.3
V
22
Cr/Pr OUT
V22
⎯
3.15
3.50
3.85
V
23
Cb/Pb OUT
V23
⎯
3.15
3.50
3.85
V
24
Y OUT
V24
⎯
2.85
3.20
3.55
V
28
Cr/Pr/R IN
V28
⎯
2.0
2.3
2.6
V
29
Cb/Pb/B IN
V29
⎯
2.0
2.3
2.6
V
30
YD-SYNC1/Y3/G IN
V30
⎯
1.7
2.0
2.3
V
18
2005-09-05
TA1383AFG
Y/Cb/Cr Block
Characteristics
I/O gain 2
(YPbPr → YCbCr)
I/O gain 3
(YCbCr → YPbPr)
I/O gain 4
(YPbPr → YPbPr)
I/O gain 5
(RGB → YCbCr)
⎯
VDY30
Max
Pins 2, and 4
1.35
1.50
1.65
⎯
Pins 30
1.26
1.40
1.54
VDCb
⎯
Pin 28
1.0
⎯
⎯
VDCr
⎯
Pin 29
1.0
⎯
⎯
GCT
⎯
fsc attenuation
⎯
⎯
−20
(00)
YDY100
⎯
SA07H: 80H
−17
−10
−5
(01)
YDY101
⎯
SA07H: 84H
−5
0
5
(10)
YDY110
⎯
SA07H: 88H
7
10
13
(11)
YDY111
⎯
SA07H: 8CH
7
10
13
(01)
YDL2A
⎯
SA07H: 81H
30
40
55
(10)
YDL2B
⎯
SA07H: 82H
70
80
110
(11)
YDL2C
⎯
SA07H: 83H
100
120
160
−1.00
0.00
1.00
Chroma trap characteristic
I/O gain 1
(YCbCr → YCbCr)
VDY
Typ.
Color difference input dynamic range
Y delay time switching
2 (TOF block)
Test
Circuit
Min
Y input dynamic range
Y delay time switching
1 (pre-filter block)
Symbol
Test Condition
Y
GMYC
⎯
SA03H: 80H,
Between pins 30 and 24
Cb
GMBC
⎯
SA03H: 80H,
Between pins 29 and 23
−1.00
0.00
1.00
Cr
GMRC
⎯
SA03H: 80H,
Between pins 28 and 22
−1.00
0.00
1.00
Y
GMYC1
⎯
−1.00
0.00
1.00
B→Y
GMBC1
⎯
−21.4
−19.9
−18.4
B→B
GMBC2
⎯
−1.1
−0.1
0.9
B→R
GMBC3
⎯
−25.5
−24.0
−22.5
R→Y
GMRC1
⎯
−14.1
−13.1
−12.1
R→B
GMRC2
⎯
−21.1
−19.1
−17.6
R→R
GMRC3
⎯
−1.2
−0.2
0.9
Y
GMYP1
⎯
−1.00
0.00
1.00
B→Y
GMBP1
⎯
−20.0
−18.5
−17.0
B→B
GMBP2
⎯
−0.8
0.2
1.2
B→R
GMBP3
⎯
−24.5
−22.5
−20.5
R→Y
GMRP1
⎯
−14.4
−13.4
−12.4
(Note Y1)
(Note Y2)
R→B
GMRP2
⎯
−20.8
−18.8
−17.3
R→R
GMRP3
⎯
−0.8
0.22
1.2
Y
GMYP
⎯
SA03H: E0H,
Between pins 30 and 24
−1.00
0.00
1.00
−1.00
0.00
1.00
−1.00
0.00
1.00
Pb
GMBP
⎯
SA03H: E0H,
Between pins 29 and 23
Pr
GMRP
⎯
SA03H: E0H,
Between pins 28 and 22
G→Y
GMGA1
⎯
−5.0
−4.0
−3.0
G→B
GMGA2
⎯
−10.6
−9.6
−8.6
G→R
GMGA3
⎯
−8.6
−7.6
−6.6
B→Y
GMBA1
⎯
−20.4
−18.9
−17.4
B→B
GMBA2
⎯
−7.0
−6.0
−5.0
B→R
GMBA3
⎯
−25.0
−23.0
−21.0
R→Y
GMRA1
⎯
−10.5
−9.5
−8.5
R→B
GMRA2
⎯
−16.5
−15.5
−14.5
R→R
GMRA3
⎯
−7.0
−6.0
−5.0
(Note Y3)
19
Unit
Vp-p
Vp-p
dB
ns
ns
dB
dB
dB
dB
dB
2005-09-05
TA1383AFG
Symbol
Test
Circuit
G→Y
GMGB1
G→B
GMGB2
G→R
Characteristics
I/O gain 6
(RGB → YPbPr)
Min
Typ.
Max
⎯
−3.1
−2.1
−1.1
⎯
−9.3
−8.3
−7.3
GMGB3
⎯
−7.9
−6.9
−5.9
B→Y
GMBB1
⎯
−22.8
−21.8
−20.8
B→B
GMBB2
⎯
−7.0
−6.0
−5.0
B→R
GMBB3
⎯
−29.0
−27.0
−25.0
R→Y
GMRB1
⎯
−13.5
−12.5
−11.5
R→B
GMRB2
⎯
−21.0
−19.0
−17.0
R→R
GMRB3
⎯
−7.0
−6.0
−5.0
GFY1
⎯
SA03H: 88H, at 11.3 MHz
−8
−4
−1
⎯
SA03H: 88H, at 16 MHz
−30
−18
−9
GFY3
⎯
SA03H: 90H, at 16 MHz
−11
−4
−1
GFY4
⎯
SA03H: 80H, at 27 MHz
−34
−26
−18
GFBR1
⎯
SA03H: 88H, at 5.65 MHz
−8
−5
−2
GFBR2
⎯
SA03H: 88H, at 16 MHz
−42
−35
−28
GFBR3
⎯
SA03H: 90H, at 8 MHz
−8
−5
−2
Filter 2
Filter 1
Pre-filter 2
(B-Y, R-Y axes)
(Note Y4)
GFY2
Filter 1
Pre-filter 1
(Y axis)
Test Condition
Filter 2
Unit
dB
dB
dB
GFBR4
⎯
SA03H: 90H, at 27 MHz
−48
−35
−26
Positive
YBMAX
⎯
SA08H: FFH, pin 24
126
140
154
Negative
YBMIN
⎯
SA08H: 01H, pin 24
−154
−140
−126
Positive
RBBMAX
⎯
SA09H/10H: FFH, pin 23/22
126
140
154
Negative
RBBMIN
⎯
SA09H/10H: 01H, pin 23/22
−154
−140
−126
Output gain switching
GGSW
⎯
SA04H: 00H/80H
5
6
7
dB
Y I/O gain (Y1/Y2 IN)
GY
⎯
Between pins 2/4 and 24
−1.0
0
1.0
dB
Y black-level range
R-Y, B-Y black-level
range
Sub contrast
characteristic
max
GSCMAX
⎯
SA05H: F8H/80H
2.0
3.0
4.0
min
GSCMIN
⎯
SA05H: 80H/00H
−4.0
−3.0
−2.0
Sub color
characteristic
max
GCLMAX
⎯
SA06H: F8H/80H
2.0
3.0
4.0
min
GCLMIN
⎯
SA06H: 80H/00H
−4.0
−3.0
−2.0
GCLT
⎯
⎯
−35
−50
⎯
max
TNTMAX
⎯
SA07H: F0H/80H
6.0
7.0
8.0
min
TNTMIN
⎯
SA70H: 80H/00H
−8.0
−7.0
−6.0
Y1/Y2
GY1IN
⎯
at 13 MHz, Input; pins 2 and 4
−2
0
2
Y3
GY3IN
⎯
at 40 MHz, Input; pin 30
−2
0
2
⎯
at 40 MHz,
Input; pins 28 and 29
−2
0
2
Input crosstalk
Tint characteristic
Frequency
characteristic
Cb/Cr
GBRIN
20
mV
mV
dB
dB
dB
°
dB
2005-09-05
TA1383AFG
Chroma Block
Characteristics
ACC characteristic
Test
Circuit
F601
F301
F31
⎯
F11
Typ.
Max
⎯
280
330
380
⎯
280
330
380
270
320
370
⎯
115
130
145
(Note CH1)
A1
⎯
0.85
1.00
1.15
⎯
600
720
840
R
VRO
⎯
600
705
840
RRB
⎯
0.93
1
1.15
B
θB
⎯
⎯
−3
0
3
R
θR
⎯
⎯
87
90
93
θBR
⎯
⎯
86
90
93
Killer OFF
VCI
⎯
4.0
5.4
10.0
Killer ON
VBI
⎯
3.5
4.6
6.0
f03
⎯
Demodulation angle
Color difference output relative phase
Free-running frequency
100% color bar
100% color bar, Cb/Cr
mVp-p
⎯
mVp-p
⎯
°
(Note CH2)
Pins 16 and 19: AC GND
Unit
°
mV
3.579345 3.579545 3.579745
MHz
βf
⎯
0.5
1.0
1.5
Hold +
f3HH
⎯
Upper hold range
250
500
2000
Pull-in +
f3PH
⎯
Upper pull-in range
250
500
2000
Hold −
f3HL
⎯
Lower hold range
−2000
−500
−250
Pull-in −
f3PL
⎯
Lower pull-in range
−2000
−500
−250
Vfsc
⎯
Pin 26
400
600
720
High
V26H
⎯
Pin 26 at NTSC input
2.7
3.0
3.3
Low
V26L
⎯
Pin 26 at quiescent
1.0
1.3
1.6
VNE
⎯
Pins 22 and 23,
fsc leakage level,
when rainbow signal
(B = C = 300 mVp-p) input
⎯
⎯
4.0
mVp-p
VHNE
⎯
Pins 22 and 23,
2 × fsc leakage level
when rainbow signal
(B = C = 300 mVp-p) input
⎯
⎯
4.0
mVp-p
0 kHz
GFH
⎯
19
21
23
+500 kHz
GFC
⎯
17
19
21
−500 kHz
GFL
⎯
14
16
18
f0+
GF+
⎯
14
16
18
f0−
GF−
⎯
22.5
24.5
26.5
APC frequency control sensitivity
APC pull-in and hold
ranges
CW output amplitude
CW output DC level
Residual carrier wave level
Residual harmonic level
TOF (f0･Q) control
characteristic
Min
VBO
Color difference output relative
amplitude
TOF characteristic
Test Condition
B
Color difference
output level
Identification
sensitivity
Symbol
(Note C3H)
Hz/mV
Hz
mVp-p
V
(Note CH4)
(Note CH5)
21
dB
dB
2005-09-05
TA1383AFG
Sync Block
Symbol
Test
Circuit
SYNC1/2
SPH
⎯
D-SYNC1
DS1PH
⎯
Characteristics
SYNC IN sync phase
NTSC horizontal sync
separation level
NTSC vertical sync
separation level
1125I/60-Hz horizontal
sync separation level
1125I/60-Hz vertical
sync separation level
D-SYNC2 sync
separation level
Max
2.8
3.0
3.2
0.75
0.85
0.95
0.8
0.9
1.0
3.9
4.2
4.6
1.4
1.6
1.8
1.3
1.5
1.7
HDPH
⎯
⎯
31.5 kHz
Wd-HD1
⎯
33.75 kHz
Wd-HD2
⎯
45 kHz
Wd-HD3
⎯
1.5
1.7
1.9
00
VthH10
⎯
0.219
0.229
0.239
01
VthH11
⎯
0.199
0.209
0.219
10
VthH12
⎯
0.179
0.189
0.199
(Note SY02)
(Note SY03)
(Note SY04)
11
VthH13
⎯
0.162
0.169
0.179
00
VthV10
⎯
0.157
0.172
0.186
01
VthV11
⎯
0.129
0.143
0.157
10
VthV12
⎯
0.1
0.114
0.129
(Note SY05)
11
VthV13
⎯
0.072
0.086
0.1
00
VthH20
⎯
0.059
0.070
0.081
01
VthH21
⎯
0.080
0.091
0.102
10
VthH22
⎯
0.109
0.120
0.131
(Note SY06)
11
VthH23
⎯
0.135
0.146
0.157
00
VthV20
⎯
0.059
0.070
0.081
01
VthV21
⎯
0.080
0.091
0.102
10
VthV22
⎯
0.109
0.120
0.131
(Note SY07)
11
VthV23
⎯
0.135
0.146
0.157
00
VthD20
⎯
0.056
0.067
0.078
01
VthD21
⎯
0.086
0.097
0.108
10
VthD22
⎯
0.111
0.122
0.133
11
VthD23
⎯
0.134
0.145
0.156
VthHD
⎯
0.6
0.7
0.8
15.73 kHz-1
FA000
⎯
15.59
15.73
15.91
(Note SY08)
Pin 7
31.5 kHz
FA001
⎯
31.19
31.5
31.82
33.75 kHz-1
FA010
⎯
33.41
33.75
34.09
44.55
45
45.45
15.59
15.73
15.91
45 kHz
FA011
⎯
15.73 kHz-2
FA100
⎯
15.73 kHz-3
FA101
⎯
15.59
15.73
15.91
33.75 kHz-2
FA110
⎯
33.41
33.75
34.09
33.75 kHz-3
FA111
⎯
33.41
33.75
34.09
15.73 kHz-4
FF000
⎯
15.59
15.73
15.91
F15MIN
⎯
14.37
14.67
14.97
F15MAX
⎯
16.61
16.94
17.27
F31MIN
⎯
28.97
29.56
30.15
F31MAX
⎯
33.23
33.90
34.57
F33MIN
⎯
30.91
31.54
32.17
F33MAX
⎯
35.44
36.15
36.86
F45MIN
⎯
41.81
42.62
43.48
15.73 kHz-1
31.5 kHz
Horizontal frequency
range
Typ.
Wd-HD0
HD input threshold
Horizontal
free-running frequency
(Note SY01)
Min
15.73 kHz
HD IN horizontal sync phase
Delayed HD pulse
width
Test Condition
33.75 kHz
45 kHz
15.73 kHz-2
(Note SY09)
(Note SY10)
F45MAX
⎯
48.27
49.24
50.21
F15nMIN
⎯
14.80
15.10
15.40
F15nMAX
⎯
16.06
16.36
16.66
22
Unit
µs
µs
µs
Vp-p
Vp-p
Vp-p
Vp-p
Vp-p
V
kHz
kHz
2005-09-05
TA1383AFG
Symbol
Test
Circuit
15.73 kHz
BH1573
31.5 kHz
BH315
33.75 kHz
BH3375
⎯
45 kHz
BH45
⎯
ID1+
⎯
ID1−
⎯
Characteristics
Horizontal oscillation
control sensitivity
0dB
AFC phase detection
current
−6dB
−12dB
HD output phase and
width
Max
⎯
2.7
3.4
4.1
⎯
5.4
6.7
8.0
5.6
7.0
8.4
7.9
9.7
11.5
256
320
400
256
320
400
56
70
87.5
56
70
87.5
536
670
838
536
670
838
4.0
4.6
4.9
⎯
1
⎯
⎯
10
⎯
ID2+
⎯
⎯
ID3+
⎯
Pin 9 voltage vs horizontal
oscillation frequency
(Note SY11)
ID3−
⎯
⎯
Start
TVMASK1
⎯
Stop
TVMASK2
⎯
15.73 kHz Ph
HDS0
⎯
−1.0
−0.8
−0.6
15.73 kHz W
HDW0
⎯
4.3
4.5
4.7
31.5 kHz Ph
HDS1
⎯
−0.06
0.04
0.14
Pin 1 (VCC1)
NTSC signal,
MONITOR OUT (pin 9)
31.5 kHz W
HDW1
⎯
2.05
2.25
2.45
33.75 kHz Ph
HDS2
⎯
−0.12
−0.02
0.08
33.75 kHz W
HDW2
⎯
1.9
2.1
2.3
−0.07
0.03
0.13
(Note SY12)
Unit
kHz/V
µA
V
H
µs
45 kHz Ph
HDS3
⎯
45 kHz W
HDW3
⎯
1.4
1.6
1.8
D5 mode Ph
HDS4
⎯
0.13
0.23
0.33
D5 mode W
HDW4
⎯
1.9
2.1
2.3
RGB mode Ph
HDS5
⎯
0
0.1
0.2
RGB mode W
HDW5
⎯
2.23
2.35
2.47
High
HDVH
⎯
Pin 17: High voltage
4.9
5.1
5.3
V
Pin 17: Low voltage
V
HD output level
HDVL
⎯
0
0.1
0.3
∆HP0−
⎯
1.31
1.45
1.6
∆HP0+
⎯
1.17
1.30
1.43
∆HP1−
⎯
0.67
0.74
0.81
∆HP1+
⎯
0.59
0.65
0.72
∆HP2−
⎯
0.64
0.71
0.78
∆HP2+
⎯
0.54
0.60
0.66
∆HP3−
⎯
0.46
0.51
0.56
∆HP3+
⎯
0.41
0.45
0.50
(− ) → (+ )
HD-DUTY1
⎯
pin 7: HD input
40
45
50
(+ ) → (− )
HD-DUTY2
⎯
pin 17: Monitor
45
50
55
Low
15.73 kHz
31.5 kHz
HD output phase
adjustment range
33.75 kHz
45 kHz
HD input polarity
detection range
Typ.
VVCO
VCO oscillation start voltage
AFC phase detection
stop period
Min
ID2−
Test Condition
(Note SY13)
µs
%
23
2005-09-05
TA1383AFG
Characteristics
15.73 kHz
31.5 kHz
33.75 kHz
Clamp pulse phase
and width
45 kHz
D5 mode
RGB mode
Clamp pulse output
level
Noise detection
High
Symbol
Test
Circuit
Typ.
Max
CPS0
⎯
6.15
6.35
6.55
⎯
1.8
2
2.2
CPS1
⎯
2.85
2.95
3.05
CPW1
⎯
0.9
1
1.1
CPS2
⎯
1.85
1.95
2.05
CPW2
⎯
0.9
1.0
1.1
CPS3
⎯
1.95
2.05
2.15
CPW3
⎯
0.9
1.0
1.1
CPS4
⎯
0.75
0.85
0.95
CPW4
⎯
0.4
0.5
0.6
CPS5
⎯
0.05
0.15
0.25
CPW5
⎯
2.23
2.35
2.47
CPVH
⎯
4.7
5.0
5.3
0
0.1
0.3
(Note SY14)
pin 8, SA 02H: 86H
CPVL
⎯
00; 1 → 0
NHi00
⎯
37
50
63
01; 1 → 0
NHi01
⎯
26
35
44
10; 1 → 0
NHi10
⎯
20
27
34
11; 1 → 0
NHi11
⎯
17
23
29
00; 0 → 1
NLow00
⎯
17
23
29
01; 0 → 1
NLow01
⎯
13
18
23
10; 0 → 1
NLow10
⎯
9
14
19
11; 0 → 1
NLow11
⎯
8
12
16
High
VDACH1
⎯
Pin 8, SA02H: 80H
4.8
5
5.2
Low
VDACL0
⎯
Pin 8, SA02H: 81H
0
0.1
0.3
VthVD
⎯
Pin 5
0.6
0.75
0.9
525I-1
VDW000
⎯
451
513
575
525P
VDW001
⎯
237
270
302
1125I
VDW010
⎯
222
252
282
750P
VDW011
⎯
451
513
575
525I-2
VDW100
⎯
455
517
579
525I-3
VDW101
⎯
222
252
282
1125P
VDW110
⎯
222
252
282
525I-1
VDPh000
⎯
14.4
17.5
20.1
525P
VDPh001
⎯
6.65
7.85
9.05
1125I
VDPh010
⎯
6.15
7.25
8.35
(Note SY15)
µs
mVp-p
V
(Note SY16)
750P
VDPh011
⎯
4.85
5.72
6.6
525I-1b
VDPh000b
⎯
12
14
16
High
VDVH
⎯
Pin 15: High voltage
4.7
5.0
5.3
Low
VDVL
⎯
Pin 15: Low voltage
0
0.1
0.3
VD output level
Unit
V
Low
VD input threshold
VD output phase
Min
CPW0
DAC output voltage
VD output width
Test Condition
V
µs
µs
V
24
2005-09-05
TA1383AFG
Symbol
Test
Circuit
525I-1
FVF000
⎯
525P
FVF001
1125I
Characteristics
Vertical free-running
frequency
Test Condition
Min
Typ.
Max
Pin 15: Quiescent,
SA00H: E0H
⎯
262.5
⎯
⎯
Pin 15: Quiescent,
SA00H: E2H
⎯
525
⎯
FVF010
⎯
Pin 15: Quiescent,
SA00H: E4H
⎯
562.5
⎯
750P
FVF011
⎯
Pin 15: Quiescent,
SA00H: E6H
⎯
750
⎯
525I-2
FVF100
⎯
Pin 15: Quiescent,
SA00H: E8H
⎯
262.5
⎯
525I-3
FVF101
⎯
Pin 15: Quiescent,
SA00H: EAH
⎯
296.5
⎯
1125P
FVF110
⎯
Pin 15: Quiescent,
SA00H: ECH
⎯
562.5
⎯
RGB
FVF111
⎯
Pin 15: Quiescent,
SA00H: EEH
⎯
562.5
⎯
525I-1
FVP000
⎯
Pin 15, SA00H: 80H
224
⎯
296.5
H
525P
FVP001
⎯
Pin 15, SA00H: 82H
48.5
⎯
612
1125I
FVP010
⎯
Pin 15, SA00H: 84H
48.5
⎯
636
750P
FVP011
⎯
Pin 15, SA00H: 86H
48.5
⎯
848
525I-2
FVP100
⎯
Pin 15, SA00H: 88H
⎯
262.5
⎯
525I-3
FVP101
⎯
Pin 15, SA00H: 8AH
32
⎯
296.5
1125P
FVP110
⎯
Pin 15, SA00H: 8CH
48.5
⎯
636
RGB
FVP111
⎯
Pin 15, SA00H: EEH
48.5
⎯
740
Vertical pull-in range
25
Unit
H
2005-09-05
TA1383AFG
Test Method (unless otherwise specified, VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C ± 3°C, bus data: preset values)
Note No.
SW Mode
Characteristic
SW28
SW29
Test Method
SW30
Y/back end block
Y1
Y/back end block common test conditions
A
(1)
Write data: Transmit PREST DATA. Read data: Read DATA.
(2)
Set SA 08H/09H/10H to 00H/00H/00H.
(3)
Set SW2 to A, SW4 to A, SW6 to B, SW9 to On, SW12 to A, SW16 to A, SW19 to A, SW22 to B, SW23 to B, and
SW24 to B.
I/O gain 2
C
C
(1)
Set INPUT SW (SA 00H) to D-SYNC1/Y3/CbCr (PbPr) (C0H).
(YPbPr → YCbCr)
↓
↓
(2)
Set MATRIX SW (SA 03H) to MODE-2 (A0H).
A
A
(3)
Input sine wave A (f = 100 kHz) to IN30 and set #30 amplitude to 0.2 Vp-p.
↓
(4)
Measure #24 amplitude VMYC [V] and determine GMYC using the following equation.
(5)
Set SW29 to A, input sine wave B (f = 100 kHz) to IN29, and set #29 amplitude to 0.2 Vp-p.
(6)
Input sync signal to IN30.
(7)
Measure #24, #23, #22 amplitudes VMBC1, VMBC2, and VMBC3 [V], and determine GMBC1, GMBC2, and GMBC3
using the following equation.
GMYC = 20 × log (VMYC/0.2) [dB]
C
GMBC* = 20 × log (VMBC*/0.2) [dB]
(8)
Set SW28 to A and SW29 to C, input sine wave B (f = 100 kHz), and set #28 amplitude to 0.2 Vp-p.
(9)
Input sync signal to IN30.
(10) Measure #24, #23, #22 amplitudes VMRC1, VMRC2, and VMRC3 [V], and determine GMRC1, GMRC2, and GMRC3
using the following equation.
GMRC* = 20 × log (VMRC*/0.2) [dB]
26
2005-09-05
TA1383AFG
Note No.
Y2
SW Mode
Characteristic
Test Method
SW28
SW29
SW30
I/O gain 3
C
C
A
(1)
Set INPUT SW (SA 00H) to D-SYNC1/Y3/CbCr (PbPr) (C0H).
(YCbCr → YPbPr)
↓
↓
(2)
Set MATRIX SW (SA 03H) to MODE-3 (C0H).
A
A
(3)
Input sine wave A (f = 100 kHz) to IN30 and set #30 amplitude to 0.2 Vp-p.
↓
(4)
Measure #24 amplitude VMYP [V] and determine GMYP using the following equation.
(5)
Set SW29 to A, input sine wave B (f = 100 kHz) to IN29, and set #29 amplitude to 0.2 Vp-p.
(6)
Input sync signal to IN30.
(7)
Measure #24, #23, #22 amplitudes VMBP1, VMBP2, and VMBP3 [V], and determine GMBP1, GMBP2, and GMBP3
using the following equation.
GMYP = 20 × log (VMYP/0.2) [dB]
C
GMBP* = 20 × log (VMBP*/0.2) [dB]
(8)
Set SW28 to A and SW29 to C, input sine wave B (f = 100 kHz) to IN28, and set #28 amplitude to 0.2 Vp-p.
(9)
Input sync signal to IN30.
(10) Measure #24, #23, #22 amplitudes VMRP1, VMRP2, and VMRP3 [V], and determine GMRP1, GMRP2, and GMRP3
using the following equation.
GMRP* = 20 × log (VMRP*/0.2) [dB]
Y3
I/O gain 5
(RGB → YCbCr)
C
C
A
(1)
Set INPUT SW (SA 00H) to DSYNC1/RGB (D0H).
↓
↓
(2)
Set MATRIX SW (SA 03H) to MODE-1 (80H).
A
A
(3)
Input sine wave A (f = 100 kHz) to IN30 and set #30 amplitude to 0.2 Vp-p.
↓
(4)
Measure #24, #23, #22 amplitudes VMGA1, VMGA2, and VMGA3 [V], and determine GMGA1, GMGA2, and GMGA3
using the following equation.
C
GMGA* = 20 × log (VMGA*/0.2) [dB]
(5)
Set SW29 to A, input sine wave B (f = 100 kHz) to IN29, and set #29 amplitude to 0.2 Vp-p.
(6)
Input sync signal to IN30.
(7)
Measure #24, #23, #22 amplitudes VMBA1, VMBA2, and VMBA3 [V], and determine GMBA1, GMBA2, and GMBA3
using the following equation.
GMBA* = 20 × log (VMBA*/0.2) [dB]
(8)
Set SW28 to A and SW29 to C, input sine wave B (f = 100 kHz) to IN28, and set #28 amplitude to 0.2 Vp-p.
(9)
Input sync signal to IN30.
(10) Measure #24, #23, #22 amplitudes VMRA1, VMRA2, and VMRA3 [V], and determine GMRA1, GMRA2, and GMRA3
using the following equation.
GMRA* = 20 × log (VMRA*/0.2) [dB]
27
2005-09-05
TA1383AFG
Note No.
Y4
SW Mode
Characteristic
Test Method
SW28
SW29
SW30
I/O gain 6
C
C
A
(1)
Set INPUT SW (SA 00H) to DSYNC1/RGB (D0H).
(RGB → YPbPr)
↓
↓
(2)
Set MATRIX SW (SA 03H) to MODE-4 (E0H).
A
A
(3)
Input sine wave A (f = 100 kHz) to IN30 and set #30 amplitude to 0.2 Vp-p.
↓
(4)
Measure #24, #23, #22 amplitudes VMGB1, VMGB2, and VMGB3 [V], and determine GMGB1, GMGB2, and GMGB3
using the following equation.
C
GMGB* = 20 × log (VMGB*/0.2) [dB]
(5)
Set SW29 to A, input sine wave B (f = 100 kHz) to IN29, and set #29 amplitude to 0.2 Vp-p.
(6)
Input sync signal to IN30.
(7)
Measure #24, #23, #22 amplitudes VMBB1, VMBB2, and VMBB3 [V], and determine GMBB1, GMBB2, and GMBB3
using the following equation.
GMBB* = 20 × log (VMBB*/0.2) [dB]
(8)
Set SW28 to A and SW29 to C, input sine wave B (f = 100 kHz), and set #28 amplitude to 0.2 Vp-p.
(9)
Input sync signal to IN30.
(10) Measure #24, #23, #22 amplitudes VMRB1, VMRB2, and VMRB3 [V], and determine GMRB1, GMRB2, and GMRB3
using the following equation.
GMRB* = 20 × log (VMRB*/0.2) [dB]
28
2005-09-05
TA1383AFG
Note No.
Characteristic
SW Mode
SW2
Chroma block
CH1
ACC characteristic
Test Method
SW30
Chroma block common test conditions
B
C
(1)
Write data: Transmit PREST DATA. Read data: Read DATA.
(2)
Set SW2 to B, SW4 to C, SW6 to B, SW9 to On, SW12 to A, SW16 to A, SW19 to A, SW22 to B, SW23 to B, and SW24 to B,
SW28 to C, SW29 to C, and SW30 to C. Input sync signal (15.734 kHz) to TP2.
(1)
Input rainbow signal to the C1 IN pin (burst: chroma = 1:1).
(2)
Adjust burst phase so that the lower extremity of the TP23A (Cb/Pb OUT) output waveform is at the second bar; the upper
extremity, at the 7th bar.
(3)
Change the chroma input signal amplitudes to 10, 30, 300, and 600 mVp-p and measure the TP23A (Cb/Pb OUT) output
amplitudes F11, F31, F301, and F601.
Determine A2 = F31/F601 according to the measurement result in (3) above.
(4)
TA23A output signal waveform
F30, F300,
6
1
2
3
4 5
7
8
F600
9
10
F10
10
TA23A (Cb/Pb OUT) output signal waveform
CH2
CH3
Identification sensitivity
APC frequency control sensitivity
B
C
C
C
30
300
600
C1 IN signal amplitude [mVp-p]
(1)
Input rainbow signal to the C1 IN pin (burst: chroma = 1:1).
(2)
Monitor TP26 (CW OUT) DC voltage.
(3)
Increase input signal amplitude from 0. When TP26 (CW OUT) DC voltage reaches High (3.2 V), measure input signal
amplitude VCI.
(4)
Decrease input signal amplitude from 100 mVp-p. When TP26 (CW OUT) DC voltage drops Low (1.4 V), measure input signal
amplitude VBI.
(1)
Connect #20 (APC FILTER) to external power supply (V20).
(2)
Change external power supply (V20) voltage. When #26 (CW OUT) output frequency matches 3.579545 MHz, voltage is
referred to as Vf.
(3)
Measure #26 (CW OUT) output frequency Xf (+100) and Xf (−100) in relation to Vf ± ∆Vf (±100 mVp-p). Determine free-running
sensitivity βf using the following equation.
βf = (Xf (+100) − Xf (−100))/200 [Hz/mV]
29
2005-09-05
TA1383AFG
Note No.
CH4
Characteristic
TOF characteristic
SW Mode
SW2
SW30
B
C
Test Method
(1)
Input sine wave C (10 mVp-p) to C1 IN pin.
(2)
Set TEST (SA 03H) to 82H and TINT (SA 07H) to 30H.
(3)
Set TOF f0 (SA 05H) to 87H (f0 max) and TOF Q (SA 06H) to 87H (Q max).
(4)
Set sine wave C frequency to 3.58 MHz, measure TP26 (CW OUT) signal amplitude, and determine input gain GFC.
(5)
Set sine wave C frequency to 3.58 MHz + 500 kHz, measure TP26 (CW OUT) signal amplitude, and determine input gain
GFH.
(6)
Set sine wave C frequency to 3.58 MHz − 500 kHz, measure TP26 (CW OUT) signal amplitude, and determine input gain GFL.
TP output signal waveform
GFH
GFC
GFL
f0 − 500 kHz
f0
f0 + 500 kHz
C IN input frequency
CH5
TOF (f0･q) control characteristic
B
C
(1)
Input sine wave C (f0 = 3.579545 MHz, amplitude = 10 mVp-p) to C1 IN pin.
(2)
Set TEST (SA 03H) to 82H and TINT (SA 07H) to 30H.
(3)
Set TOF f0 (SA 05H) to 87H (f0 = max) and TOF Q (SA 06H) to 80H (Q min), measure CW OUT (TP26) signal amplitude, and
determine input gain GFF.
(4)
Set TOF f0 (SA 05H) to 81H (f0 = min) and TOF Q (SA 06H) to 87H (max).
(5)
Measure CW OUT (TP26) signal amplitude, and determine input gain GFQ.
30
2005-09-05
TA1383AFG
Note No.
SW Mode
Characteristic
SW2
SW4
SW9
Test Method
SW30
Sync block
SY01
SYNC IN sync phase
Sync block common test conditions
ON
(1)
Write data: Transmit PREST DATA. Read data: Read DATA.
(2)
Set SW6 to B, SW12 to A, SW16 to B, SW19 to B, SW22 to B, SW23 to B, and SW24 to B, SW28 to B, and
SW29 to B.
A
A
A
(1)
Set SA 00H data to 80H (or 90H).
or
or
or
(2)
Set SW2 to A (or C), SW4 to C (or A), and SW30 to C.
C
C
C
(3)
Input composite video signal of 15.734-kHz horizontal frequency to Y1/SYNC1 IN (or Y2/SYNC2 IN).
(4)
Monitor #2 (or #4) pin waveform and #9 (AFC FILTER) pin waveform. Measure phase difference SPH.
(5)
Set SW2 to C, SW4 to C, and SW30 to A.
(6)
Input signal a to D-SYNC1/Y3 IN.
(7)
Set SA 00H data to C4H.
(8)
Monitor #30 pin waveform and #9 (AFC FILTER) pin waveform. Measure phase difference DS1PH.
29.63 µs
2 µs
Signal a
0.286 V
SPH, DS1PH
#9 Pin Waveform
31
2005-09-05
TA1383AFG
Note No.
SY02
SW Mode
Characteristic
HD IN horizontal sync phase
Test Method
SW2
SW4
SW9
SW30
C
C
ON
A
(1)
Set SA 00H data to E2H.
(2)
Input signal b (horizontal frequency 31.5 kHz) to #7 (HD IN).
(3)
Set SA 02H data to 02H.
(4)
Monitor #7 and #9 (AFC FILTER) pin waveforms. Measure phase difference HDPH.
31.75 µs
2.35 µs
Signal b
1.5 V
HDPH
#9 Pin Waveform
32
2005-09-05
TA1383AFG
Note No.
SY03
SW Mode
Characteristic
Delayed HD pulse width
Test Method
SW2
SW4
SW9
SW30
C
C
ON
A
(1)
Set SA 00H data to C0H and input 15.734-kHz composite video signal to D-SYNC1/Y3 IN.
(2)
Determine pulse width Wd-HD0 of delayed HD from #9 (AFC FILTER) pin waveform.
(3)
Set SA 00H data to C2H and input signal c (T = 31.75 µs, t = 2.35 µs) to D-SYNC1/Y3 IN.
(4)
Determine pulse width Wd-HD1 of delay HD from #9 (AFC FILTER) pin waveform.
(5)
Set SA 00H data to C4H and input signal c (T = 29.63 µs, t = 2 µs) to D-SYNC1/Y3 IN.
(6)
Determine pulse width Wd-HD2 of delay HD from #9 (AFC FILTER) pin waveform.
(7)
Set SA 00H data to C6H and input signal c (T = 22.22 µs, t = 1.65 µs) to D-SYNC1/Y3 IN.
(8)
Determine pulse width Wd-HD3 of delay HD from #9 (AFC FILTER) pin waveform.
T
t
Signal c
0.286 V
Wd-HD*
#9 Pin Waveform
33
2005-09-05
TA1383AFG
Note No.
SY04
SW Mode
Characteristic
NTSC
Test Method
SW2
SW4
SW9
SW30
A
C
ON
C
horizontal sync separation level
(1)
Set SA 00H data to 80H.
(2)
Input 15.734-kHz composite video signal to Y1/SYNC1 IN. Set sync signal amplitude to 0.286 Vp-p.
(3)
Decrease horizontal sync signal amplitude of line 21 of field 1 in pedestal direction.
(4)
Monitor #3 (SYNC OUT). When no sync signal on line 21 of field 1 is detected, measure input signal sync
amplitude of line 21, and determine sync separation level VthH10.
(5)
Set SA 01H data to 90H.
(6)
Repeat steps (3) and (4) above and determine sync separation level VthH11.
(7)
Set SA 01H data to A0H.
(8)
Repeat steps (3) and (4) above and determine sync separation level VthH12.
(9)
Set SA 01H data to B0H.
(10) Repeat steps (3) and (4) above and determine sync separation level VthH13.
SY05
NTSC
vertical sync separation level
A
C
ON
C
(1)
Set SA 00H data to 80H.
(2)
Input 15.734-kHz composite video signal to Y1/SYNC1 IN. Set sync signal amplitude to 0.286 Vp-p.
(3)
Decrease vertical sync signal amplitude of first half of line 4 of field 1 in pedestal direction.
(4)
Monitor #15 (VD OUT). When VD pulse start phase shifts to line 5, measure input signal sync amplitude of
line 4, and determine sync separation level VthV10.
(5)
Set SA 01H data to 84H.
(6)
Repeat steps (3) and (4) above and determine sync separation level VthV11.
(7)
Set SA 01H data to 88H.
(8)
Repeat steps (3) and (4) above and determine sync separation level VthV12.
(9)
Set SA 01H data to 8CH.
(10) Repeat steps (3) and (4) above and determine sync separation level VthV13.
34
2005-09-05
TA1383AFG
Note No.
SY06
SW Mode
Characteristic
1125I/60-Hz
Test Method
SW2
SW4
SW9
SW30
C
C
ON
A
horizontal sync separation level
(1)
Set SA 00H data to C4H.
(2)
Input 33.75-kHz (1125I/60-Hz) video signal to D-SYNC1/Y3 IN. Monitor #30 (D-SYNC1/Y3 IN) and measure
sync tip DC voltage Vsync30.
(3)
Apply external voltage to #30 via 100 kΩ. Increase voltage from Vsync30.
(4)
Monitor #17 (HD OUT). When phase is unlocked from input sync signal, measure #30 sync tip voltage.
Determine difference from Vsync30, VthH20.
(5)
Set SA 01H data to 90H.
(6)
Repeat steps (3) and (4) above and determine sync separation level VthH21.
(7)
Set SA 01H data to A0H.
(8)
Repeat steps (3) and (4) above and determine sync separation level VthH22.
(9)
Set SA 01H data to B0H.
(10) Repeat steps (3) and (4) above and determine sync separation level VthH23.
SY07
1125I/60-Hz
vertical sync separation level
C
C
ON
A
(1)
SA 00H data to C4H.
(2)
Input 33.75-kHz (1125I/60-Hz) video signal to D-SYNC1/Y3 IN. Monitor #30 (D-SYNC1/Y3 IN) and measure
sync tip DC voltage Vsync30.
(3)
Apply external voltage to #30 via 100 kΩ. Increase voltage from Vsync30.
(4)
Monitor #17 (HD OUT). When phase is unlocked from input sync signal, measure #30 sync tip voltage.
Determine difference from Vsync30, VthV20.
(5)
Set SA 01H data to 84H.
(6)
Repeat steps (3) and (4) above and determine sync separation level VthV21.
(7)
Set SA 01H data to 88H.
(8)
Repeat steps (3) and (4) above and determine sync separation level VthV22.
(9)
Set SA 01H data to 8CH.
(10) Repeat steps (3) and (4) above and determine sync separation level VthV23.
35
2005-09-05
TA1383AFG
Note No.
SY08
SW Mode
Characteristic
DSYNC2 sync separation level
Test Method
SW2
SW4
SW9
SW30
C
C
ON
C
(1)
Set SW6 to A and set SA 00H data to 00H.
(2)
Input 33.75-kHz (1125I/60) video signal to TP6 (D-SYNC2 IN).
(3)
Monitor #6 (D-SYNC2 IN) and measure sync tip DC voltage Vsync6.
(4)
Apply external voltage to #30 via 100 kΩ. Increase voltage from Vsyn6.
(5)
Monitor READ BUS DATA. When H/V FREQ data deviate from approx. 33.75 kHz/60 Hz, measure #6 sync
tip voltage. Determine difference from Vsync6, VthD20.
(6)
Set SA 01H data to 81H.
(7)
Repeat steps (3) and (4) above and determine sync separation level VthD21.
(8)
Set SA 01H data to 82H.
(9)
Repeat steps (3) and (4) above and determine sync separation level VthD22.
(10) Set SA 01H data to 83H.
(11) Repeat steps (3) and (4) above and determine sync separation level VthD23.
SY09
SY10
Horizontal free-running frequency
Horizontal frequency range
C
C
C
C
OPEN
OPEN
C
C
(1)
Set SW9 to open and SA 00H data to 80H.
(2)
Monitor #17 (HD OUT) pin waveform and measure oscillation frequency FA000.
(3)
As in steps (1) and (2) above, set SA00H data to 82H, 84H, 86H, 88H, and 8AH. Measure respective
oscillation frequencies FA001, FA010, FA011, FA100, and FA101.
(4)
Set SA 00H data to 8CH, SA 02H to 83H, and SA 03H to 82H.
(5)
Monitor #17 (HD OUT) pin waveform and measure oscillation frequency FA110.
(6)
Set SA 00H data to 8EH, monitor #17 (HD OUT) pin waveform, and count oscillation frequency FA111.
(7)
Set SA 00H data to 80H, SA 02H to E0H, and SA 03H to 80H.
(8)
Monitor #17 (HD OUT) pin waveform and count oscillation frequency FF000.
(1)
Set SW9 to open and SA 00H data to 80H.
(2)
Apply 9 V to #9 via 10 kΩ. Monitor #17 (HD OUT) pin waveform and count oscillation frequency F1573MIN.
(3)
Apply 0 V to #9 via 10 kΩ. Monitor #17 (HD OUT) pin waveform and count oscillation frequency F1573MAX.
(4)
Set SA 00H data to 82H. As in steps (2) and (3) above, count oscillation frequencies F315MIN and
F315MAX.
(5)
Set SA 00H data to 81H. As in steps (2) and (3) above, count oscillation frequencies 1573nMIN and
F1573nMAX.
36
2005-09-05
TA1383AFG
Note No.
SY11
SW Mode
Characteristic
AFC phase detection current
Test Method
SW2
SW4
SW9
SW30
C
C
OPEN
C
(1)
Set SA 00H to C0H and SA 02H to A0H.
(2)
Set SW9 to open and measure #9 voltage V9 (6.3 to 6.4 V) (measure #9 voltage at no load).
(3)
Connect external power supply (PS) to TP9 and apply V9.
(4)
Set SW30 to A. Input 15.734-kHz sync signal d to D-SYNC1/Y3 IN. Monitor #9. Measure voltages V1 and
V2.
(5)
Set SA 02H data to C0H. Repeat steps (2) to (4) above. Measure voltages V3 and V4.
(6)
Set SA 02H data to 80H. Connect external power supply (PS) to TP9 and apply V9 − 0.1 V and measure
voltage V5.
(7)
Connect external power supply (PS) to TP9 and apply V9 + 0.1 V and measure voltage V6.
(8)
Determine ID1 to ID6 using following equations.
ID1+ = (V1 [V] ÷ 1 [kΩ]) × 1000 [µA]
ID1− = (V2 [V] ÷ 1 [kΩ]) × 1000 [µA]
ID2+ = (V3 [V] ÷ 1 [kΩ]) × 1000 [µA]
ID2− = (V4 [V] ÷ 1 [kΩ]) × 1000 [µA]
ID3+ = (V5 [V] ÷ 1 [kΩ]) × 1000 [µA]
ID3− = (V6 [V] ÷ 1 [kΩ]) × 1000 [µA]
63.5 µs
4.7 µs
Signal d
0.286 V
V1, V3, V5
#9 Pin Waveform
V2, V4, V6
37
2005-09-05
TA1383AFG
Note No.
SY12
SW Mode
Characteristic
HD output phase and width
Test Method
SW2
SW4
SW9
SW30
C
C
ON
A
(1)
Set SA 00H data to C0H.
(2)
Input 15.734-kHz composite video signal to D-SYNC1/Y3 IN.
(3)
Measure #17 (HD OUT) and #30. Measure phase difference HDS0 and pulse width HDW0.
(4)
Set SA 00H data to C2H. Input signal c (T = 31.75 µs, t = 2.35 µs) and measure phase difference HDS1 and
pulse width HDW1.
(5)
Set SA 00H data to C4H. Input signal c (T = 29.63 µs, t = 2 µs) to D-SYNC1/Y3 IN and measure phase
difference HDS2 and pulse width HDW2.
(6)
Set SA 00H data to C6H. Input signal c (T = 24.1 µs, t = 1.65 µs) to D-SYNC1/Y3 IN and measure phase
difference HDS3 and pulse width HDW3.
(7)
Set SA 00H data to CCH. Input signal c (T = 14.815 µs, t = 1 µs) to D-SYNC1/Y3 IN and measure phase
difference HDS4 and pulse width HDW4.
(8)
Set SA 00H data to FEH. Input signal c (T = 31.75 µs, t = 2.35 µs, amplitude = 1.5 V) to D-SYNC1/Y3 IN and
measure phase difference HDS5 and pulse width HDW5.
T
t
Signal c
0.286 V
HDS*
#17 Pin Waveform
HDW*
38
2005-09-05
TA1383AFG
Note No.
SY13
SW Mode
Characteristic
HD output phase adjustment range
Test Method
SW2
SW4
SW9
SW30
C
C
ON
C
(1)
While monitoring #17 (HD OUT), change SA 04H data from 80H to 88H, and measure #17 pin waveform
phase amount ∆HP0−.
(2)
While monitoring #17 (HD OUT), change SA 04H data from 88H to 8FH, and measure #17 pin waveform
phase amount ∆HP0+.
(3)
Set SA 00H data to 82H. While monitoring #17 (HD OUT), change SA 04H data from 80H to 88H, and
measure #17 pin waveform phase amount ∆HP1−.
(4)
While monitoring #17 (HD OUT), change SA 04H data from 88H to 8FH, and measure #17 pin waveform
phase amount ∆HP1+.
(5)
Set SA 00H data to 84H. While monitoring #17 (HD OUT), change SA 04H data from 80H to 88H, and
measure #17 pin waveform phase amount ∆HP2−.
(6)
While monitoring #17 (HD OUT), change SA 04H data from 88H to 8FH, and measure #17 pin waveform
phase amount ∆HP2+.
(7)
Set SA 00H data to 86H. While monitoring #17 (HD OUT), change SA 04H data from 80H to 88H, and
measure #17 pin waveform phase amount ∆HP3−.
(8)
While monitoring #17 (HD OUT), change SA 04H data from 88H to 8FH, and measure #17 pin waveform
phase amount ∆HP3+.
39
2005-09-05
TA1383AFG
Note No.
SY14
SW Mode
Characteristic
Clamp pulse phase and width
Test Method
SW2
SW4
SW9
SW30
C
C
ON
A
(1)
Set SA 00H data to C0H. Input 15.734-kHz composite video signal to D-SYNC1/Y3 IN.
(2)
Set SA 02H data to 86H.
(3)
Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS0 and width CPW0.
(4)
Set SA 00H data to C2H. Input signal c (T = 31.75 µs, t = 2.35 µs) to D-SYNC1/Y3 IN.
(5)
Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS1 and width CPW1.
(6)
Set SA 00H data to C4H. Input signal c (T = 29.63 µs, t = 2 µs) to D-SYNC1/Y3 IN.
(7)
Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS2 and width CPW2.
(8)
Set SA 00H data to C6H. Input signal c (T = 22.22 µs, t = 1.65 µs) to D-SYNC1/Y3 IN.
(9)
Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS3 and width CPW3.
(10) Set SA 00H data to CCH. Input signal c (T = 14.815 µs, t = 1.15 µs) to D-SYNC1/Y3 IN.
(11) Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS4 and width CPW4.
(12) Set SA 00H data to FEH. Input signal c (T = 31.75 µs, t = 2.35 µs, amplitude = 1.5 V) to D-SYNC1/Y3 IN.
(13) Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS5 and width CPW5.
T
t
Signal c
0.286 V
CPS*
TP8 Pin Waveform
CPW*
SY15
Noise detection
A
C
ON
C
(1)
Set SA 00H data to 80H.
(2)
Input 500-kHz sine wave to Y1/SYNC2 IN. Increase sine wave amplitude from 0 Vp-p. When READ MODE 1
N-DET changes from 0 to 1, measure amplitude NHi00.
Input 500-kHz sine wave to Y1/SYNC2 IN. Decrease sine wave amplitude from 1.0 Vp-p. When READ MODE
1 N-DET changes from 1 to 0, measure amplitude NLow00.
As in steps (1) and (2) above, set SA 02H (NOISE LVL) data to 88H, 90H, and 98H, and measure respective
amplitudes NHi01, NLow01, NHi0, NLow10, NHi11, and Nlow11.
(3)
(4)
40
2005-09-05
TA1383AFG
Note No.
SY16
SW Mode
Characteristic
VD output width
VD output phase
Test Method
SW2
SW4
SW9
SW30
C
C
ON
A
(1)
Set SA 00H data to C0H. Input 15.734-kHz composite video signal (525I/60-Hz) to D-SYNC1/Y3 IN.
(2)
Monitor #30 and TP15 (VP OUT). Measure VD output width VDW000 and phase difference VDPh000.
(3)
Set SA 00H data to C8H. Monitor #30 and TP15 (VP OUT). Measure VD output width VDW100.
(4)
Set SA 00H data to CAH. Monitor #30 and TP15 (VP OUT). Measure VD output width VDW101.
(5)
Set SA 00H data to C0H and SA 03H data to 84H. Monitor #30 and TP15 (VP OUT). Measure VD output
phase difference VDPh000b.
(6)
Set SA 00H data to C2H. Input 525P/60-Hz composite video signal to D-SYNC1/Y3 IN.
(7)
Monitor #30 and TP15 (VP OUT). Measure VD output phase difference VDPh001 and width VDW001.
(8)
Set SA 00H data to C4H. Input 1125I/60-Hz composite video signal to D-SYNC1/Y3 IN.
(9)
Monitor #30 and TP15 (VP OUT). Measure VD output phase difference VDPh010 and width VDW010.
(10) Set SA 00H data to C6H. Input 750P/60-Hz composite video signal to D-SYNC1/Y3 IN.
(11) Monitor #30 and TP15 (VP OUT). Measure VD output phase difference VDPh110 and width VDW110.
(12) Set SA 00H data to CCH. Input 1125P/60-Hz composite video signal to D-SYNC1/Y3 IN.
(13) Monitor #30 and TP15 (VP OUT). Measure VD output width VDW110.
Video Signal
525I-60 Hz or
525P-60 Hz
TP15 Pin Waveform
VDPh000, VDPh000b, VDPh001
VDW000, VDPh001, VDW100, VDW101
Video Signal
1125I-60 Hz
VDPh010
TP15 Pin Waveform
Video Signal
750P-60 Hz or
1125P-60 Hz
TP15 Pin Waveform
41
VDW010
VPPh011
VDW011, VDW110
2005-09-05
TA1383AFG
Signals Used for Testing
•
Sine wave A
•
Sine wave B
•
Sync signal
•
Rainbow signal
180°150°120° 90° 60° 30° 0° −30°−60°−90°
•
Sine wave C
•
Composite video signal
15.743 kHz
42
2005-09-05
A C
B
A C
B
TP2
TP4
#5
DV IN
A B
TP6
D-SYNC2
IN
43
#8
#9
#7
TP8 TP9
HD IN MONITOR
#10
10
11
A
B
C
D
#12
12
ADD
#13
13
SDA
18
#14
14
SCL
C1 IN
#17
VD OUT
HD OUT
19
100 Ω
0.1 µF (Note 7)
or 100 pF
BC
A
SCL
20
DIGITAL GND
0.0022 µF
3.58 MHz X’tal
30 kΩ 0.22 µF
#19
SDA
21
C2 IN
APC FILTER
100 Ω
#20
ADDRESS
GND1
100 Ω
12 pF
100 Ω
#21
HD OUT
TP17
BC
A
#16
17
16
#15
0.1 µF (Note 7)
or
100 pF
TP19
100 Ω
9
CSB503F30
3.58 X’tal
A B
HVCO
Cr/Pr OUT
A B
1.6 kΩ
2.2 kΩ
75 Ω
1.6 kΩ
2.2 kΩ
75 Ω
10 µF
100 µF
0.01 µF
2.7 kΩ
2.7 kΩ
1.6 kΩ TP22B
1.6 kΩ TP23B
1.6 kΩ TP24B
3.9 kΩ
3.9 kΩ
C1 IN
IN16
470 Ω
8
AFC FILTER
Cb/Pb OUT
Y OUT
TP24A TP23A TP22A
10 µF
470 Ω
7
MONITOR OUT
6
C2 IN
IN19
15 kΩ 15 kΩ 15 kΩ
#6
HD IN
#24
#23
#22
Cr
Cb
Y OUT
25
24 OUT 23 OUT 22
A B
470 Ω
5
SW9
4
1 kΩ
#4
VCC2 (5 V)
TP26B
6.2 kΩ
Sync
OUT
3
CW TP26
OUT
100 Ω
0.01 µF 100 µF
TP28
0.01 µF
#3
#26
D-SYNC2 IN
(for freq. det.)
26
fsc OUT
10 µF
100 Ω
2
B
A C
VD IN
27
GND2
1.6 kΩ
5.1 kΩ
75 Ω
TP26C
0.1 µF
#2
#28
0.1 µF
B
A C
Y2/SYNC2 IN
28
Cr/Pr/R IN
TP29
0.1 µF
1
#29
0.1 µF
B
A C
SYNC OUT
29
Cb/Pb/B IN
#30
0.1 µF
3.9 kΩ
TP30
10 KΩ
30
D-SYNC1/Y3/G IN
1.6 kΩ
5.1 kΩ
10 µF
Y1/SYNC1 IN
VCC1 (9 V)
3.9 kΩ
IN29
0.1 µF
100 µF 0.01 µF
1.6 kΩ
5.1 kΩ
75 Ω
IN28
1 µF
Y1/Sync2 IN
10 µF
IN4
1.6 kΩ
Y1/Sync1 IN
10 µF
IN2
3.9 kΩ
D-Sync1/Y3 IN
10 µF
IN30
1.6 kΩ
5.1 kΩ
75 Ω
Cb IN
3.9 kΩ
75 Ω
0.01 µF
Cr IN
5.1 kΩ
75 Ω
VCC 9 V
100 µF
TA1383AFG
Test Circuit Diagram
VCC 5 V
TP16
TA1383AFG
15
VD OUT
TP15
Note 7: If there is a possibility of inputting CVBS
signals, connect a 100-pF capacitor.
2005-09-05
Y2/Sync2 IN
D-Sync2 IN
1.6 kΩ
10 µF
Y1/Sync1
DV IN
10 µF
Y2/Sync2
D-Sync2
44
HD IN MONITOR
SDA
A
B
C
D
SCL
VD OUT
ADD
18
SDA
17
SCL
C1 IN
0.1 µF (Note 8)
or
100 pF
0.1 µF (Note 8)
or 100 pF
1.6 kΩ
2.2 kΩ
75 Ω
2.7 kΩ
2.7 kΩ
2.2 kΩ
1.6 kΩ
75 Ω
C2 IN
HD OUT
19
DIGITAL GND
20
C2 IN
21
30 kΩ 0.22 µF
0.01 µF
10 µF
470 Ω
ADDRESS
APC FILTER
2200 pF
X’tal
Cr OUT
Cb OUT
5V
470 Ω
GND1
3.58 X’tal
12 pF
100 Ω
100 Ω
100 Ω
Y OUT
C2 IN
HVCO
HVCO
22
Cr/Pr OUT
Y OUT
0.01 µF 100 µF
100 µF
0.01 µF
0.01 µF
3.9 kΩ
5V
15 kΩ 15 kΩ 15 kΩ
Sync
OUT
23
470 Ω
AFC FILTER
24
Cb/Pb OUT
25
VCC2 (5 V)
CW
OUT
6.2 kΩ
MONITOR OUT
26
fsc OUT
D-Sync1/Y3
1 µF
HD IN
27
GND2
#28
0.1 µF
Cb
0.01 µF
D-SYNC2 IN
(for freq. det.)
28
Cr/Pr/R IN
0.1 µF
1.6 kΩ
5.1 kΩ
Reg.
0.1 µF
VD IN
2
Y2/SYNC2 IN
29
Cb/Pb/B IN
0.1 µF
1.6 kΩ
3.9 kΩ
5.1 kΩ
9V
0.1 µF
10 µF
SYNC OUT
1
10 KΩ
Y1/SYNC1 IN
3.9 kΩ
30
D-SYNC1/Y3/G IN
1.6 kΩ
5.1 kΩ
75 Ω
Cr
0.1 µF
3.9 kΩ
D-Sync1/Y3 IN 10 µF
VCC1 (9 V)
1.6 kΩ
5.1 kΩ
0.01 µF
75 Ω
10 µF
100 µF 0.01 µF
3.9 kΩ
Y1/Sync1 IN
5.1 kΩ
75 Ω
10 µF
1.6 kΩ
3.9 kΩ
75 Ω
0.01 µF
Cr IN
5.1 kΩ
75 Ω
Cb IN
75 Ω
9V
100 µF
TA1383AFG
Application Circuit 1 (Typical values)
C1 IN
10 µF
C1 IN
HD OUT
16
TA1383AFG
3
4
5
6
7
8
9
10
11
12
13
14
15
VD OUT
Note 8: If there is a possibility of inputting CVBS
signals, connect a 100-pF capacitor.
2005-09-05
TA1383AFG
Application Circuit 2 (How to measure H/V frequency)
16
C1-IN
APC
19
C2-IN
Internal pulse (A)
FREQ
COUNTER
6
D-SYNC2-IN
(for H/V freq.
counter)
BUS READ
TA1383
This IC’s H/V frequency counting is done by internal pulse (A) which is made in APC circuit. So, if APC circuit
doesn’t lock in the regular frequency, the frequency of pulse (A) will not be correct and the H/V frequency data will
not be showed correct data.
Decision algorithm of H/V frequency detection (detection range, detection times and so on) should be determined
under consideration the factors such as signal strength, existence of ghost signal, APC stability, I2C BUS data
transmission and so on via prototype TV set evaluation.
45
2005-09-05
TA1383AFG
Package Dimensions
Weight: 0.63 g (typ.)
46
2005-09-05
TA1383AFG
47
2005-09-05