TOSHIBA TA1318NG

TA1318NG
TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic
TA1318NG
SYNC Processor, Frequency Counter IC for TV Component Signals
TA1318NG is a sync processor for TV component signals.
TA1318NG provides sync and frequency counter processing for
external input signals.
These functions are integrated in a 24 pin dual-in-line
shrink-type plastic package.
TA1318NG provides I2C bus interface, so various functions and
controls are adjustable via the bus.
Features
•
Horizontal synchronization circuit (15.75 kHz, 31.5 kHz, 33.75
kHz, 45 kHz)
•
Vertical synchronization circuit (525I, 525P, 625I, 750P, 1125I, 1125P, PAL 100 Hz, NTSC 120 Hz)
•
Horizontal and vertical frequency counter
•
Horizontal PLL
•
Accepts 2-level and 3-level sync
•
Accepts both negative and positive HD and VD
•
Clamp pulse output
•
HD, VD output (polarity inverter)
•
Separated sync output
•
Mask for the copy guard signal
1
Weight: 1.22 g (typ.)
2005-09-08
TA1318NG
Block Diagram
DAC3
VD2-OUT
VD1-OUT
SYNC1-IN
DAC1
SYNC2-IN
Address SW
SCL
SDA
HD2-OUT
Digital GND
HD1-OUT
24
23
22
21
20
19
18
17
16
15
14
13
DAC3
SW
INV
SW
INV
SW
SYNC
SEPA
DAC1
SW
SYNC
SEPA
DV2-OUT
SW
DV1-OUT
SW
TEST DAC3
2
I CBUS
Decoder
DAC1
V-Input
SW
H/VFREQ
Counter
INV
SW
HD2-OUT
SW
HD1-OUT
SW
V-FREQ
SW
V C/D
V-FREQ
DET SW
V-SYNC
Clamp
CP
SW
Pulse
DAC2
DAC2
SW
H/CSYNC
INV
SW
H-FREQ
DET SW
V
Integral
HD
Polarity
H-INPUT
SW
H-AFC
2 × fH
H C/D
H-Ramp
H-FREQ
HVCO
SW
1
2
3
4
5
6
7
8
9
10
11
12
HD2-IN
VD2-IN
HD1-IN
VD1-IN
Analog GND
AFC Filter
HVCO
VCC
DAC2
VD3-IN
HD3-IN
CP-OUT
2
2005-09-08
TA1318NG
Pin Functions
Pin
No.
Pin Name
Function
Interface Circuit
8
Input Signal/Output Signal
Th: 0.7 V
Inputs horizontal sync signal.
1
HD2-IN
Accepts input of both positive
and negative polarity.
1
1 kΩ
50 kΩ
Input signal from this pin is not
synchronized.
or
Th: 0.7 V
5
8
Th: 0.7 V
Inputs vertical sync signal.
VD2-IN
Accepts input of both positive
and negative polarity.
Input signal from this pin is not
synchronized.
2
1 kΩ
or
45 kΩ
2
Th: 0.7 V
5
3
2005-09-08
TA1318NG
Pin
No.
Pin Name
Function
Interface Circuit
8
Input Signal/Output Signal
Th: 0.7 V
Inputs horizontal sync signal.
3
HD1-IN
Accepts input of both positive
and negative polarity.
3
1 kΩ
50 kΩ
Input signal from this pin is not
synchronized.
or
Th: 0.7 V
5
8
Th: 0.7 V
Inputs vertical sync signal.
VD1-IN
Accepts input of both positive
and negative polarity.
Input signal from this pin is not
synchronized.
4
1 kΩ
or
45 kΩ
4
Th: 0.7 V
5
5
Analog GND
GND pin for analog circuit
blocks.
⎯
4
⎯
2005-09-08
TA1318NG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
8
Connects filter for horizontal
AFC.
6
300 Ω
AFC Filter
Voltage on this pin determines
horizontal output frequency.
6
DC
30 kΩ
5
8
Connects ceramic oscillator for
horizontal oscillation.
4 kΩ
Use Murata
CSBLA503KECZF30.
7
⎯
1 kΩ
HVCO
2 kΩ
7
1 kΩ
10 kΩ
5
VCC pin.
8
VCC
⎯
Connects 9 V (typ.).
5
⎯
2005-09-08
TA1318NG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
8
DC
500 Ω
DAC2 output pin.
In Test mode, outputs HD or
composite sync signal to
frequency counter.
DAC2 (H/C. SYNC output)
To improve the driving ability, it
is possible to connect a
resister (minimum: 2 kΩ)
between this pin and GND.
However, when the resister is
added, the output DC voltage
is down.
9
H/C SYNC
200 Ω
7V
30 kΩ
9
or
0V
14
8
Th: 0.7 V
Inputs vertical sync signal.
VD3-IN
Accepts input of both positive
and negative polarity.
10
1 kΩ
or
45 kΩ
10
Th: 0.7 V
5
8
Th: 0.7 V
Inputs horizontal sync signal.
HD3-IN
Accepts input of both positive
and negative polarity.
11
1 kΩ
or
50 kΩ
11
Th: 0.7 V
5
6
2005-09-08
TA1318NG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
500 Ω
8
5.0 V
Clamp pulse (CP) output pin.
CP-OUT
Outputs CP generated by sync
circuit.
12
0V
200 Ω
2.5 kΩ
12
14
8
HD output pin.
Open collector output.
13
HD1-OUT
HD1/HD2 input signal is output
from this pin without
synchronization.
13
200 Ω
or
Polarity is switched by BUS
write function.
14
14
Digital GND
⎯
GND pin for logic blocks.
7
⎯
2005-09-08
TA1318NG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
8
HD output pin.
Open collector output.
15
HD2-OUT
HD1/HD2 input signal is output
from this pin without
synchronization.
15
200 Ω
or
Polarity is switched by BUS
write function.
14
8
SDA
2
SDA pin for I C bus.
50 Ω
16
ACK
20 kΩ
SDA
⎯
4 VF
16
5
14
8
2005-09-08
TA1318NG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
8
SCL
2
SCL pin for I C bus.
20 kΩ
17
⎯
SCL
4 VF
17
5
7.5 V
60 kΩ
18
DA/DB
1.5 V
9
100 kΩ
When this pin is connected to
VCC (GND), used for DC/DDH
(D8/D9H); when left open,
DA/DBH.
15 kΩ
Address SW
9V
DC/DD
7.5 V
1 kΩ
100 kΩ
18
15 kΩ
100 kΩ
Slave address switch pin.
8
1.5 V
D8/D9
0 V
5
2005-09-08
TA1318NG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
White 100％ = 1 Vp−p
1 kΩ
8
Inputs Y signal (Note 1) for
sync separation circuit.
19
or
1 kΩ
4 VF
Input via clamp capacitor.
1 kΩ
SYNC2-IN
1 kΩ
19
5
8
500 Ω
DAC1 output pin.
In Test mode, outputs VD or
composite sync signal to
frequency counter.
DAC1 (V SYNC output)
To improve the driving ability, it
is possible to connect a
resister (minimum: 2 kΩ)
between this pin and GND.
However, when the resister is
added, the output DC voltage
is down.
20
or
V SYNC
200 Ω
7V
30 kΩ
20
DC
0V
14
Note 1: The signal format for SYNC1-IN (pin 21) and SYNC2-IN (pin 19)
NTSC (525I/60 Hz), PAL/SECAM (625I/50 Hz), NTSC Double Scan (525I/120 Hz), PAL/SECAM Double Scan (625I/100 Hz), 525P/60 Hz, 750P/60 Hz,
1125I/60 Hz, 1125P/30 Hz
This IC doesn’t have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on.
10
2005-09-08
TA1318NG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
White 100％ = 1 Vp−p
1 kΩ
8
Inputs Y signal (Note 1) for
sync separation circuit.
21
or
1 kΩ
4 VF
Input via clamp capacitor.
1 kΩ
SYNC1-IN
1 kΩ
21
5
8
VD output pin.
Open collector output.
VD1/VD2 input signal is output
from this pin without
synchronization.
22
VD1-OUT
22
Start phase
200 Ω
or
Polarity is switched by BUS
write function.
(Note) When HD PHASE will
be changed, synchronized VD
width will change. Use the start
phase of VD.
14
Start phase
Note 1: The signal format for SYNC1-IN (pin 21) and SYNC2-IN (pin 19)
NTSC (525I/60 Hz), PAL/SECAM (625I/50 Hz), NTSC Double Scan (525I/120 Hz), PAL/SECAM Double Scan (625I/100 Hz), 525P/60 Hz, 750P/60 Hz,
1125I/60 Hz, 1125P/30 Hz
This IC doesn’t have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on.
11
2005-09-08
TA1318NG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
8
VD output pin.
Open collector output.
VD1/VD2 input signal is output
from this pin without
synchronization.
23
VD2-OUT
Start phase
23
200 Ω
or
Polarity is switched by BUS
write function.
(Note) When HD PHASE will
be changed, synchronized VD
width will change. Use the start
phase of VD.
14
Start phase
8
DAC3 output pin.
24
DAC3
Open collector output.
24
DC
500 Ω
or
In Test mode, outputs test
pulse for shipping.
test pulse for shipping
14
12
2005-09-08
TA1318NG
Bus Control Map
Write Mode
Slave Address: D8/DA/DCH
Sub-Add
D7
MSB
D6
D5
D4
D3
00
H-FREQUENCY
HD1/VD1-OUT SW
01
DAC1
DAC2
02
V-FREQUENCY
03
D2
HD2/VD2-OUT SW
DAC3
CLP-PHS
TEST
FREQ DET SW
HD PHASE
D1
D0
LSB
SEPA LEVEL
HD1-INV
HD2-INV
INPUT SW
VD1-INV
VD2-INV
D1
D0
LSB
Preset
MSB
LSB
1000
0000
1000
0000
1000
0000
1000
0000
Read Mode
Slave Address: D9/DB/DDH
D7
MSB
D6
D5
D4
D3
0
POR
V FREQUENCY DET
1
HD-IN
H FREQUENCY DET
D2
Bus Control Functions
Write Mode (*: Preset)
•
•
•
•
•
•
•
•
H-FREQUENCY (Horizontal oscillation frequency)
Switches horizontal frequency.
*(10): 33.75 kHz
(00): 15.75 kHz
(01): 31.5 kHz
(11): 45 kHz
Note: To prevent a horizontal mislock, set (10) 33.75 kHz mode just before (01) 31.5 kHz mode setting when
the horizontal frequency mode is switched to (01) 31.5 kHz mode.(wait time: 1 ms or more)
Additionally, in 31.5 kHz mode, set (10) 33.75 kHz mode at first and set (01) 31.5 kHz mode again,
when 525 p/625 p signal is pulled-in again from no-input.
HD1/VD1-OUT SW (HD1/VD1 output switch)
Switches output from pin 13/22. When set to 00, 01, or 10, outputs HD/VD without synchronization.
When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when
HD PHASE will be changed.
*(00): HD1/VD1
(01): HD2/VD2
(10): HD3/VD3
(11): Synchronized HD/VD
HD2/VD2-OUT SW (HD2/VD2 output switch)
Switches output from pin 15/23. When set to 00, 01, or 10, outputs HD/VD without synchronization.
When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when
HD PHASE will be changed.
*(00): HD1/VD1
(01): HD2/VD2
(10): HD3/VD3
(11): Synchronized HD/VD
SEPA LEVEL (Sync separation level switch)
Switches sync separation level of pin 19/21. Set values are the levels from sync tip. Sync separation level
is changed according to the ratio of H-SYNC width during 1H period.
*(00): 10IRE
(01): 15IRE
(10): 20IRE
(11): 25IRE (at 1125I/60)
DAC1 (DAC1 control)
Controls 2-bit DAC (pin 9).
*(10): 5 V
(00): 1 V
(01): 3 V
(11): 7 V
DAC2 (DAC2 control)
Controls 2-bit DAC (pin 20).
*(00): 1 V
(01): 3 V
(10): 5 V
(11): 7 V
DAC3 (DAC3 control)
Controls open collector 1-bit DAC (pin 24).
*(0): OPEN (HIGH)
(1): ON (LOW)
TEST (Test mode)
Switches DAC1, 2, and 3 outputs. Also used to test IC for shipping.
*(0): DAC outputs are used as DAC.
(1): DAC1 outputs V. SYNC to the frequency counter.
DAC2 outputs H. SYNC or C. SYNC to the frequency counter.
DAC3 outputs IC test pulse for shipping.
13
2005-09-08
TA1318NG
•
•
•
HD1-INV (HD1 output polarity switch)
Switches HD1 output (pin 13) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
*(0): Normal
(1): Inverse
HD2-INV (HD2 output polarity switch)
Switches HD1 output (pin 15) polarity. When set to 0, positive HD input is output as negative HD. When
set to 0, output from the sync circuit is output as negative HD.
*(0): Normal
(1): Inverse
V-FREQUENCY (Vertical frequency switch (pull-in range))
Sets vertical frequency pull-in range, VD-STOP, or free-running frequency.
Free-running frequency is controlled by H-FREQUENCY.
Pull-in Range
•
•
•
•
•
•
Format/H (V) Frequency
*(000)
48~1281 H
1125P/30 Hz (33.75 kHz)
(001)
48~849 H
750P/60 Hz (45 kHz)
(010)
FREE-RUN
(011)
48~637 H
1125I/60 Hz (33.75 kHz)
(100)
48~613 H
525P/60 Hz (31.5 kHz)
(101)
48~363 H
PAL/SECAM/50 Hz (15.625 kHz)
PAL/SECAM double scan/100 Hz (31.5 kHz)
(110)
48~307 H
NTSC/60 Hz (15.734 kHz)
NTSC double scan /120 Hz (31.5 kHz)
(111)
VP STOP
VD output is HIGH
Free-running frequency is controlled by H-FREQUENCY.
(00): 262 H (01): 525 H (10): 562 H (11): 750 H
CLP PHS (Clamp pulse phase switch)
Switches clamp pulse phase.
If no signal input, 0.9 µs pulse is output from the H-C/D circuit.
*(0): 1 µs (3.4%) delay following HD stop phase, 0.8 µs (2.7%) pulse
(1): 0.5 µs (1.7%) delay following HD stop phase, 0.8 µs (2.7%) pulse
FREQ DET SW (Horizontal/vertical frequency counter switch)
Switches input signal used for horizontal/vertical frequency counter. This switch is controlled
independently from INPUT SW. The detection result is output as read BUS data.
*(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs
INPUT SW (Input signal switch for synchronization)
Switches input signal used for synchronization.
*(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs
HD PHASE (HD phase adjustment)
Adjusts phase of HD output from the sync circuit. The phase of the adjustment center value is the same
as that of input H-SYNC or input HD. (Note) Synchronized VD width will change, when HD PHASE will
be changed.
(000000) :
−5% (H periodically)
*(100000) :
0%
(111111) :
5%
VD1-INV (VD1 output polarity switch)
Switches VD1 output (pin 22) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
*(0): Normal
(1): Inverse
VD2-INV (VD2 output polarity switch)
Switches VD2 output (pin 23) polarity. When set to 0, negative VD input is output as negative VD. When
set to 0, output from the sync circuit is output as negative VD.
*(0): Normal
(1): Inverse
14
2005-09-08
TA1318NG
Read Mode
•
•
•
•
POR (Power on reset)
(0): Status read (at second data read and subsequent)
(1): Power on (at first data read)
HD-IN (Input signal self-check result)
Detects HD or H-SYNC input signal selected by INPUT SW.
(0): No signal input (1): Signal input
V FREQ DET (Vertical frequency of SYNC or VD input selected by FREQ DET SW)
(0000000)∼(0001100): No-VD
(0001101) : Vicinity of 162 Hz
(1111110) : Vicinity of 17 Hz
How to calculate vertical frequency (X):
Convert V-FREQ DET read data into decimal and define the resulting value as Y.
Where H-FREQUENCY is 15.75 kHz/31.5 kHz, Z = 476.2 µs
Where H-FREQUENCY is 33.75 kHz/45 kHz, Z = 474.1 µs
Vertical frequency (X) = 1 ÷ (Y × Z) [Hz]
Error of Y is +1, −0. If vertical frequency is 162 Hz or more, the frequency cannot be accurately
measured. Time constant used to separate V.SYNC from integrated C.SYNC is 9 µs (error: ±1 µs).
H FREQ DET (Horizontal frequency of SYNC or HD input selected by FREQ DET SW)
(0000000): No signal input (1111110): 53 kHz or more
How to calculate horizontal frequency (X):
X, Y, and Z are defined same as for V FREQ.
Horizontal frequency (X) = Y ÷ (5 × Z) [kHz]
Error of Y is +1, −0. If horizontal frequency is 53 kHz or more, the frequency cannot be accurately
measured. When V-SYNC or VD is not input, horizontal frequency cannot be measured, resulting in
data = (0000000).
Note 1: The start trigger for frequency counting is the internal reset-pulse made from ACK of 2nd byte in BUS
read mode. The counting period is between the first V-sync (VD) and the second V-sync (VD) after the
trigger.
The counted data will have +1 or −0 error according to the read timing.
To assume stable data reading;
1. Set BUS reading interval more than 60 ms.
2. Don’t use the first data because it is unsettled.
are recommended.
Note 2: Make data (1111111) invalid in your programs. This data may be obtained in case the trigger pulse and
the V-sync (VD) are simultaneous.
Note 3:Make following data invalid in your programs. These data are obtained when the pin voltage of SYNC-IN
pin is higher than sync separation level and while any signal is not input into SYNC-IN pin.
(H FREQUENCY DET, V FREQUENCY DET)
= (0000001, 0001101), (0000001, 0001110), (0000111, 1111111), (0000000, 1111111),
and (0000101, 1111111)
Data 1 and
Start trigger 2
Start trigger 1
Read Timing
Data 2 and
Start trigger 3
More than 60 ms
V-SYNC or VD
Counting period 1
(to Data 1)
Counting period 2
(to Data 2)
Decision algorithm (detection range, detection times and so on) should be determined under
consideration of Note 1, Note 2 and the other factors such as signal strength, existence of ghost signal,
H-AFC stability, I2C BUS data transmission and so on via prototype TV set evaluation.
15
2005-09-08
TA1318NG
2
Data Transfer Format via I C BUS
Slave Address: D8/DA/DCH
A6
A5
A4
A3
A2
A1
A0
W/R
1
1
0
1
1
0/1
0/1
0/1
Start and Stop Condition
SDA
SCL
S
P
Start condition
Stop condition
Bit Transfer
SDA
SCL
SDA stable
Change of SDA allowed
Acknowledge
SDA by transmitter
Bit 9: High impedance
SDA by receiver
Only bit 9: Low impedance
SCL from master
1
8
9
S
Clock pulse for acknowledgment
16
2005-09-08
TA1318NG
Data Transmit Format 1
S
Slave address
7 bit
0 A
MSB
S: Start condition
Sub address
8 bit
A
Transmit data
8 bit
A P
MSB
MSB
A: Acknowledge
P: Stop condition
Data Transmit Format 2
S
Slave address
0 A
Sub address
･･････
A
Transmit data
Sub address
A
･･････
A
Transmit data n
A P
Data Receive Format
S
Slave address
7 bit
1 A
Received data 1
8 bit
A
Received data 2
A P
MSB
MSB
At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave
transmitter. This acknowledge is still generated by this slave.
The Stop condition is generated by the master.
(* important) The data read from THIS IC should always be completed in whole two words, not one word,
otherwise the IICBUS may cause error.
Optional Data Transmit Format: Automatic Increment Mode
S
Slave address
7 bit
0 A 1
MSB
Sub address
7 bit
A
････
Transmit data 1
8 bit
MSB
MSB
Transmit data 2
8 bit
A P
MSB
In this transmission method, data is set on automatically incremented sub-address from the specified
sub-address.
I2C BUS Conditions
Characteristics
Symbol
Min
Typ.
Max
Unit
Low level input voltage
VIL
0
⎯
1.5
V
High level input voltage
VIH
3.0
⎯
Vcc
V
VOL1
0
⎯
0.4
V
Ii
−10
⎯
10
µA
Low level output voltage at 3 mA sink current
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Capacitance for each I/O pin
SCL clock frequency
Hold time START condition
Low period of SCL clock
Ci
⎯
⎯
10
pF
fSCL
0
⎯
100
kHz
tHD;STA
4.0
⎯
⎯
µs
tLOW
4.7
⎯
⎯
µs
tHIGH
4.0
⎯
⎯
µs
Set-up time for a repeated START condition
tSU;STA
4.7
⎯
⎯
µs
Data hold time
tHD;DAT
280
⎯
⎯
ns
Data set-up time
tSU;DAT
250
⎯
⎯
ns
Set-up time for STOP condition
tSU;STO
4.0
⎯
⎯
µs
tBUF
4.7
⎯
⎯
µs
High period of SCL clock
Bus free time between a STOP and START condition
17
2005-09-08
TA1318NG
Maximum Ratings (Ta = 25°C)
Characteristics
Supply voltage
Symbol
Rating
Unit
VCCmax
12
V
Vin
GND − 0.3~
VCC + 0.3
V
Input pin voltage
Power dissipation
1250
mW
Power dissipation reduction rate
1/Qja
PD (*1)
−10
mW/°C
Operating temperature
Topr
−20~65
°C
Storage temperature
Tstg
−55~150
°C
Note: Refer to the figure below.
Power consumption reduction ratio
PD (mW)
1250
10 mW/°C
850
0
0
25
65
Ambient temperature
150
Ta
(°C)
Figure PD - Ta Curve
Operating Conditions
Characteristics
Description
Min
Typ.
Max
Unit
V
Power supply voltage (VCC)
Pin 8
8.5
9.0
9.5
HD1, HD2, HD3 Input level
Pin 3, 1, 11
2.0
5.0
9.0
VD1, VD2, VD3 Input level
Pin 4, 2, 10
2.0
5.0
9.0
Pin 11
0.02
⎯
0.20
H
Frequency
detection
Pin 11
0.45
µs
⎯
0.25H
⎯
Synchronization
Pin 10
1 µs
⎯
47H
⎯
Frequency
detection
Pin 10
1
⎯
400
µs
Vp-p
Synchronization
HD3 input width
VD3 input width
Vp-p
SYNC1, SYNC2 Input level
Pin 21, 19, white 100% with negative sync
0.9
1.0
1.1
HD1, HD2, VD1, VD2-OUT
Input current
Pin 13, 15, 22, 23
⎯
0.9
1.5
DAC3 Input current
Pin 24
⎯
0.5
1.0
0
1.0
Pin 18
D8/D9H
0
Address switching voltage
DC/DDH
8.0
9.0
9.0
mA
18
V
2005-09-08
TA1318NG
Electrical Characteristics (VCC = 9 V, Ta = 25°C, unless otherwise specified)
Current Dissipation
Pin Name
Symbol
Test
Circuit
Min
Typ.
Max
Unit
VCC
ICC
⎯
32
38
44
mA
Symbol
Test
Circuit
S1PH
⎯
S2PH
⎯
HD3PH
⎯
HD-DUTY1
⎯
HD-DUTY2
⎯
VthS10
AC Characteristics
Horizontal Block
Characteristics
Sync1/2 input horizontal sync phase
HD3 input horizontal sync phase
Polarity distinction active range
Sync1 input threshold amplitude
Sync2 input threshold amplitude
HD3 input threshold amplitude
(Synchronization block)
HD1 input threshold voltage
HD2 input threshold voltage
HD3 input threshold voltage
(SW block)
HD output phase adjustment variable
range
Clamp pulse phase/width/level
Min
Typ.
Max
0.6
0.7
0.8
0.6
0.7
0.8
0.6
0.7
0.8
61
66
71
48
53
58
⎯
0.040
0.070
0.100
VthS11
⎯
0.060
0.106
0.152
VthS12
⎯
0.081
0.142
0.203
VthS13
⎯
0.102
0.178
0.255
VthS20
⎯
0.040
0.070
0.100
VthS21
⎯
0.060
0.106
0.152
VthS22
⎯
0.081
0.142
0.203
VthS23
⎯
0.102
0.178
0.255
VthHD3
⎯
0.65
0.75
0.85
VthHD1
⎯
0.65
0.75
0.85
VthHD2
⎯
0.65
0.75
0.85
VthHD3
⎯
0.65
0.75
0.85
∆HP0−
⎯
2.86
3.18
3.49
∆HP0+
⎯
2.86
3.18
3.49
∆HP1−
⎯
1.43
1.59
1.75
∆HP1+
⎯
1.43
1.59
1.75
∆HP2−
⎯
1.33
1.48
1.63
∆HP2+
⎯
1.33
1.48
1.63
∆HP3−
⎯
1.00
1.11
1.22
∆HP3+
⎯
1.00
1.11
1.22
CPS0
⎯
0.85
1.00
1.15
CPW0
⎯
0.65
0.80
0.95
CPV0
⎯
4.7
5.0
5.3
0.35
0.50
0.65
0.65
0.80
0.95
4.7
5.0
5.3
CPS1
⎯
CPW1
⎯
CPV1
⎯
Test Condition
(Note HA01)
(Note HA02)
(Note HA03)
(Note HA06)
(Note HA07)
(Note HA08)
CPS3
⎯
0
⎯
1
CPW3
⎯
0.50
0.90
1.30
CPV3
⎯
4.7
5.0
5.3
19
µs
µs
%
(Note HA04)
(Note HA05)
Unit
Vp-p
Vp-p
Vp-p
µs
µs
V
µs
V
µs
V
2005-09-08
TA1318NG
Characteristics
Delayed HD pulse width
Symbol
Test
Circuit
Typ.
Max
Unit
µs
Wd-HD
⎯
1.0
1.2
1.4
⎯
4.5
5.0
5.5
V13TL0
⎯
⎯
0.1
0.5
V13TH1
⎯
4.5
5.0
5.5
V13TL1
⎯
⎯
0.1
0.5
V13TH2
⎯
4.5
5.0
5.5
(Note HA09)
⎯
V
V13TL2
⎯
⎯
0.1
0.5
V13TH3
⎯
4.5
5.0
5.5
V13TL3
⎯
⎯
0.1
0.5
V15TH0
⎯
4.5
5.0
5.5
V15TL0
⎯
⎯
0.1
0.5
V15TH1
⎯
4.5
5.0
5.5
V15TL1
⎯
⎯
0.1
0.5
V15TH2
⎯
4.5
5.0
5.5
V15TL2
⎯
⎯
0.1
0.5
V15TH3
⎯
4.5
5.0
5.5
V15TL3
⎯
⎯
0.1
0.5
V13IH0
⎯
4.5
5.0
5.5
V13IL0
⎯
⎯
0.1
0.5
V13IH1
⎯
4.5
5.0
5.5
V13IL1
⎯
⎯
0.1
0.5
V13IH2
⎯
4.5
5.0
5.5
V13IL2
⎯
⎯
0.1
0.5
V13IH3
⎯
4.5
5.0
5.5
V13IL3
⎯
⎯
0.1
0.5
V15IH0
⎯
4.5
5.0
5.5
HD2 output voltage
HD1 output voltage (polarity inverse)
⎯
⎯
V
V
V15IL0
⎯
⎯
0.1
0.5
V15IH1
⎯
4.5
5.0
5.5
V15IL1
⎯
⎯
0.1
0.5
V15IH2
⎯
4.5
5.0
5.5
HD2 output voltage (polarity inverse)
⎯
V
V15IL2
⎯
⎯
0.1
0.5
V15IH3
⎯
4.5
5.0
5.5
V15IL3
⎯
⎯
0.1
0.5
ID1
⎯
310
385
460
ID2
⎯
310
385
460
520
650
780
520
650
780
3.9
4.2
4.5
1.4
1.8
2.2
1.4
1.8
2.2
1.4
1.8
2.2
1.4
1.8
2.2
AFC phase detection current
HD output pulse width
(free-run)
Min
V13TH0
HD1 output voltage
VCO oscillation start voltage
Test Condition
ID3
⎯
ID4
⎯
VVCO
⎯
TH00
⎯
TH01
⎯
TH10
⎯
TH11
⎯
(Note HB01)
(Note HB02)
(Note HB03)
20
µA
V
µs
2005-09-08
TA1318NG
Characteristics
Horizontal free-run frequency
Horizontal oscillation control
sensitivity
DAC1 output voltage
DAC2 output voltage
DAC3 output voltage
Symbol
Test
Circuit
F00
F01
F10
⎯
F11
⎯
44.55
45
45.45
F50
⎯
15.47
15.625
15.78
BH00
⎯
2.4
3.0
3.6
BH01
⎯
4.8
6.0
7.2
BH10
⎯
4.8
6.0
7.2
BH10
⎯
7.1
8.9
10.7
VDAC10
⎯
0.5
1.0
1.5
VDAC11
⎯
2.7
3.0
3.3
VDAC12
⎯
4.7
5.0
5.3
VDAC13
⎯
6.5
7.0
7.5
VDAC20
⎯
0.5
1.0
1.5
VDAC21
⎯
2.7
3.0
3.3
VDAC22
⎯
4.7
5.0
5.3
Test Condition
Min
Typ.
Max
⎯
15.59
15.75
15.91
⎯
31.19
31.5
31.82
33.41
33.75
34.09
(Note HB04)
(Note HB05)
⎯
⎯
V
V
VDAC23
⎯
6.5
7.0
7.5
⎯
⎯
0.5
0.7
VDAC31
⎯
8.5
8.8
⎯
21
kHz
kHz/V
VDAC30
⎯
Unit
V
2005-09-08
TA1318NG
Vertical Block
Characteristics
VD1 input threshold voltage
VD2 input threshold voltage
VD3 input threshold voltage
(SW block)
VD3 input threshold voltage
(synchronization block)
Symbol
Test
Circuit
VthVD1
⎯
VthVD2
⎯
VthVD3
⎯
VthVD3
⎯
V22TH0
⎯
(Note VA01)
(Note VA02)
Min
Typ.
Max
0.65
0.75
0.85
0.65
0.75
0.85
0.65
0.75
0.85
0.65
0.75
0.85
4.5
5.0
5.5
V22TL0
⎯
⎯
0.1
0.5
V22TH1
⎯
4.5
5.0
5.5
V22TL1
⎯
⎯
0.1
0.5
V22TH2
⎯
4.5
5.0
5.5
VD1 output voltage
⎯
V22TL2
⎯
⎯
0.1
0.5
⎯
4.5
5.0
5.5
V22TL3
⎯
⎯
0.1
0.5
V23TH0
⎯
4.5
5.0
5.5
V23TL0
⎯
⎯
0.1
0.5
V23TH1
⎯
4.5
5.0
5.5
V23TL1
⎯
V23TH2
⎯
⎯
0.1
0.5
4.5
5.0
5.5
V23TL2
⎯
⎯
0.1
0.5
V23TH3
⎯
4.5
5.0
5.5
V23TL3
⎯
⎯
0.1
0.5
V22IH0
⎯
4.5
5.0
5.5
V22IL0
⎯
⎯
0.1
0.5
V22IH1
⎯
4.5
5.0
5.5
V22IL1
⎯
⎯
0.1
0.5
V22IH2
⎯
4.5
5.0
5.5
VD1 output voltage (polarity inverse)
⎯
⎯
⎯
⎯
0.1
0.5
⎯
4.5
5.0
5.5
V22IL3
⎯
⎯
0.1
0.5
V23IH0
⎯
4.5
5.0
5.5
V23IL0
⎯
⎯
0.1
0.5
V23IH1
⎯
4.5
5.0
5.5
V23IL1
⎯
⎯
0.1
0.5
V23IH2
⎯
4.5
5.0
5.5
V23IL2
⎯
⎯
0.1
0.5
V23IH3
⎯
4.5
5.0
5.5
V23IL3
⎯
⎯
0.1
0.5
VPW0
⎯
251
286
321
VPW1
⎯
126
143
160
VPW2
⎯
117
133
150
VPW3
⎯
88
100
112
V
(Note VA03)
22
Vp-p
V
V22IL2
⎯
Vp-p
V
V22IH3
VD2 output voltage (polarity inverse)
Unit
V
V22TH3
VD2 output voltage
Vertical output pulse width
Test Condition
µs
2005-09-08
TA1318NG
Characteristics
Vertical free-run frequency
Symbol
Test
Circuit
FV0
FV1
Min
Typ.
Max
⎯
26.02
26.35
26.67
⎯
39.21
39.75
40.30
FV3
⎯
52.20
52.98
53.77
FV4
⎯
54.24
55.06
55.89
FV5
⎯
91.28
92.98
94.69
FV6
⎯
107.8
109.9
112.1
FV20
⎯
57.0
60.0
63.0
FV21
⎯
57.0
60.0
63.0
FV22
⎯
57.0
60.0
63.0
(Note VA04)
FV23
⎯
57.0
60.0
63.0
FVPL0
⎯
311
321
332
FVPL1
⎯
624
643
663
668
689
710
Vertical pull-in range
Sync input-VD output phase
difference
Test Condition
FVPL2
⎯
(Note VA05)
FVPL3
⎯
891
918
947
⎯
9.6
11.8
14.0
31.50 kHz
⎯
5.7
6.8
7.9
33.75 kHz
⎯
5.3
6.4
7.5
45.00 kHz
⎯
4.4
5.2
6.0
23
Hz
Hz
15.75 kHz
⎯
Unit
µs
2005-09-08
TA1318NG
Test Conditions and Measuring Method
Note
HA01
SW Mode
Item
Sync1/2 input horizontal sync phase
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
a
b
(1)
↓
↓
(2)
SW19-a and SW21-b.
b
a
(3)
Input Signal a (horizontal 33.75 kHz ) to pin 21 (SYNC1-IN).
Set sub-address (02) 60.
(4)
Set sub-address (02) 61.
(5)
Measure the phase difference S1PH between pin 21 and pin 6 (AFC filter) wave form.
(6)
SW19-b and SW21-a.
(7)
Input Signal a (33.75 kHz ) to pin 19 (SYNC2-IN).
(8)
Set sub-address (02) 01.
(9)
Measure the phase difference S2PH between pin 19 and pin 6 (AFC filter) wave form.
29.63 µs
0.593 µs
Signal a
0.285 V
S1PH･S2PH
Pin 6 wave form
24
2005-09-08
TA1318NG
Note
HA02
SW Mode
Item
HD3 input horizontal sync phase
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
Set sub-address (00) 40 and (02) 82.
(2)
Input signal b (horizontal 31.5 kHz ) to pin 11 (HD3-IN).
(3)
Measure the phase difference HD3PH between pin 11 and pin 6 (AFC filter) wave form.
31.75 µs
2.35 µs
Signal b
1.5 V
HD3PH
Pin 6 wave form
HA03
Polarity distinction active range
c
b
⎯
⎯
(1)
Set sub-address (00) 70 and (02) 82.
(2)
Input signal b ((horizontal 31.5 kHz ) to pin 11 (HD3-IN).
(3)
Decreasing the duty of signal b to 0% (get negative period shorter), measure the duty of Signal b
(HD-DUTY1) when the phase between pin 11 and pin 13 (HD1-OUT) change.
(4)
Increasing the duty of Signal b to 100% (get negative period longer), measure the duty of Signal b
(HD-DUTY2) when the phase between pin 11 and pin 13 (HD1OUT) change.
31.75 µs
2.35 µs
Signal b
1.5 V
B
A
* duty = A/(A + B) × 100 (%)
25
2005-09-08
TA1318NG
Note
HA04
SW Mode
Item
Sync1 input threshold amplitude
Sync2 input threshold amplitude
S06
S18
c
b
S19
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S21
a
b
(1)
Set sub-address (00) 0B and (02) 60.
↓
↓
(2)
Input Signal a (33.75 kHz) to pin 21 (SYNC1-IN)
b
a
(3)
Measure the sync. tip DC voltage of signal a on pin 21 (SYNC1-IN). (Vsync11)
(4)
Supply external voltage via 100 kΩ to pin 21 and increase the voltage.
(5)
Measure the sync. tip DC voltage (Vsync12) when HD-OUT desynchronizes with signal a calculate VthS10.
VthS10 = Vsync12 − Vsync11
(6)
Set sub-address (00) B1, B2 and B3 and calculate VthS11, VthS12 and VthS13 as well.
(7)
Calculate VthS20, VthS21, VthS22 and VthS23 against pin 19 (SYNC2-IN) in the same way as 4 to 6.
29.63 µs
0.593 µs
Signal a
HA05
HD3 input threshold amplitude
(synchronization block)
c
b
⎯
⎯
0.285 V
(1)
Set sub-address (00) 70 and (02) 62.
(2)
Input Signal b (31.5 kHz) to pin 11 (HD3-IN).
(3)
Increasing the voltage of Signal b from 0 V, measure the voltage of Signal b VthHD3 when HD1-OUT lock.
31.75 µs
2.35 µs
Signal b
26
VthHD1
2005-09-08
TA1318NG
Note
HA06
SW Mode
Item
HD1 input threshold voltage
HD2 input threshold voltage
HD3 input threshold voltage
(SW block)
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
Set sub-address (00) 40.
(2)
Input Signal b (31.5 kHz) to pin 3 (HD1-IN).
(3)
Increasing the voltage of Signal b from 0 V, measure the voltage of Signal b VthHD1 when HD1-OUT lock.
(4)
Measure the voltage of pin 1 VthHD2. Measure the voltage of pin 11 VthHD3 as well.
31.75 µs
2.35 µs
Signal b
27
VthHD1
2005-09-08
TA1318NG
Note
HA07
SW Mode
Item
HD output phase adjustment variable
range
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
Set sub-address (00) 30.
(2)
Input Signal b (horizontal period T = 63.5 µs) to pin 11 (HD3-IN).
(3)
Set sub-address (02) 02.
(4)
Change form 00 to 7C sub-address (03), then measure the phase change quantity (∆HP0−) of pin 13
(HD1-OUT) wave form.
(5)
Change form 80 to FC sub-address (03), then measure the phase change quantity (∆HP0+) of pin 13
(HD1-OUT) wave form.
(6)
When horizontal period of Signal b is T = 31.75 µs measure ∆HP1− and ∆HP1+ as well.
(7)
When horizontal period of Signal b is T = 29.63 µs measure ∆HP2− and ∆HP2+ as well.
(8)
When horizontal period of Signal b is T = 22.22 µs measure ∆HP3− and ∆HP3+ as well.
T µs
2.35 µs
Signal b
1.5 V
Pin 15 wave form
data (00)
∆HP*−
Pin 15 wave form
data (7C) (80)
∆HP*+
Pin 15 wave form
data (FC)
28
2005-09-08
TA1318NG
Note
HA08
SW Mode
Item
Clamp pulse phase/width/level
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
Set sub-address (00) B0.
(2)
Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN).
(3)
Set sub-address (02) 02.
(4)
Measure the clamp pulse phase (CPS0), width (CPW0), output level (CPV0) of pin 12 (CLP-OUT) against
Signal a.
(5)
Set sub-address (02) 12.
(6)
Measure the clamp pulse phase (CPS1), width (CPW1), output level (CPV1) of pin 12 (SCP-OUT) against
Signal a.
(7)
Input no-signal to pin 11.
(8)
Measure the clamp pulse phase (CPS2), width (CPW2), output level (CPV2) of pin 12 (SCP-OUT) against pin
13 (HD-OUT).
29.63 µs
2.35 µs
Signal a
1.5 V
CPS0･CPS1
CPV0･CPV1
Pin 12 wave form
CPW0･CPW1
Pin 13 wave form
CPS3
Pin 12 wave form
CPV3
CPW3
29
2005-09-08
TA1318NG
Note
HA09
SW Mode
Item
Delayed HD pulse width
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
Set sub-address (00) 70.
(2)
Input Signal b (horizontal 31.5 kHz) to pin 11 (HD3-IN).
(3)
Set sub-address (02) 62.
(4)
Measure the pulse width (WdHD) of pin 6 (AFC filter) wave form.
31.75 µs
2.35 µs
Signal b
1.5 V
Wd-HD
Pin 6 wave form
30
2005-09-08
TA1318NG
Note
HB01
SW Mode
Item
AFC phase detection current
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
OPEN
b
a
b
(1)
BUS control data preset.
(2)
Horizontal oscillation frequency is 15.75 kHz (00).
(3)
SW6 open. Measure the Voltage of pin 6 V6 (no external supply).
(4)
Connect external supply with pin 6, and supply the voltage (V6).
(5)
Input signal (below figure) to pin 21 (SYNC1-IN). When INPUT SW is SYNC1-IN , measure V1 and V2 of pin
6 wave form.
(6)
Supply V6 − 0.1 V and V6 + 0.1 V to pin 6, then measure V3 and V4.
(7)
Calculate by following equations.
ID1 [µA] = (V1 [V] ÷ 1 [kΩ]) × 1000
ID2 [µA] = (V2 [V] ÷ 1 [kΩ]) × 1000
ID3 [µA] = (V3 [V] ÷ 1 [kΩ]) × 1000
ID4 [µA] = (V4 [V] ÷ 1 [kΩ]) × 1000
63.5 µs
Pin 21 wave form
0.25 V
V1, V3
Pin 6 wave form
HB02
VCO oscillation start voltage
⎯
⎯
⎯
⎯
(1)
V2, V4
Increasing the voltage of pin 8 VCC form 2.5V, measure the voltage VVCO when pin 7 appear oscillation
wave form.
31
2005-09-08
TA1318NG
Note
HB03
SW Mode
Item
HD output pulse width
(free-run)
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
BUS control data preset.
(2)
When horizontal oscillation frequency is 15.75 kHz (00), measure the output pulse width TH00 of pin 13
(HD1-OUT) wave form.
(3)
When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), measure the output
pulse width TH01, TH02, TH03 as well.
Pin 13 (HD1OUT)
wave form
TH
HB04
HB05
Horizontal free-run frequency
OPEN
Horizontal oscillation control sensitivity OPEN
b
b
⎯
⎯
⎯
⎯
(1)
BUS control data preset.
(2)
SW6 open. When horizontal oscillation frequency is 15.75 kHz (00), measure the oscillation frequency F00 of
pin 13 (HD1-OUT) wave form.
(3)
When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), measure the oscillation
frequency F01, F10, F11 as well.
(4)
When horizontal oscillation frequency is 15.75 kHz (00) and vertical free-run frequency is (101), measure the
oscillation frequency F50 of pin 15 wave form.
(1)
BUS control data preset.
(2)
SW6 open.
(3)
Connect external voltage with pin 6 . Horizontal oscillation frequency is 15.75 kHz (00). Supply V6 (about 6.3
V) + 0.05 V or V6 − 0.05 V to pin 6, then measure the frequency FA, FB of pin 13 (HD1-OUT) wave form.
Calculate frequency changing ratio (BH00). BH00 = (FB − FA)/0.1
(4)
When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), calculate BH01, BH10,
BH11 as wall.
32
2005-09-08
TA1318NG
Note
VA01
SW Mode
Item
VD1 input threshold voltage
VD2 input threshold voltage
VD3 input threshold voltage
(SW block)
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
Set sub-address (00) 80.
(2)
Input Signal a (vertical 60 Hz) to pin 4 (VD1-IN).
(3)
Set sub-address (02) 00.
(4)
Increasing the voltage of Signal a from 0 V. measure the voltage of Signal b VthVD1 when VD1-OUT lock.
(5)
Measure VthVD2 and VthVD3 against pin 2 and pin 10 as wall.
16.67 ms
0.12 ms
Signal a
VA02
VD3 input threshold voltage
(synchronization block)
c
b
⎯
⎯
VthVD1
(1)
Set sub-address (00) 70.
(2)
Input Signal b (vertical 60 Hz) to pin 10 (VD3-IN).
(3)
Set sub-address (02) 03.
(4)
Increasing the voltage of Signal b from 0 V, measure the voltage of Signal a VthVD3 when VD1-OUT lock.
16.67 ms
0.12 ms
Signal a
33
2005-09-08
TA1318NG
Note
VA03
SW Mode
Item
Vertical output pulse width
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN).
(2)
Set sub-address (02) 02.
(3)
When sub-addrss (00) is B0, measure the pulse width VPW2 of pin 22 (VD1-OUT) wave form.
(4)
When sub-addrss (00) is 30, 70, F0, measure the pulse width VPW0, VPW1, VPW3 of pin 22 (VD1-OUT)
wave form as well.
29.63 µs
0.593 µs
Signal a
V period
Pin 22 wave form
VPW*
34
2005-09-08
TA1318NG
Note
VA04
SW Mode
Item
Vertical free-run frequency
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN).
(2)
Set sub-address (00) B0.
(3)
When sub-address (02) is 02, 22, 62, 82, A2 or C2, measure the frequency FV0, FV1, FV3, FV4, FV5 or FV6
of pin 22 (VD1-OUT) wave form.
(4)
Input no-signal to pin 3 (HD1-IN).
(5)
Set sub-address (02) 42.
(6)
When sub-address (00) is 30, 70, B0 or F0, measure the frequency FV20, FV21, FV22 or FV23 of pin 22
(VD1-OUT) wave form.
29.63 µs
0.593 µs
Signal a
0.285 V
V period
Pin 22 wave form
VPW*
35
2005-09-08
TA1318NG
Note
VA05
SW Mode
Item
Vertical pull-in range
Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
S06
S18
S19
S21
c
b
⎯
⎯
(1)
Input Signal a (horizontal period T = 63.5 µs) to pin 11 (HD3-IN).
(2)
Set sub-address (02) 02.
(3)
Set sub-address (00) 30.
(4)
Input Signal C (vertical period initial T = 1ms) to pin 10 (VD3-IN). Increasing vertical period of Signal C,
measure the frequency FVPL0 when pin 22 (VD1-OUT) wave form synchronize with Signal C.
(5)
Input Signal a (horizontal period T = 31.75 µs) to pin 11 (HD3-IN).
(6)
Set sub-address (00) 70.
(7)
Measure FVPL1 as well.
(8)
Input Signal a (horizontal period T = 29.63 µs) to pin 11 (HD3-IN).
(9)
Set sub-address (00) B0.
(10) Measure FVPL2 as well.
(11) Input Signal a (horizontal period T = 22.22 µs) to pin 11 (HD3-IN).
(12) Set sub-address (00) F0.
(13) Measure FVPL3 as well.
horizontal period Tµs
0.593 µs
Signal a
1.5 V
V period (initial T = 1 ms)
0.25 ms
Signal c
1.5 V
measuring period
Pin 22 wave form
36
2005-09-08
Pin 1
Pin 2
Pin 3
Pin 4
1 kΩ
Pin 6
a
37
7
SW6
b c
Pin 7
#7
8
9
#9
Pin 9
10
#10
Pin 10
5.1 kΩ
14
11
#11
Pin 11
#13
3.9 kΩ
13
75 Ω
5.1 kΩ
1 kΩ
REG.
75 Ω
5.1 kΩ
c
5.1 kΩ
100 Ω
#15
1 kΩ
HD1-OUT
15
CP-OUT
DIGITAL GND
100 Ω
#16
HD3-IN
16
HD2-OUT
17
VD3-IN
SDA
TA1318NG
DAC2
1 µF
3.9 kΩ
0.01 µF
100 µF
0.01 µF
100 Ω
#6
#17
100 Ω
6
18
SCL
19
#18
VCC
100 Ω
SCL
100 Ω
5
Address SW
1 µF
b
SW19
#19
0.01 µF
100 Ω
#4
HVCO
DAC1
SYNC2-IN
20
a b
SW18
100 µF
4
a
360 Ω
#3
AFC Filter
21
SYNC1-IN
5.1 kΩ
Pin 20 SYNC2
CSBLA503
M 0.01 µF
○
KECZF30
3
#20
2.2 µF 7.5 kΩ
#2
b
SW21
#21
Analog GND
22
VD1-OUT
5.1 kΩ
a
68 kΩ
2
VD1-IN
HD1-IN
23
VD2-OUT
SYNC1
10 kΩ
#1
#22
100 Ω
1
#23
100 Ω
VD2-IN
24
DAC3
#24
100 Ω
HD2-IN
0.01 µF
5V
10 kΩ
9V
100 Ω
9V
100 µF
0.01 µF
100 µF
TA1318NG
Test Circuit
TPS1-in
10 µF
SDA
TPS2-in
10 µF
12
#12
Pin 12
M Mylar capacitor
○
2005-09-08
TA1318NG
Application Circuit 1 (Typical values)
10 kΩ
10 kΩ
15
14
13
9
10
11
12
DAC2
VD3-IN
HD3-IN
CP-OUT
HD1-OUT
8
DIGITAL GND
CP-OUT
16
HD3-IN
DAC1
17
VD3-IN
SYNC1-IN
18
SDA
VD1-OUT
19
DAC2
20
SCL
21
HD1OUT
VCC
22
Address SW
23
HD2OUT
SDA
100 Ω
100 Ω
SCL
HD2-OUT
SYNC2IN
1 µF
10 kΩ
24
VD2-OUT
10 kΩ
DAC1
DAC3
15 kΩ
VD1- SYNC1OUT
IN
SYNC2-IN
VD2OUT
DAC3
1 µF
0.01 µF
VD2-IN
HD1-IN
VD1-IN
Analog GND
AFC Filter
HVCO
TA1318NG
HD2-IN
1
2
3
4
5
6
7
VD2-IN
HD1-IN
VD1-IN
2.2 µF
HD2-IN
7.5 kΩ
360 Ω
M 0.01 µF
○
100 µF
9V
38
0.01 µF
100 µF
CSBLA503
KECZF30
M Mylar capacitor
○
2005-09-08
TA1318NG
Application Circuit 2 (How to measure H/V frequency)
To measure H/V frequency of signal 2 (fH2: unknown) correctly, use two separated input terminals as the
following figure. One is for frequency measuring (SYNC2-in) and the other is for the AFC (SYNC1-IN). And
measure H/V frequency of signal 2 (fH2: unknown) on condition that AFC is stable (AFC locks in signal 1 (fH1:
known).) or that AFC is free-run when SYNC1-IN is no-signal.
Signal 1
(fH1: known)
Signal 2
(fH2: unknown)
Signal 1
AFC
SYNC1-IN
for H-AFC
BUS READ
Internal pulse (A)
H/V FREQ
COUNTER
Signal 2
SYNC2-IN
for
H/V freq. counter
TA1318NG
This IC’s H/V frequency counting is done by internal pulse (A) which is made in AFC circuit. So, if AFC circuit
doesn’t lock in the regular frequency, the frequency of pulse (A) will not be correct and the H/V frequency data will
not be showed correct data.
Decision algorithm of H/V frequency detection (detection range, detection times and so on) should be determined
under consideration the factors such as signal strength, existence of ghost signal, H-AFC stability, I2C BUS data
transmission and so on via prototype TV set evaluation.
39
2005-09-08
TA1318NG
Package Dimensions
Weight: 1.22 g (typ.)
40
2005-09-08
TA1318NG
41
2005-09-08