TA1318AF TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic TA1318AF SYNC Processor, Frequency Counter IC for TV Component Signals TA1318AF is a sync processor for TV component signals. TA1318AF provides sync and frequency counter processing for external input signals. These functions are integrated in a 30 pin SSOP-type plastic package. TA1318AF provides I2C bus interface, so various functions and controls are adjustable via the bus. Features Weight: 0.63 g (typ.) • Horizontal synchronization circuit (15.75 kHz, 31.5 kHz, 33.75 kHz, 45 kHz) • Vertical synchronization circuit (525I, 525P, 625I, 750P, 1125I, 1125P, PAL 100 Hz, NTSC 120 Hz) • Horizontal and vertical frequency counter • Horizontal PLL • Accepts 2-level and 3-level sync • Accepts both negative and positive HD and VD • Clamp pulse output • HD, VD output (polarity inverter) • Separated sync output • Mask for the copy guard signal 1 2003-02-19 TA1318AF Block Diagram DAC3 VD2-OUT VD1-OUT NC SYNC1-IN DAC1 30 29 28 27 26 25 24 DAC3 SW INV SW INV SW SYNC SEPA DAC1 SW SYNC SEPA DV2-OUT SW DV1-OUT SW TEST DAC3 SYNC2-IN Address SW 23 SCL SDA NC 22 21 20 2 I CBUS Decoder DAC1 V-Input SW H/VFREQ Counter V-SYNC V C/D 18 19 NC HD1-OUT 17 16 INV SW INV SW HD2-OUT SW HD1-OUT SW V-FREQ SW V-FREQ DET SW Clamp Pulse DAC2 DAC2 SW H/CSYNK HD2-OUT Digital GND V Integral H-FREQ DET SW CP SW HD 2 × fH Polarity H-INPUT SW H-AFC H C/D H-Ramp H-FREQ SW HVCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HD2-IN VD2-IN HD1-IN VD1-IN Analog GND NC AFC Filter NC HVCO NC VCC DAC2 VD3-IN HD3-IN CP-OUT 2 2003-02-19 TA1318AF Pin Functions Pin No. Pin Name Function Interface Circuit 11 Input Signal/Output Signal Th: 0.7 V Input horizontal sync signal. 1 HD2-IN It accepts input of both positive and negative polarity. 1 or 50 kΩ Input signal from this pin is not synchronized. 1 kΩ Th: 0.7 V 5 11 Th: 0.7 V Input vertical sync signal. VD2-IN It accepts input of both positive and negative polarity. Input signal from this pin is not synchronized. 2 1 kΩ or 45 kΩ 2 Th: 0.7 V 5 3 2003-02-19 TA1318AF Pin No. Pin Name Function Interface Circuit 11 Input Signal/Output Signal Th: 0.7 V Input horizontal sync signal. 3 HD1-IN It accepts input of both positive and negative polarity. 3 or 50 kΩ Input signal from this pin is not synchronized. 1 kΩ Th: 0.7 V 5 11 Th: 0.7 V Input vertical sync signal. VD1-IN It accepts input of both positive and negative polarity. Input signal from this pin is not synchronized. 4 1 kΩ or 45 kΩ 4 Th: 0.7 V 5 5 Analog GND GND pin for analog circuit blocks. 6 N.C. Connect to GND. 4 2003-02-19 TA1318AF Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 11 7 AFC Filter Connect filter for horizontal AFC. Voltage on this pin determines horizontal output frequency. 300 Ω 7 DC 30 kΩ 5 8 N.C. Connect to GND. 11 4 kΩ Use Murata CSBLA503KECZF30. 9 1 kΩ HVCO 2 kΩ 9 Connect ceramic oscillator for horizontal oscillation. 1 kΩ 10 kΩ 5 10 N.C. 11 VCC Connect to GND. VCC pin. Connect 9 V (typ.). 5 2003-02-19 TA1318AF Pin No. Pin Name Function In Test mode, it outputs HD or composite sync signal to frequency counter. DAC2 (H/C. SYNC output) To improve the driving ability, it is possible to connect a resister (minimum: 2 kΩ) between this pin and GND. However, when the resister is added, the output DC voltage is down. 11 DC 12 or H/C SYNC 7V 200 Ω 30 kΩ 12 Input Signal/Output Signal 500 Ω DAC2 output pin. Interface Circuit 0V 18 11 Input vertical sync signal. VD3-IN It accepts input of both positive and negative polarity. 13 1 kΩ or 45 kΩ 13 Th: 0.7 V Th: 0.7 V 5 11 HD3-IN It accepts input of both positive and negative polarity. 14 1 kΩ or 50 kΩ Input horizontal sync signal. 14 Th: 0.7 V Th: 0.7 V 5 6 2003-02-19 TA1318AF Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 500 Ω 11 5.0 V Clamp pulse (CP) output pin. CP-OUT It outputs CP generated by sync circuit. 15 0V 200 Ω 2.5 kΩ 15 18 11 HD output pin. Open collector output. 16 HD1-OUT HD1/HD2 input signals are output from this pin without synchronization. 16 200 Ω or Polarity is switched by BUS write function. 18 17 N.C. Connect to GND. 18 Digital GND GND pin for logic blocks. 7 2003-02-19 TA1318AF Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 11 HD output pin. Open collector output. 19 HD2-OUT HD1/HD2 input signals are output from this pin without synchronization. 19 or 200 Ω Polarity is switched by BUS write function. 18 20 N.C. Connect to GND. 11 SDA 2 SDA pin for I C bus. 21 50 Ω ACK 20 kΩ SDA 4 VF 21 5 18 8 2003-02-19 TA1318AF Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 11 SCL 2 SCL pin for I C bus. 20 kΩ 22 SCL 4 VF 22 5 15 kΩ 100 kΩ 23 1 kΩ 1.5 V 9 9V 7.5 V DA/DB 100 kΩ When this pin is connected to VCC (GND), used for DC/DDH (D8/D9H); when left open, DA/DBH. 60 kΩ Address SW 15 kΩ 23 DC/DD 7.5 V 100 kΩ Slave address switch pin. 11 D8/D9 1.5 V 0 V 5 2003-02-19 TA1318AF Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal White 100％ = 1 Vp−p 1 kΩ 11 Input Y signal (Note 1) for sync separation circuit. 24 or 1 kΩ 4 VF Input via clamp capacitor. 1 kΩ SYNC2-IN 1 kΩ 24 5 11 500 Ω DAC1 output pin. In Test mode, it outputs VD or composite sync signal to frequency counter. DAC1 (V SYNC output) To improve the driving ability, it is possible to connect a resister (minimum: 2 kΩ) between this pin and GND. However, when the resister is added, the output DC voltage is down. 25 or V SYNC 7V 200 Ω 30 kΩ 25 DC 0V 18 Note 1: The signal format for SYNC1-IN (pin 26) and SYNC2-IN (pin 24) NTSC (525I/60 Hz), PAL/SECAM (625I/50 Hz), NTSC Double Scan (525I/120 Hz), PAL/SECAM Double Scan (625I/100 Hz), 525P/60 Hz, 750P/60 Hz, 1125I/60 Hz, 1125P/30 Hz This IC doesn’t have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on. 10 2003-02-19 TA1318AF Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal White 100％ = 1 Vp−p 1 kΩ 11 Input Y signal (Note 1) for sync separation circuit. 26 or 1 kΩ 4 VF Input via clamp capacitor. 1 kΩ SYNC1-IN 1 kΩ 26 5 27 N.C. Connect to GND. 11 VD output pin. Open collector output. VD1/VD2 input signals are output from this pin without synchronization. 28 VD1-OUT 28 Start phase 200 Ω or Polarity is switched by BUS write function. (Note) When HD PHASE will be changed, synchronized VD width will change. Use the start phase of VD. 18 Start phase Note 1: The signal format for SYNC1-IN (pin 26) and SYNC2-IN (pin 24) NTSC (525I/60 Hz), PAL/SECAM (625I/50 Hz), NTSC Double Scan (525I/120 Hz), PAL/SECAM Double Scan (625I/100 Hz), 525P/60 Hz, 750P/60 Hz, 1125I/60 Hz, 1125P/30 Hz This IC doesn’t have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on. 11 2003-02-19 TA1318AF Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 11 VD output pin. Open collector output. VD1/VD2 input signals are output from this pin without synchronization. 29 VD2-OUT 29 Start phase 200 Ω or Polarity is switched by BUS write function. (Note) When HD PHASE will be changed, synchronized VD width will change. Use the start phase of VD. 18 Start phase 11 DAC3 output pin. 30 DAC3 Open collector output. 30 DC 500 Ω or In Test mode, outputs test pulse for shipping. test pulse for shipping 18 12 2003-02-19 TA1318AF Bus Control Map Write Mode Slave Address: D8/DA/DCH Sub-Add D7 MSB D6 D5 D4 D3 00 H-FREQUENCY HD1/VD1-OUT SW 01 DAC1 DAC2 02 V-FREQUENCY 03 D2 HD2/VD2-OUT SW DAC3 CLP-PHS TEST FREQ DET SW HD PHASE D1 D0 LSB SEPA LEVEL HD1-INV HD2-INV INPUT SW VD1-INV VD2-INV D1 D0 LSB Preset MSB LSB 1000 0000 1000 0000 1000 0000 1000 0000 Read Mode Slave Address: D9/DB/DDH D7 MSB D6 D5 D4 D3 0 POR V FREQUENCY DET 1 HD-IN H FREQUENCY DET D2 Bus Control Functions Write Mode (*: Preset) • • • • • • • • H-FREQUENCY (Horizontal oscillation frequency) Switches horizontal frequency. (00): 15.75 kHz (01): 31.5 kHz *(10): 33.75 kHz (11): 45 kHz HD1/VD1-OUT SW (HD1/VD1 output switch) Switches output from pin 16/28. When set to 00, 01, or 10, outputs HD/VD without synchronization. When set to 11, outputs HD/VD from the sync circuit. (Note) Synchronized VD width will change, when HD PHASE will be changed. *(00): HD1/VD1 (01): HD2/VD2 (10): HD3/VD3 (11): Synchronized HD/VD HD2/VD2-OUT SW (HD2/VD2 output switch) Switches output from pin 19/29. When set to 00, 01, or 10, outputs HD/VD without synchronization. When set to 11, outputs HD/VD from the sync circuit. *(00): HD1/VD1 (01): HD2/VD2 (10): HD3/VD3 (11): Synchronized HD/VD SEPA LEVEL (Sync separation level switch) Switches sync separation level of pin 24/26. Set values are the levels from sync tip. Sync separation level is changed according to the ratio of H-SYNC width during 1H period. *(00): 10IRE (01): 15IRE (10): 20IRE (11): 25IRE (at 1125I/60) DAC1 (DAC1 control) Controls 2-bit DAC (pin 12). (00): 1 V (01): 3 V *(10): 5 V (11): 7 V DAC2 (DAC2 control) Controls 2-bit DAC (pin 25). *(00): 1 V (01): 3 V (10): 5 V (11): 7 V DAC3 (DAC3 control) Controls open collector 1-bit DAC (pin 30). *(0): OPEN (HIGH) (1): ON (LOW) TEST (Test mode) Switches DAC1, 2, and 3 outputs. Also used to test IC for shipping. *(0): DAC outputs are used as DAC. (1): DAC1 outputs V. SYNC to the frequency counter. DAC2 outputs H. SYNC or C. SYNC to the frequency counter. DAC3 outputs IC test pulse for shipping. 13 2003-02-19 TA1318AF • • • HD1-INV (HD1 output polarity switch) Switches HD1 output (pin 16) polarity. When set to 0, positive HD input is output as negative HD. When set to 0, output from the sync circuit is output as negative HD. *(0): Normal (1): Inverse HD2-INV (HD2 output polarity switch) Switches HD1 output (pin 19) polarity. When set to 0, positive HD input is output as negative HD. When set to 0, output from the sync circuit is output as negative HD. *(0): Normal (1): Inverse V-FREQUENCY (Vertical frequency switch (pull-in range)) Sets vertical frequency pull-in range, VD-STOP, or free-running frequency. Free-running frequency is controlled by H-FREQUENCY. Pull-in Range • • • • • • Format/H (V) Frequency *(000) 48~1281 H 1125P/30 Hz (33.75 kHz) (001) 48~849 H 750P/60 Hz (45 kHz) (010) FREE-RUN (011) 48~637 H 1125I/60 Hz (33.75 kHz) (100) 48~613 H 525P/60 Hz (31.5 kHz) (101) 48~363 H PAL/SECAM/50 Hz (15.625 kHz) PAL/SECAM double scan/100 Hz (31.5 kHz) (110) 48~307 H NTSC/60 Hz (15.734 kHz) NTSC double scan /120 Hz (31.5 kHz) (111) VP STOP VD output is HIGH Free-running frequency is controlled by H-FREQUENCY. (00): 262 H (01): 525 H (10): 562 H (11): 750 H CLP PHS (Clamp pulse phase switch) Switches clamp pulse phase. If no signal input, 0.9 µs pulse is output from the H-C/D circuit. *(0): 1 µs (3.4%) delay following HD stop phase, 0.8 µs (2.7%) pulse (1): 0.5 µs (1.7%) delay following HD stop phase, 0.8 µs (2.7%) pulse FREQ DET SW (Horizontal/vertical frequency counter switch) Switches input signal used for horizontal/vertical frequency counter. This switch is controlled independently from INPUT SW. The detection result is output as read BUS data. *(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs INPUT SW (Input signal switch for synchronization) Switches input signal used for synchronization. *(00): SYNC1 input (01): SYNC2 input (10)/(11): HD3/VD3 inputs HD PHASE (HD phase adjustment) Adjusts phase of HD output from the sync circuit. The phase of the adjustment center value is the same as that of input H-SYNC or input HD. (Note) Synchronized VD width will change, when HD PHASE will be changed. (000000) : −5% (H periodically) *(100000) : 0% (111111) : 5% VD1-INV (VD1 output polarity switch) Switches VD1 output (pin 28) polarity. When set to 0, negative VD input is output as negative VD. When set to 0, output from the sync circuit is output as negative VD. *(0): Normal (1): Inverse VD2-INV (VD2 output polarity switch) Switches VD2 output (pin 29) polarity. When set to 0, negative VD input is output as negative VD. When set to 0, output from the sync circuit is output as negative VD. *(0): Normal (1): Inverse 14 2003-02-19 TA1318AF Read Mode • • • • POR (Power on reset) (0): Status read (at second data read and subsequent) (1): Power on (at first data read) HD-IN (Input signal self-check result) Detects HD or H-SYNC input signal selected by INPUT SW. (0): No signal input (1): Signal input V FREQ DET (Vertical frequency of SYNC or VD input selected by FREQ DET SW) (0000000)∼(0001100): No-VD (0001101) : Vicinity of 162 Hz (1111111) : Vicinity of 17 Hz How to calculate vertical frequency (X): Convert V-FREQ DET read data into decimal and define the resulting value as Y. Where H-FREQUENCY is 15.75 kHz/31.5 kHz, Z = 476.2 µs Where H-FREQUENCY is 33.75 kHz/45 kHz, Z = 474.1 µs Vertical frequency (X) = 1 ÷ (Y × Z) [Hz] Error of Y is +1, −0. If vertical frequency is 162 Hz or more, the frequency cannot be accurately measured. Time constant used to separate V.SYNC from integrated C.SYNC is 9 µs (error: ±1 µs). H FREQ DET (Horizontal frequency of SYNC or HD input selected by FREQ DET SW) (0000000): No signal input (1111111): 53 kHz or more How to calculate horizontal frequency (X): X, Y, and Z are defined same as for V FREQ. Horizontal frequency (X) = Y ÷ (5 × Z) [kHz] Error of Y is +1, −0. If horizontal frequency is 53 kHz or more, the frequency cannot be accurately measured. When V-SYNC or VD is not input, horizontal frequency cannot be measured, resulting in data = (0000000). Note: The start trigger for frequency counting is the internal reset-pulse made from ACK of 2nd byte in BUS read mode. The counting period is between the first V-sync (VD) and the second V-sync (VD) after the trigger. The counted data will have +1 or −0 error according to the read timing. To assume stable data reading; 1. Set BUS reading interval more than 3 V. 2. Don’t use the first data because it is unsettled. are recommended. Read Timing Data 1 and Start trigger 2 Start trigger 1 Data 2 and Start trigger 3 More than 3 V V-SYNC or VD Counting period 1 (to Data 1) Counting period 2 (to Data 2) Decision algorithm (detection range, detection times and so on) should be determined under consideration of Note 1, Note 2 and the other factors such as signal strength, existence of ghost signal, H-AFC stability, I2C BUS data transmission and so on via prototype TV set evaluation. 15 2003-02-19 TA1318AF 2 Data Transfer Format via I C BUS Slave Address: D8/DA/DCH A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 1 0/1 0/1 0/1 Start and Stop Condition SDA SCL S P Start condition Stop condition Bit Transfer SDA SCL Change of SDA allowed SDA stable Acknowledge SDA by transmitter Bit 9: High impedance SDA by receiver Only bit 9: Low impedance SCL from master 1 8 9 S Clock pulse for acknowledgment 16 2003-02-19 TA1318AF Data Transmit Format 1 S Slave address 7 bit 0 A MSB S: Start condition Sub address 8 bit A MSB A: Acknowledge Transmit data 8 bit A P MSB P: Stop condition Data Transmit Format 2 S Slave address 0 A Sub address ･･････ A Transmit data Sub address A A ･･････ Transmit data n A P Data Receive Format S Slave address 7 bit MSB 1 A Received data 1 8 bit A Received data 2 A P MSB At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave transmitter. This acknowledge is still generated by this slave. The Stop condition is generated by the master. (* important) The data read from THIS IC should always be completed in whole two words, not one word, otherwise the IICBUS may cause error. Optional Data Transmit Format: Automatic Increment Mode S Slave address 7 bit MSB 0 A 1 MSB Sub address 7 bit A Transmit data 1 8 bit MSB ････ Transmit data 2 8 bit A P MSB In this transmission method, data is set on automatically incremented sub-address from the specified sub-address. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 17 2003-02-19 TA1318AF Maximum Ratings (Ta = 25°C) Characteristics Supply voltage Input pin signal voltage Power dissipation Symbol Rating Unit VCCmax 12 V einmax 9 Vp-p 1136 mW PD (*1) Power dissipation reduction rate 1/θja 9.1 mW/°C Operating temperature Topr −20~65 °C Storage temperature Tstg −55~150 °C Note 1: Refer to the figure below. Note 2: It is possible that this IC function faultily caused by leak problems according to a field intensity from CRT. Put this IC lay-out position to CRT be far more than 20 cm. If there is not enough distance, intercept it by a shield. Note 3: Pins 24 and 26 are susceptible to damage from surge voltages and should be handled with extreme care. Power consumption reduction ratio PD (mW) 1136 773 0 0 25 65 150 Ambient temperature Ta (°C) Figure PD - Ta Curve 18 2003-02-19 TA1318AF Operating Condition Characteristics Description Min Typ. Max Unit V Power supply voltage (VCC) Pin 11 8.5 9.0 9.5 HD1, HD2, HD3 Input level Pin 3, 1, 14 2.0 5.0 9.0 VD1, VD2, VD3 Input level Pin 4, 2, 13 2.0 5.0 9.0 HD3 input width VD3 input width Synchronization Pin 14 Frequency detection Pin 14 Synchronization Pin 13 Frequency detection Pin 13 Vp-p 0.02 0.20 H 0.45 µs 0.25H 1 µs 47H 1 400 µs Vp-p SYNC1, SYNC2 Input level Pin 26, 24, white 100% with negative sync 0.9 1.0 1.1 HD1, HD2, VD1, VD2-OUT Input current Pin 16, 19, 28, 29 0.9 1.5 DAC3 Input current Pin 30 0.5 1.0 Address switching voltage Pin 23 D8/D9H 0 0 1.0 DC/DDH 8.0 9.0 9.0 mA V Note: Pins 24 and 26 are susceptible to damage from surge voltages. Do not connect either of pins to an external input pin directly. When constructing a TV set, please consider to connect an external protection diode or a switch IC between any external input pin and pin 24 or 26. 19 2003-02-19 TA1318AF Electrical Characteristics (VCC = 9 V, Ta = 25°C, unless otherwise specified) Current Dissipation Pin Name Symbol Test Circuit Min Typ. Max Unit VCC ICC 32 38 44 mA Symbol Test Circuit S1PH S2PH HD3PH HD-DUTY1 HD-DUTY2 VthS10 AC Characteristics Horizontal Block Characteristics Sync1/2 input horizontal sync phase HD3 input horizontal sync phase Polarity distinction active range Sync1 input threshold amplitude Sync2 input threshold amplitude HD3 input threshold amplitude (Synchronization block) HD1 input threshold voltage HD2 input threshold voltage HD3 input threshold voltage (SW block) HD output phase adjustment variable range Clamp pulse phase/width/level Test Condition Min Typ. Max 0.6 0.7 0.8 0.6 0.7 0.8 0.6 0.7 0.8 61 66 71 48 53 58 0.040 0.070 0.100 VthS11 0.060 0.106 0.152 VthS12 0.081 0.142 0.203 VthS13 0.102 0.178 0.255 VthS20 0.040 0.070 0.100 VthS21 0.060 0.106 0.152 VthS22 0.081 0.142 0.203 VthS23 0.102 0.178 0.255 VthHD3 0.65 0.75 0.85 VthHD1 0.65 0.75 0.85 VthHD2 0.65 0.75 0.85 (Note HA01) (Note HA02) (Note HA03) (Note HA04) (Note HA05) (Note HA06) VthHD3 0.65 0.75 0.85 ∆HP0− 2.86 3.18 3.49 ∆HP0+ 2.86 3.18 3.49 ∆HP1− 1.43 1.59 1.75 ∆HP1+ 1.43 1.59 1.75 ∆HP2− 1.33 1.48 1.63 ∆HP2+ 1.33 1.48 1.63 ∆HP3− 1.00 1.11 1.22 ∆HP3+ 1.00 1.11 1.22 CPS0 0.85 1.00 1.15 CPW0 0.65 0.80 0.95 CPV0 4.7 5.0 5.3 CPS1 0.35 0.50 0.65 CPW1 0.65 0.80 0.95 CPV1 4.7 5.0 5.3 CPS3 0 1 CPW3 0.50 0.90 1.30 CPV3 4.7 5.0 5.3 (Note HA07) (Note HA08) 20 Unit µs µs % Vp-p Vp-p Vp-p µs µs V µs V µs V 2003-02-19 TA1318AF Characteristics Delayed HD pulse width HD1 output voltage HD2 output voltage HD1 output voltage (polarity inverse) HD2 output voltage (polarity inverse) AFC phase detection current VCO oscillation start voltage HD output pulse width (free-run) Symbol Test Circuit Wd-HD V13TH0 Test Condition Min Typ. Max Unit 1.0 1.2 1.4 µs 4.5 5.0 5.5 V13TL0 0.1 0.5 V13TH1 4.5 5.0 5.5 V13TL1 0.1 0.5 V13TH2 4.5 5.0 5.5 V13TL2 0.1 0.5 V13TH3 4.5 5.0 5.5 V13TL3 0.1 0.5 V15TH0 4.5 5.0 5.5 V15TL0 0.1 0.5 V15TH1 4.5 5.0 5.5 V15TL1 0.1 0.5 V15TH2 4.5 5.0 5.5 V15TL2 0.1 0.5 V15TH3 4.5 5.0 5.5 V15TL3 0.1 0.5 V13IH0 4.5 5.0 5.5 V13IL0 0.1 0.5 V13IH1 4.5 5.0 5.5 V13IL1 0.1 0.5 V13IH2 4.5 5.0 5.5 V13IL2 0.1 0.5 V13IH3 4.5 5.0 5.5 V13IL3 0.1 0.5 V15IH0 4.5 5.0 5.5 V15IL0 0.1 0.5 V15IH1 4.5 5.0 5.5 V15IL1 0.1 0.5 V15IH2 4.5 5.0 5.5 V15IL2 0.1 0.5 V15IH3 4.5 5.0 5.5 V15IL3 0.1 0.5 ID1 310 385 460 ID2 310 385 460 ID3 520 650 780 ID4 520 650 780 VVCO 3.9 4.2 4.5 TH00 1.4 1.8 2.2 TH01 1.4 1.8 2.2 TH10 1.4 1.8 2.2 TH11 1.4 1.8 2.2 (Note HA09) (Note HB01) (Note HB02) (Note HB03) 21 V V V V µA V µs 2003-02-19 TA1318AF Characteristics Horizontal free-run frequency Horizontal oscillation control sensitivity DAC1 output voltage DAC2 output voltage DAC3 output voltage Symbol Test Circuit F00 F01 F10 Test Condition (Note HB04) Min Typ. Max 15.59 15.75 15.91 31.19 31.5 31.82 33.41 33.75 34.09 F11 44.55 45 45.45 F50 15.47 15.625 15.78 BH00 2.4 3.0 3.6 BH01 4.8 6.0 7.2 BH10 4.8 6.0 7.2 BH10 7.1 8.9 10.7 VDAC10 0.5 1.0 1.5 VDAC11 2.7 3.0 3.3 VDAC12 4.7 5.0 5.3 VDAC13 6.5 7.0 7.5 VDAC20 0.5 1.0 1.5 VDAC21 2.7 3.0 3.3 VDAC22 4.7 5.0 5.3 VDAC23 6.5 7.0 7.5 VDAC30 0.5 0.7 VDAC31 8.5 8.8 (Note HB05) 22 Unit kHz kHz/V V V V 2003-02-19 TA1318AF Vertical Block Characteristics VD1 input threshold voltage VD2 input threshold voltage VD3 input threshold voltage (SW block) VD3 input threshold voltage (synchronization block) VD1 output voltage VD2 output voltage VD1 output voltage (polarity inverse) VD2 output voltage (polarity inverse) Vertical output pulse width Symbol Test Circuit VthVD1 VthVD2 VthVD3 VthVD3 V22TH0 Min Typ. Max 0.65 0.75 0.85 0.65 0.75 0.85 0.65 0.75 0.85 0.65 0.75 0.85 4.5 5.0 5.5 V22TL0 0.1 0.5 V22TH1 4.5 5.0 5.5 V22TL1 V22TH2 V22TL2 Test Condition (Note VA01) (Note VA02) 0.1 0.5 4.5 5.0 5.5 0.1 0.5 V22TH3 4.5 5.0 5.5 V22TL3 0.1 0.5 V23TH0 4.5 5.0 5.5 V23TL0 0.1 0.5 V23TH1 4.5 5.0 5.5 V23TL1 0.1 0.5 V23TH2 4.5 5.0 5.5 V23TL2 0.1 0.5 V23TH3 4.5 5.0 5.5 V23TL3 0.1 0.5 V22IH0 4.5 5.0 5.5 V22IL0 0.1 0.5 V22IH1 4.5 5.0 5.5 V22IL1 V22IH2 V22IL2 0.1 0.5 4.5 5.0 5.5 0.1 0.5 V22IH3 4.5 5.0 5.5 V22IL3 0.1 0.5 V23IH0 4.5 5.0 5.5 V23IL0 0.1 0.5 V23IH1 4.5 5.0 5.5 V23IL1 0.1 0.5 V23IH2 4.5 5.0 5.5 V23IL2 0.1 0.5 V23IH3 4.5 5.0 5.5 V23IL3 0.1 0.5 VPW0 251 286 321 VPW1 126 143 160 VPW2 117 133 150 VPW3 88 100 112 (Note VA03) 23 Unit Vp-p Vp-p V V V V µs 2003-02-19 TA1318AF Characteristics Vertical free-run frequency Vertical pull-in range Sync input-VD output phase difference Symbol Test Circuit FV0 Test Condition Min Typ. Max 26.02 26.35 26.67 FV1 39.21 39.75 40.30 FV3 52.20 52.98 53.77 FV4 54.24 55.06 55.89 FV5 91.28 92.98 94.69 FV6 107.8 109.9 112.1 FV20 57.0 60.0 63.0 FV21 57.0 60.0 63.0 FV22 57.0 60.0 63.0 FV23 57.0 60.0 63.0 FVPL0 311 321 332 FVPL1 624 643 663 FVPL2 668 689 710 FVPL3 891 918 947 15.75 kHz 9.6 11.8 14.0 31.50 kHz 5.7 6.8 7.9 33.75 kHz 5.3 6.4 7.5 45.00 kHz 4.4 5.2 6.0 (Note VA04) (Note VA05) 24 Unit Hz Hz µs 2003-02-19 TA1318AF Test Conditions and Measuring Method Note HA01 SW Mode Item Sync1/2 input horizontal sync phase Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b a b (1) ↓ ↓ (2) SW19-a and SW21-b. b a (3) Input Signal a (horizontal 33.75 kHz ) to pin 21 (SYNC1-IN). (4) Set sub-address (02) 61. (5) Measure the phase difference S1PH between pin 21 and pin 6 (AFC filter) wave form. Set sub-address (02) 60. (6) SW19-b and SW21-a. (7) Input Signal a (33.75 kHz ) to pin 19 (SYNC2-IN). (8) Set sub-address (02) 01. (9) Measure the phase difference S2PH between pin 19 and pin 6 (AFC filter) wave form. 29.63 µs 0.593 µs Signal a 0.285 V S1PH･S2PH Pin 6 wave form 25 2003-02-19 TA1318AF Note HA02 SW Mode Item HD3 input horizontal sync phase Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) Set sub-address (00) 40 and (02) 82. (2) Input signal b (horizontal 31.5 kHz ) to pin 11 (HD3-IN). (3) Measure the phase difference HD3PH between pin 11 and pin 6 (AFC filter) wave form. 31.75 µs 2.35 µs Signal b 1.5 V HD3PH Pin 6 wave form HA03 Polarity distinction active range c b (1) Set sub-address (00) 70 and (02) 82. (2) Input signal b ((horizontal 31.5 kHz ) to pin 11 (HD3-IN). (3) Decreasing the duty of signal b to 0% (get negative period shorter), measure the duty of Signal b (HD-DUTY1) when the phase between pin 11 and pin 13 (HD1-OUT) change. (4) Increasing the duty of Signal b to 100% (get negative period longer), measure the duty of Signal b (HD-DUTY2) when the phase between pin 11 and pin 13 (HD1OUT) change. 31.75 µs 2.35 µs Signal b 1.5 V B A * duty = A/(A + B) × 100 (%) 26 2003-02-19 TA1318AF Note HA04 SW Mode Item Sync1 input threshold amplitude Sync2 input threshold amplitude Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b a b (1) Set sub-address (00) 0B and (02) 60. ↓ ↓ (2) Input Signal a (33.75 kHz) to pin 21 (SYNC1-IN) b a (3) Measure the sync. tip DC voltage of signal a on pin 21 (SYNC1-IN). (Vsync11) (4) Supply external voltage via 100 kΩ to pin 21 and increase the voltage. (5) Measure the sync. tip DC voltage (Vsync12) when HD-OUT desynchronizes with signal a calculate VthS10. VthS10 = Vsync12 − Vsync11 (6) Set sub-address (00) B1, B2 and B3 and calculate VthS11, VthS12 and VthS13 as well. (7) Calculate VthS20, VthS21, VthS22 and VthS23 against pin 19 (SYNC2-IN) in the same way as 4 to 6. 29.63 µs 0.593 µs Signal a HA05 HD3 input threshold amplitude (synchronization block) c b 0.285 V (1) Set sub-address (00) 70 and (02) 62. (2) Input Signal b (31.5 kHz) to pin 11 (HD3-IN). (3) Increasing the voltage of Signal b from 0 V, measure the voltage of Signal b VthHD3 when HD1-OUT lock. 31.75 µs 2.35 µs Signal b 27 VthHD1 2003-02-19 TA1318AF Note HA06 SW Mode Item HD1 input threshold voltage HD2 input threshold voltage HD3 input threshold voltage (SW block) Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) Set sub-address (00) 40. (2) Input Signal b (31.5 kHz) to pin 3 (HD1-IN). (3) Increasing the voltage of Signal b from 0 V, measure the voltage of Signal b VthHD1 when HD1-OUT lock. (4) Measure the voltage of pin 1 VthHD2. Measure the voltage of pin 11 VthHD3 as well. 31.75 µs 2.35 µs Signal b 28 VthHD1 2003-02-19 TA1318AF Note HA07 SW Mode Item HD output phase adjustment variable range Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) Set sub-address (00) 30. (2) Input Signal b (horizontal period T = 63.5 µs) to pin 11 (HD3-IN). (3) Set sub-address (02) 02. (4) Change form 00 to 7C sub-address (03), then measure the phase change quantity (∆HP0−) of pin 13 (HD1-OUT) wave form. (5) Change form 80 to FC sub-address (03), then measure the phase change quantity (∆HP0+) of pin 13 (HD1-OUT) wave form. (6) When horizontal period of Signal b is T = 31.75 µs measure ∆HP1− and ∆HP1+ as well. (7) When horizontal period of Signal b is T = 29.63 µs measure ∆HP2− and ∆HP2+ as well. (8) When horizontal period of Signal b is T = 22.22 µs measure ∆HP3− and ∆HP3+ as well. T µs 2.35 µs Signal b 1.5 V Pin 15 wave form data (00) ∆HP*− Pin wave form data (7C) (80) ∆HP*+ Pin wave form data (FC) 29 2003-02-19 TA1318AF Note HA08 SW Mode Item Clamp pulse phase/width/level Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) Set sub-address (00) B0. (2) Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN). (3) Set sub-address (02) 02. (4) Measure the clamp pulse phase (CPS0), width (CPW0), output level (CPV0) of pin 12 (CLP-OUT) against Signal a. (5) Set sub-address (02) 12. (6) Measure the clamp pulse phase (CPS1), width (CPW1), output level (CPV1) of pin 12 (SCP-OUT) against Signal a. (7) Input no-signal to pin 11. (8) Measure the clamp pulse phase (CPS2), width (CPW2), output level (CPV2) of pin 12 (SCP-OUT) against pin 13 (HD-OUT). 29.63 µs 2.35 µs Signal a 1.5 V CPS0･CPS1 CPV0･CPV1 Pin 12 wave form CPW0･CPW1 Pin 13 wave form CPS3 Pin 12 wave form CPV3 CPW3 30 2003-02-19 TA1318AF Note HA09 SW Mode Item Delayed HD pulse width Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) Set sub-address (00) 70. (2) Input Signal b (horizontal 31.5 kHz) to pin 11 (HD3-IN). (3) Set sub-address (02) 62. (4) Measure the pulse width (WdHD) of pin 6 (AFC filter) wave form. 31.75 µs 2.35 µs Signal b 1.5 V Wd-HD Pin 6 wave form 31 2003-02-19 TA1318AF Note HB01 SW Mode Item AFC phase detection current Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 OPEN b a b (1) BUS control data preset. (2) Horizontal oscillation frequency is 15.75 kHz (00). (3) SW6 open. Measure the Voltage of pin 6 V6 (no external supply). (4) Connect external supply with pin 6, and supply the voltage (V6). (5) Input signal (below figure) to pin 21 (SYNC1-IN). When INPUT SW is SYNC1-IN , measure V1 and V2 of pin 6 wave form. (6) Supply V6 − 0.1 V and V6 + 0.1 V to pin 6, then measure V3 and V4. (7) Calculate by following equations. ID1 [µA] = (V1 [V] ÷ 1 [kΩ]) × 1000 ID2 [µA] = (V2 [V] ÷ 1 [kΩ]) × 1000 ID3 [µA] = (V3 [V] ÷ 1 [kΩ]) × 1000 ID4 [µA] = (V4 [V] ÷ 1 [kΩ]) × 1000 63.5 µs Pin 21 wave form 0.25 V V1, V3 Pin 6 wave form HB02 VCO oscillation start voltage (1) V2, V4 Increasing the voltage of pin 8 VCC form 2.5V, measure the voltage VVCO when pin 7 appear oscillation wave form. 32 2003-02-19 TA1318AF Note HB03 SW Mode Item HD output pulse width (free-run) Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) BUS control data preset. (2) When horizontal oscillation frequency is 15.75 kHz (00), measure the output pulse width TH00 of pin 13 (HD1-OUT) wave form. (3) When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), measure the output pulse width TH01, TH02, TH03 as well. Pin 13 (HD1OUT) wave form TH HB04 HB05 Horizontal free-run frequency OPEN Horizontal oscillation control sensitivity OPEN b b (1) BUS control data preset. (2) SW6 open. When horizontal oscillation frequency is 15.75 kHz (00), measure the oscillation frequency F00 of pin 13 (HD1-OUT) wave form. (3) When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), measure the oscillation frequency F01, F10, F11 as well. (4) When horizontal oscillation frequency is 15.75 kHz (00) and vertical free-run frequency is (101), measure the oscillation frequency F50 of pin 15 wave form. (1) BUS control data preset. (2) SW6 open. (3) Connect external voltage with pin 6 . Horizontal oscillation frequency is 15.75 kHz (00). Supply V6 (about 6.3 V) + 0.05 V or V6 − 0.05 V to pin 6, then measure the frequency FA, FB of pin 13 (HD1-OUT) wave form. Calculate frequency changing ratio (BH00). BH00 = (FB − FA)/0.1 (4) When horizontal oscillation frequency is 31.5 kHz (01), 33.75 kHz (10), 45 kHz (11), calculate BH01, BH10, BH11 as wall. 33 2003-02-19 TA1318AF Note VA01 SW Mode Item VD1 input threshold voltage VD2 input threshold voltage VD3 input threshold voltage (SW block) Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) Set sub-address (00) 80. (2) Input Signal a (vertical 60 Hz) to pin 4 (VD1-IN). (3) Set sub-address (02) 00. (4) Increasing the voltage of Signal a from 0 V. measure the voltage of Signal b VthVD1 when VD1-OUT lock. (5) Measure VthVD2 and VthVD3 against pin 2 and pin 10 as wall. 16.67 ms 0.12 ms Signal a VA02 VD3 input threshold voltage (synchronization block) c b (1) VthVD1 Set sub-address (00) 70. (2) Input Signal b (vertical 60 Hz) to pin 10 (VD3-IN). (3) Set sub-address (02) 03. (4) Increasing the voltage of Signal b from 0 V, measure the voltage of Signal a VthVD3 when VD1-OUT lock. 16.67 ms 0.12 ms Signal a 34 2003-02-19 TA1318AF Note VA03 SW Mode Item Vertical output pulse width Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN). (2) Set sub-address (02) 02. (3) When sub-addrss (00) is B0, measure the pulse width VPW2 of pin 22 (VD1-OUT) wave form. (4) When sub-addrss (00) is 30, 70, F0, measure the pulse width VPW0, VPW1, VPW3 of pin 22 (VD1-OUT) wave form as well. 29.63 µs 0.593 µs Signal a V period Pin 22 wave form VPW* 35 2003-02-19 TA1318AF Note VA04 SW Mode Item Vertical free-run frequency Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) Input Signal a (horizontal 33.75 kHz) to pin 11 (HD3-IN). (2) Set sub-address (00) B0. (3) When sub-address (02) is 02, 22, 62, 82, A2 or C2, measure the frequency FV0, FV1, FV3, FV4, FV5 or FV6 of pin 22 (VD1-OUT) wave form. (4) Input no-signal to pin 3 (HD1-IN). (5) Set sub-address (02) 42. (6) When sub-address (00) is 30, 70, B0 or F0, measure the frequency FV20, FV21, FV22 or FV23 of pin 22 (VD1-OUT) wave form. 29.63 µs 0.593 µs Signal a 0.285 V V period Pin 22 wave form VPW* 36 2003-02-19 TA1318AF Note VA05 SW Mode Item Vertical pull-in range Test Conditions and Measuring Method (VCC = 9 V, Ta = 25 ± 3°C, unless otherwise specified) S06 S18 S19 S21 c b (1) Input Signal a (horizontal period T = 63.5 µs) to pin 11 (HD3-IN). (2) Set sub-address (02) 02. (3) Set sub-address (00) 30. (4) Input Signal C (vertical period initial T = 1ms) to pin 10 (VD3-IN). Increasing vertical period of Signal C, measure the frequency FVPL0 when pin 22 (VD1-OUT) wave form synchronize with Signal C. (5) Input Signal a (horizontal period T = 31.75 µs) to pin 11 (HD3-IN). (6) Set sub-address (00) 70. (7) Measure FVPL1 as well. (8) Input Signal a (horizontal period T = 29.63 µs) to pin 11 (HD3-IN). (9) Set sub-address (00) B0. (10) Measure FVPL2 as well. (11) Input Signal a (horizontal period T = 22.22 µs) to pin 11 (HD3-IN). (12) Set sub-address (00) F0. (13) Measure FVPL3 as well. horizontal period Tµs 0.593 µs Signal a 1.5 V V period (initial T = 1 ms) 0.25 ms Signal c 1.5 V measuring period Pin 22 wave form 37 2003-02-19 Pin 1 Pin 2 Pin 3 Pin 4 1 kΩ Pin 6 a SW6 b c 38 Pin 7 100 Ω #7 10 11 12 #9 HD2-OUT 13 #10 #13 17 14 #11 Pin 9 Pin 10 Pin 11 Pin 12 16 75 Ω 5.1 kΩ REG. 75 Ω #15 3.9 kΩ 1 kΩ c 5.1 kΩ 5.1 kΩ 5.1 kΩ 100 Ω 100 Ω 3.9 kΩ 0.01 µF 100 µF 0.01 µF 1 kΩ HD1-OUT NC 18 CP-OUT HD3-IN 19 DIGITAL GND 20 NC SDA #16 VD3-IN DAC2 9 VCC 8 21 100 Ω #6 22 100 Ω 7 23 #17 100 Ω 6 #18 0.01 µF 5 SCL NC #19 SCL 1 µF 100 Ω b SW19 100 µF #4 HVCO SYNC2-IN 1 µF 5.1 kΩ a b Pin 20 SW18 SYNC2 360 Ω 24 Address SW 25 DAC1 #20 NC 26 SYNC1-IN #21 CSBLA503 KECZF30 AFC Filter 4 NC 27 NC #22 a M 0.01 µF ○ #3 b SW21 2.2 µF 7.5 kΩ 3 a 68 kΩ #2 Analog GND 28 VD1-OUT 5.1 kΩ 10 kΩ 0.01 µF SYNC1 10 kΩ 2 VD1-IN 29 VD2-OUT #23 100 Ω #1 HD1-IN VD2-IN #24 100 Ω 1 100 Ω 30 DAC3 5V HD2-IN 9V 100 Ω 9V 100 µF 0.01 µF 100 µF TA1318AF Test Circuit TPS1-in 10 µF SDA TPS2-in 10 µF TA1318AF 15 #12 M Mylar capacitor ○ 2003-02-19 TA1318AF Application Circuit 1 (Typical values) HD1-OUT CP-OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDA NC 16 HD3-IN DIGITAL GND 17 VD3-IN HD2-OUT 10 kΩ 10 kΩ NC 18 DAC2 19 VCC 20 NC SYNC2-IN 100 Ω 100 Ω DAC1 SCL SYNC1-IN 21 HVCO NC 22 NC VD1-OUT 23 AFC Filter 24 NC 25 Analog GND 26 VD1-IN 27 HD1OUT HD1-IN 28 HD2OUT SDA VD2-IN 29 Address SW 10 kΩ SCL HD2-IN 30 VD2-OUT 10 kΩ SYNC1SYNC2DAC1 IN IN DAC3 15 kΩ VD1OUT 1 µF VD2OUT DAC3 1 µF 0.01 µF TA1318AF 0.01 µF 360 Ω 100 µF DAC2 2.2 µF 7.5 kΩ HD2-IN VD2-IN HD1-IN VD1-IN M 0.01 µF ○ 100 µF 9V 39 VD3-IN HD3-IN CP-OUT CSBLA503KECZF30 M Mylar capacitor ○ 2003-02-19 TA1318AF Application Circuit 2 (How to measure H/V frequency) To measure H/V frequency of signal 2 (fH2: unknown) correctly, use two separated input terminals as the following figure. One is for frequency measuring (SYNC2-in) and the other is for the AFC (SYNC1-IN). And measure H/V frequency of signal 2 (fH2: unknown) on condition that AFC is stable (AFC locks in signal 1 (fH1: known).) or that AFC is free-run when SYNC1-IN is no-signal. Signal 1 (fH1: known) Signal 2 (fH2: unknown) Signal 1 AFC SYNC1-IN for H-AFC BUS READ Internal pulse (A) H/V FREQ COUNTER Signal 2 SYNC2-IN for H/V freq. counter TA1318AF This IC’s H/V frequency counting is done by internal pulse (A) which is made in AFC circuit. So, if AFC circuit doesn’t lock in the regular frequency, the frequency of pulse (A) will not be correct and the H/V frequency data will not be showed correct data. Decision algorithm of H/V frequency detection (detection range, detection times and so on) should be determined under consideration the factors such as signal strength, existence of ghost signal, H-AFC stability, I2C BUS data transmission and so on via prototype TV set evaluation. 40 2003-02-19 TA1318AF Package Dimensions Weight: 0.63 g (typ.) 41 2003-02-19 TA1318AF RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 42 2003-02-19